Detection device for semiconductor chip

Abstract

The utility model relates to the technical field of chip detection, and discloses a detection device for a semiconductor chip, which solves the problems in the background technology and comprises a working table, a vacuum chamber is arranged on the working table, a vacuum machine is arranged at the top of the vacuum chamber, an anti-static bottom plate is arranged at the bottom of the vacuum chamber, and the anti-static bottom plate is arranged on the working table. Chip detection assemblies are arranged on the anti-static bottom plate, chip clamping grooves are formed between the chip detection assemblies, the anti-static bottom plate is connected with a grounding wire, the grounding wire penetrates through the side wall of the vacuum chamber and is connected with the ground, and an ion fan is arranged in the vacuum chamber. Static charges are neutralized in time, and the chip is prevented from being damaged by electrostatic discharge in the detection process, so that the performance and reliability of the chip are guaranteed.

Description

Technical Field

[0001] This utility model belongs to the field of chip testing technology, specifically a testing device for semiconductor chips. Background Technology

[0002] With the rapid development of semiconductor technology, the integration and complexity of chips are constantly increasing, and the process nodes are gradually moving towards smaller nanometer levels. However, the miniaturization and high integration of chips also make them more sensitive to the impact of the external environment, especially to electrostatic discharge.

[0003] Existing semiconductor chip testing devices are mainly used to test the electrical performance, functionality, and reliability of chips to ensure that they meet design specifications and quality requirements. However, many traditional testing devices do not fully consider electrostatic discharge protection in their design, which can easily lead to electrostatic accumulation and discharge during the testing process, causing irreversible damage to the chip, resulting in performance degradation, functional failure, or even complete damage. To address this, we propose a semiconductor chip testing device. Utility Model Content

[0004] To address the problems mentioned in the background art, this utility model provides the following technical solution: a semiconductor chip detection device, comprising a workbench, a vacuum chamber disposed on the workbench, a vacuum machine disposed on the top of the vacuum chamber, an anti-static base plate disposed on the bottom of the vacuum chamber, chip detection components disposed on the anti-static base plate, chip slots disposed between the chip detection components, the anti-static base plate being connected to a grounding wire, the grounding wire passing through the side wall of the vacuum chamber and connected to the ground, and an ion fan disposed inside the vacuum chamber.

[0005] Preferably, the chip detection assembly includes two first guide rails symmetrically arranged on an anti-static base plate. Sliding members are slidably arranged on both first guide rails, and the two sliding members are connected by a second guide rail. A detection group is slidably arranged on the second guide rail, and a probe is arranged at the bottom of the detection group. The dual guide rail structure enables precise positioning of the detection group, ensuring that the probe can accurately contact the test point of the chip, thereby improving detection accuracy and efficiency.

[0006] Preferably, the chip slot is positioned between the two first guide rails, optimizing the chip slot's position design and enabling the testing group to more flexibly cover all test points of the chip, thereby improving the comprehensiveness and efficiency of the testing.

[0007] Preferably, the vacuum chamber is equipped with a control panel, which is electrically connected to the vacuum machine, sliding component, detection group, and ion fan, providing integrated control functions, simplifying the operation process, and improving the automation level and ease of operation of the detection device.

[0008] Preferably, the workbench is equipped with casters at the bottom to enhance the flexibility of the device and facilitate movement and adjustment of its position between different workplaces.

[0009] Preferably, the front wall of the vacuum chamber is provided with an observation window, which is made of anti-static glass, providing a visual operating interface to facilitate operators to monitor the detection process in real time, while ensuring that the observation window will not introduce static electricity problems.

[0010] Compared with the prior art, the beneficial effects of this utility model are:

[0011] During operation, the chip is first placed into the chip slot within the vacuum chamber. The vacuum machine is then activated to evacuate the air from the chamber, achieving the preset vacuum level. This vacuum environment is maintained until the test is complete. The chip is then indirectly placed on an anti-static base plate, and static charge is conducted to the ground via a grounding wire. An ion fan is activated to continuously release positive and negative ions, neutralizing any remaining static charge in the vacuum chamber. After the chip is secured in the chip slot, the sliding parts of the first and second guide rails are adjusted via the control panel to move the probe of the testing group above the chip's test point. The probe descends and contacts the chip's pads, transmitting test signals and collecting response data. By sliding the guide rails, the probe can cover test points at different locations on the chip, achieving comprehensive testing. The control panel integrates the operation of all equipment, automating the testing process. This effectively prevents static electricity accumulation, promptly neutralizes static charge, and avoids damage to the chip from electrostatic discharge during testing, thus ensuring the chip's performance and reliability. Attached Figure Description

[0012] The accompanying drawings are provided to further illustrate the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention, but do not constitute a limitation thereof. In the drawings:

[0013] Figure 1 This is a front view of the overall structure of this utility model;

[0014] In the diagram: 1. Workbench; 2. Vacuum chamber; 3. Vacuum machine; 4. First guide rail; 5. Second guide rail; 6. Detection group; 7. Chip slot; 8. Grounding wire; 9. Ionizing fan; 10. Control panel; 11. Casters. Detailed Implementation

[0015] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0016] Depend on Figure 1 The present invention includes a workbench 1, a vacuum chamber 2 on the workbench 1, a vacuum machine 3 on the top of the vacuum chamber 2, an anti-static base plate on the bottom of the vacuum chamber 2, a chip detection assembly on the anti-static base plate, chip slots 7 between the chip detection assemblies, the anti-static base plate being connected to a grounding wire 8, the grounding wire 8 passing through the side wall of the vacuum chamber 2 and connecting to the ground, and an ion fan 9 inside the vacuum chamber 2.

[0017] The chip testing assembly includes two first guide rails 4, which are symmetrically arranged on an anti-static base plate. Sliding elements are slidably mounted on both first guide rails 4, and the two sliding elements are connected by a second guide rail 5. A testing group 6 is slidably mounted on the second guide rail 5, and a probe is mounted at the bottom of the testing group 6. The dual guide rail structure enables precise positioning of the testing group 6, ensuring that the probe can accurately contact the test points of the chip, thereby improving testing accuracy and efficiency.

[0018] The chip slot 7 is positioned between the two first guide rails 4. The optimized position design of the chip slot 7 allows the detection group 6 to more flexibly cover all test points of the chip, improving the comprehensiveness and efficiency of the detection.

[0019] A control panel 10 is installed on the vacuum chamber 2. The control panel 10 is electrically connected to the vacuum machine 3, the sliding component, the detection group 6, and the ion fan 9, providing integrated control functions, simplifying the operation process, and improving the automation level and ease of operation of the detection device.

[0020] The bottom of the workbench 1 is equipped with casters 11, which enhances the flexibility of the device and makes it easy to move and adjust its position between different workplaces.

[0021] The front wall of vacuum chamber 2 is equipped with an observation window made of anti-static glass, which provides a visual operating interface, making it convenient for operators to monitor the testing process in real time, while ensuring that the observation window will not introduce static electricity.

[0022] Working Principle: During operation, the chip is first placed into the chip slot 7 inside the vacuum chamber 2. The vacuum machine 3 is started to evacuate the air from the vacuum chamber 2 to achieve the preset vacuum level. The vacuum environment is maintained until the test is completed. The chip is then placed indirectly on the anti-static base plate. The static charge is conducted to the ground through the grounding wire 8. The ion fan 9 is started to continuously release positive and negative ions to neutralize the residual static charge in the vacuum chamber 2. After the chip is fixed in the chip slot 7, the sliding parts of the first guide rail 4 and the second guide rail 5 are adjusted through the control panel 10 to move the probe of the detection group 6 above the chip test point. The probe descends and contacts the chip pad, transmitting test signals and collecting response data. Through the sliding of the guide rails, the probe can cover the test points at different locations on the chip, achieving comprehensive testing. The control panel 10 integrates the operation of all equipment, automating the testing process. This effectively prevents static accumulation, neutralizes static charge in a timely manner, and avoids damage to the chip from electrostatic discharge during the testing process, thereby ensuring the chip's performance and reliability.

[0023] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0024] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A testing device for semiconductor chips, comprising a stage (1), characterized in that: A vacuum chamber (2) is provided on the workbench (1). A vacuum machine (3) is provided on the top of the vacuum chamber (2). An antistatic base plate is provided at the bottom of the vacuum chamber (2). A chip detection assembly is provided on the antistatic base plate. A chip slot (7) is provided between the chip detection assemblies. The antistatic base plate is connected to a grounding wire (8). The grounding wire (8) passes through the side wall of the vacuum chamber (2) and connects to the ground. An ion fan (9) is provided inside the vacuum chamber (2).

2. The detection device for semiconductor chips according to claim 1, characterized in that: The chip detection assembly includes two first guide rails (4), which are symmetrically arranged on an anti-static base plate. Sliding members are slidably arranged on both first guide rails (4), and the two sliding members are connected by a second guide rail (5). A detection group (6) is slidably arranged on the second guide rail (5), and a probe is provided at the bottom of the detection group (6).

3. The detection device for semiconductor chips according to claim 2, characterized in that: The chip slot (7) is located between the two first guide rails (4).

4. The detection device for semiconductor chips according to claim 3, characterized in that: The vacuum chamber (2) is equipped with a control panel (10), which is electrically connected to the vacuum machine (3), the sliding component, the detection group (6), and the ion fan (9).

5. The detection device for semiconductor chips according to claim 4, characterized in that: The bottom of the workbench (1) is equipped with casters (11).

6. The detection device for semiconductor chips according to claim 5, characterized in that: The front wall of the vacuum chamber (2) is provided with an observation window, which is made of anti-static glass.

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