Chip module and electronic equipment

Abstract

The utility model relates to the field of chip packaging, in particular to a chip module and electronic equipment. The chip module comprises a printed circuit board, a chip packaging structure and a capacitor, the printed circuit board comprises a first surface, a second surface and a plurality of through holes penetrating through the first surface and the second surface, the first surface and the second surface are oppositely arranged, the chip packaging structure faces the first surface, the chip packaging structure comprises a power supply gate ball area, and the power supply gate ball area is provided with a plurality of power supply gate balls. The chip packaging structure is connected with the plurality of through holes through part of the power grid balls, the capacitor faces the second surface, and part of the capacitor crosses an area not connected with the through holes and is connected with the printed circuit board. According to the chip module provided by the utility model, the second surface of the printed circuit board is provided with a space for arranging a large-size high-capacity capacitor, and the capacitor can provide timely and sufficient charge supply, so that voltage fluctuation is stabilized, and transient alternating voltage noise on a power supply plane path is suppressed.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging, specifically to a chip module and electronic device. Background Technology

[0002] With the continuous development of integrated circuit technology, the operating frequency and integration density of chips are constantly increasing. The power supply required for devices under high-speed operation and full load conditions not only demands balanced current distribution but also good resistance to transient voltage disturbances. In traditional high-density packaging (such as BGA packaging), a large number of power balls are arranged at the bottom of the chip. These power balls are connected to the power plane of the printed circuit board (PCB) through vias to achieve normal power supply to the chip. However, under current design and manufacturing processes, the following problems often occur: First, during normal operation or full load operation, some areas of the packaging substrate and PCB corresponding to power balls may experience increased current density due to a small number or uneven distribution of vias. Excessive local current density can easily cause local overheating of the packaging substrate, resulting in thermal imbalance and thus deformation or warping of the packaging substrate. Furthermore, high current density may also lead to electromigration, affecting the long-term reliability and lifespan of the chip. Second, during high-speed or full-load operation, transient AC voltage fluctuations inevitably occur on the chip's power plane. Normally, to suppress this type of noise, bypass capacitors or decoupling capacitors need to be added near the chip's power supply port. However, when vias and corresponding pads are distributed close to the back of the circuit board, it is often difficult to add large-size, high-capacity capacitors in this area, making it difficult to effectively improve transient voltage noise.

[0003] The aforementioned problems are particularly pronounced in large-scale, high-density devices. If current distribution cannot be improved during the design and manufacturing stages to reduce excessive current density and thermal imbalance, it will be difficult to fundamentally improve the long-term stability and reliability of the chip system. Similarly, if sufficient space cannot be provided on the back of the circuit board to accommodate large-size, high-capacity capacitors, it will be difficult to effectively improve the transient power supply performance of the chip from a power integrity perspective. Utility Model Content

[0004] The purpose of this invention is to at least solve the problem that transient voltage noise is difficult to improve. This purpose is achieved through the following technical solution:

[0005] The first aspect of this utility model provides a chip module, comprising:

[0006] A printed circuit board, the printed circuit board including a first side and a second side arranged opposite to each other and a plurality of through holes passing through the first side and the second side;

[0007] A chip packaging structure is disposed facing the first surface. The chip packaging structure includes a power gate ball region, on which a plurality of power gate balls are disposed. The chip packaging structure is connected to the plurality of through holes through a portion of the power gate balls.

[0008] A capacitor is disposed facing the second surface, and a portion of the capacitor spans the area where the through hole is not provided and is connected to the printed circuit board.

[0009] According to the chip module of this utility model, by providing areas on the printed circuit board without power gate balls, through-holes are not required in these areas, allowing space on the second side of the printed circuit board to accommodate large-size, high-capacity capacitors. The addition of these large-size, high-capacity capacitors ensures timely and sufficient charge replenishment when the chip is operating at full load or when rapid current changes occur during power-on, thereby stabilizing voltage fluctuations and suppressing transient AC voltage noise on the power plane. This significantly improves the power quality during chip operation, meeting the stringent power integrity requirements of high-speed, high-density integrated circuits.

[0010] In addition, the chip module according to this utility model may also have the following additional technical features:

[0011] In some embodiments of this utility model, the printed circuit board is further provided with a power supply, the direction of the power supply to the chip package structure is the current direction, and along the current direction, the chip package structure includes at least two power gate ball regions.

[0012] In some embodiments of this utility model, the chip packaging structure includes an interconnected packaging substrate and a chip die, the power gate ball region is disposed on the packaging substrate, and along a direction perpendicular to the packaging substrate, the projection surface of the chip die on the packaging substrate coincides with the power gate ball region.

[0013] In some embodiments of this utility model, the chip die is divided into at least two chip regions, and the at least two chip regions and the at least two power gate ball regions are arranged in a one-to-one correspondence.

[0014] In some embodiments of this utility model, the through hole is divided into at least two through hole regions, and the at least two through hole regions are respectively arranged in a one-to-one correspondence with at least two power grid ball regions. In this case, the plurality of through holes in at least one through hole region are connected to all the power grid balls in its corresponding power grid ball region. In this case, all the through holes in at least one through hole region are connected to the power grid balls.

[0015] In some embodiments of this utility model, the through hole and part of the power grid ball are provided in a one-to-one correspondence.

[0016] In some embodiments of this invention, the capacitor is connected to the second surface via a solder pad.

[0017] In some embodiments of this utility model, there are multiple capacitors, and the multiple capacitors are arranged at intervals.

[0018] The second aspect of this invention provides an electronic device comprising the aforementioned chip module. Attached Figure Description

[0019] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0020] Figure 1 A schematic diagram of the structure of a chip module according to the first embodiment of the present invention is shown.

[0021] Figure 2 A schematic diagram of the structure of a chip module according to the second embodiment of the present invention is shown.

[0022] Figure 3 This diagram schematically illustrates a local current transport path on a chip, packaging substrate, or circuit board in the prior art.

[0023] Figure 4 A schematic diagram of the current path structure during chip die and packaging substrate slicing according to an embodiment of the present invention is shown.

[0024] Figure 5 A schematic diagram of the current path through the first power grid ball region according to an embodiment of the present invention is shown.

[0025] Figure 6 A schematic diagram of the current path through the second power grid ball region according to an embodiment of the present invention is shown.

[0026] Figure 7 A schematic diagram illustrating chip region segmentation according to an embodiment of the present invention is shown.

[0027] Figure 8 A schematic diagram of the power grid ball segmentation of the packaging substrate according to an embodiment of the present invention is shown.

[0028] The attached figures are labeled as follows:

[0029] 10. Bare chip die; 11. First chip area; 12. Second chip area;

[0030] 20. Packaging substrate; 21. First power gate ball region; 22. Second power gate ball region;

[0031] 30. Printed circuit board; 31. Power supply plane; 311. Power plane; 312. Ground plane; 32. Power supply;

[0032] 40. Power grid ball; 50. Power ball protrusion; 60. Capacitor. Detailed Implementation

[0033] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0034] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0035] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0036] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "over," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure is flipped, an element described as "below other elements or features" or "below other elements or features" would subsequently be oriented "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations.

[0037] like Figures 1 to 8 As shown, according to an embodiment of the present invention, a chip module is proposed. The chip module includes a printed circuit board 30, a chip package structure, and a capacitor 60. The printed circuit board 30 includes a first side and a second side arranged opposite to each other, and a plurality of through holes penetrating the first side and the second side. The chip package structure is disposed facing the first side and includes a power gate ball area with power gate balls on it. The chip package structure is connected to some of the through holes through some of the power gate balls 40. The capacitor 60 is disposed facing the second side, and some of the capacitors 60 cross another part of the area without through holes and are connected to the printed circuit board 30.

[0038] According to the chip module of this utility model, by providing areas on the printed circuit board 30 that are not connected to the power grid ball 40, through-holes are not required in these areas, allowing space on the second side of the printed circuit board 30 to accommodate a large-size, high-capacity capacitor 60. The addition of this large-size, high-capacity capacitor 60 ensures timely and sufficient charge replenishment when the chip is operating at full load or when rapid current changes occur during power-on, thereby stabilizing voltage fluctuations and suppressing transient AC voltage noise on the power plane. This significantly improves the power integrity of the chip module during operation, meeting the stringent power integrity requirements of high-speed, high-density integrated circuits.

[0039] In the prior art, the number of power gate balls 40 in a chip package structure is given, and the number of through holes on the printed circuit board 30 is correspondingly provided to the given number of power gate balls 40 in the chip package structure. However, in this embodiment, the number of through holes on the printed circuit board 30 can be adjusted according to requirements. Specifically, in this embodiment, fewer through holes can be provided depending on the required number of power gate balls 40, so that some power gate balls 40 are not connected to through holes. This saves space on the second side of the printed circuit board 30, and the saved space can be used to connect large-size, high-capacity capacitors, thereby improving the power integrity of the system due to the introduction of large-size, high-capacity capacitors.

[0040] In some embodiments, the printed circuit board 30 also includes a power supply 32, with the direction from the power supply 32 to the chip package structure being the current direction. Along the current direction, the chip package structure includes at least two power gate ball regions. By partitioning the power gate ball regions, the number of power gate balls 40 actually connected to the power plane of the printed circuit board 30 in certain power gate ball regions can be selectively reduced while satisfying current distribution balance and reliability. This flexible configuration allows designers to dynamically optimize the number of power gate balls 40 connections based on real-time requirements and the current ratio to path impedance ratio. This not only meets power quality and reliability requirements but also allows for flexible allocation for different chip application scenarios, improving the scalability and customizability of the design.

[0041] It is understood that the chip packaging structure includes an interconnected packaging substrate 20 and a die 10. A power gate ball region is disposed on the packaging substrate 20, and along a direction perpendicular to the packaging substrate 20, the projection surface of the die 10 on the packaging substrate 20 coincides with the power gate ball region. Firstly, by directly placing the power gate ball region below the corresponding projection area of ​​the die 10, the power transmission path from the packaging substrate 20 to the die 10 is significantly shortened. A shorter current path reduces parasitic inductance and resistance, thereby reducing transient voltage drop and noise, and improving power integrity and electrical performance under high-speed operation. Secondly, the alignment of the power gate ball region with the chip region makes the current distribution from the packaging substrate 20 to the chip more intuitive and balanced. By combining the aforementioned design method of partitioning along the current direction and precisely matching the number of power gate balls 40, the current density and heat distribution of each partition can be effectively controlled. This avoids electron migration problems caused by excessively high current densities in certain areas, while mitigating localized heating and stress concentration, improving thermal management, and reducing the risk of substrate warpage. Finally, a corresponding power gate ball area is set directly below the chip die 10, and a large-value capacitor 60 is arranged in the back space of the through-hole not connected to the power gate ball 40. This provides additional energy reserves for the chip more directly and quickly when it is powered on or under rapid changes in full load. This makes transient current compensation more efficient, helps to smooth voltage fluctuations, and suppresses high-frequency noise.

[0042] Furthermore, the die 10 is divided into at least two chip regions, and each of these chip regions corresponds to at least two power gate ball regions. By functionally partitioning the die 10 and making these chip regions correspond one-to-one with the power gate ball regions on the packaging substrate 20, the current demand of each chip region can be more directly matched with the corresponding power gate ball region. Using the aforementioned method (precisely configuring the number of power gate balls 40 in each power gate ball region and analyzing impedance ratios), independent control of the output current of each power gate ball region can be achieved. This allows for more balanced power distribution during the design phase, thereby avoiding problems such as electron migration and localized overheating caused by current concentration in certain power gate ball regions.

[0043] Understandably, the vias are divided into at least two via regions, each corresponding to at least two power gate ball regions. At least one via region's vias are connected to all the power gate balls 40 of its corresponding power gate ball region. All vias in at least one via region are connected to all the power gate balls 40 of its corresponding power gate ball region, making the power gate ball region corresponding to that via region a stable core power supply point, providing sufficient and stable current output to a specific functional area or core circuit module of the chip. In other via regions corresponding to power gate ball regions, the strategy of leaving some power gate balls 40 unconnected to the printed circuit board 30 allows designers to flexibly adjust the effective current carrying capacity of each region, thereby achieving a more balanced current distribution in the overall power network, reducing the risk of electron migration caused by excessively high local current density, and improving long-term reliability and power integrity. Furthermore, for via regions that do not connect all power gate balls, the space on the back of the corresponding printed circuit board 30 is not provided with vias, thus allowing for flexible placement of large-size, high-capacity capacitors 60. These large-size, high-capacity capacitors 60 provide additional transient current reserves during power-up and rapid changes in full load, significantly reducing power supply ripple and transient voltage noise, ensuring that high-speed devices maintain stable voltage and performance under harsh operating conditions.

[0044] In a specific embodiment, the chip module of this implementation includes a printed circuit board 30, a packaging substrate 20, and a die 10. The printed circuit board 30 has a power supply plane 31, which includes a power plane 311 and a ground plane 312. The power plane 311 is used for power transmission. The printed circuit board 30 supplies power to the packaging substrate 20 through power gate balls 40, and the packaging substrate 20 supplies power to the die 10 through power ball bumps 50. The power supply 32 of the printed circuit board 30 is located on one side of the die 10 and the packaging substrate 20. The power supply 32 transmits current to the packaging substrate 20 through the power supply plane 31. The current path in the packaging substrate 20 is from the side closer to the power supply 32 to the side farther away from the power supply 32.

[0045] It is understandable that the chip die 10 is divided into two equally divided chip regions, namely the first chip region 11 and the second chip region 12. The core power and ground regions of the packaging substrate 20 are divided into two equally divided regions, namely the first power gate ball region 21 and the second power gate ball region 22. The first power gate ball region 21 is closer to the power supply 32, and the second power gate ball region 22 is farther away from the power supply 32. Therefore, the current path in the packaging substrate 20 is from the first power gate ball region 21 to the second power gate ball region 22.

[0046] Understandably, since the first chip region 11 and the first power gate region 21 are close to the power supply 32, the current of the first chip region 11 is mainly supplied by the first power gate region 21. Similarly, the current of the second chip region 12 is supplied by both the first power gate region 21 and the second power gate region 22.

[0047] It is understandable that the core power supply area of ​​the packaging substrate 20 is basically the same size as that of the chip die 10. From a top view, the core power supply area of ​​the packaging substrate 20 and the chip die 10 basically overlap.

[0048] like Figures 3 to 6 The diagram illustrates the current flow path, omitting the capacitor 60 and ground plane beneath the printed circuit board 30. Further, based on the aforementioned chip module, the steps for determining the required number of vias for each of the first power gate ball region 21 and the second power gate ball region 22 include:

[0049] Step 1: Since the current consumed by each circuit module on the chip is different, we count the types and quantities of circuit modules contained in each region of the first chip region 11 and the second chip region 12, as well as the current consumed by each type of circuit module. Then, we calculate the total current I of the first chip region 11. A The total current I consumed by the second chip region 12 B .

[0050] Step 2: The current flowing through the first power gate ball region 21 needs to supply not only the current to the first chip region 11 of the chip, but also the current to the second chip region 12 of the die 10. That is, I1 = I 1A +I 1B (Formula 1). Where, I 1A For the current flowing through the first power gate ball region 21 to the first chip region 11, I 1B I1 is the current flowing from the first power gate region 21 to the second chip region 12, and I1 is the total current flowing through the first power gate region 21.

[0051] Step 3: Since the power supply 32 is located on the right side of the chip module, the current in the first chip region 11 is already almost entirely supplied by the first power gate ball region 21, which is closer to the power supply. Therefore, the current flowing through the second power gate ball region 22 will not supply the current in the first chip region 11, but only the current in the second chip region 12. That is, I2 = I 2B (Formula 2), where I 2B I2 is the current flowing through the second power gate region 22 to the second chip region 12, and I3 is the total current flowing through the second power gate region 22.

[0052] Step 4: Based on steps 1 to 3, the following formula can be derived.

[0053] The current in the first chip region 11 is provided only by a portion of the current flowing through the first power gate ball region 21, i.e., I A =I 1A (Formula 3);

[0054] The current in the second chip region 12 is the sum of the partial currents flowing through the first power gate region 21 and the second power gate region 22, i.e., I B =I 1B +I 2B (Formula 4)

[0055] Step 5: Current I flowing through the second chip region 12 B It consists of two branch currents, namely the current I flowing from the first power gate ball region 21 to the second chip region 12. 1B and the current I flowing through the second power gate ball region 22 to the second chip region 12 2B The magnitudes of these two branch currents are determined by Ohm's law, i.e., I 2B / I 1B =R 1B / R 2B And because I B =I 1B +I 2B We obtain the magnitudes of the two branch currents as follows:

[0056]

[0057] Step 6: Based on formulas (I), (III), and (V) above, we obtain the current flowing through the first power grid ball region 21 as follows:

[0058] Step 7: Based on formulas (II) and (VI) above, we obtain the current flowing through the second power grid ball region 22 as follows:

[0059] Step 8: Calculate or simulate the resistance (R) of each chip region through the first power gate ball region 21 and the second power gate ball region 22 to the second chip region 12 using circuit simulation software (EDA tool) or theoretical calculation. 1B and R 2B Among them, R 1B R is the resistor connecting the first power gate ball region 21 to the second chip region 12. 2B The resistor is the resistor connecting the second power gate ball region 22 to the second chip region 12.

[0060] Step 9: Based on the above formulas (vii) and (viii) and the resistance value obtained in step 8, calculate the total currents I1 and I2 through the first power grid ball region 21 and the second power grid ball region 22, respectively.

[0061] Step 10: Divide the total currents I1 and I2 flowing through the first power gate region 21 and the second power gate region 22 by the number of power gate balls N1 and N2 required to connect the vias in each power gate region, respectively. This yields the average current flowing through each power gate ball in each power gate region, i.e., I1average = I1 / N1 and I2average = I2 / N2. It is worth noting that the number of power gate balls 40 connecting the vias of the printed circuit board 30 is less than or equal to the number of power gate balls 40 of the given chip, i.e., N1 ≤ N. 10 and N2≤N 20 (Formula 9), where N 10 and N 20 It is the number of power gate balls in the first power gate ball region 21 and the second power gate ball region 22 of the given package substrate 20.

[0062] Step 11: According to the design requirements, the current of the power grid ball 40 in each power grid ball area needs to be equal or approximately equal, I1_average=I1 / N1=I2_average=I2 / N2 (Formula 10);

[0063] Substituting formulas (vii) and (viii) into formula (x), we obtain the relationship between the number N1 and N2 of the power gate balls 40 connected to the printed circuit board 30 through the vias in each power gate ball region. It should be noted that the number of power gate balls 40 connected to the vias is the same as the required number of vias.

[0064]

[0065] Step 12: Simplify formula (XI). We obtain the relationship between the number of through holes N1 and N2 required for each power grid ball region and the corresponding through hole area.

[0066]

[0067] Formula (12) shows the relationship between the required number of through-holes N1 / N2 and the current ratio I of the first chip region 11 and the second chip region 12. A / I B It is also related to the ratio R between the resistance of the first power gate ball region 21 and the second power gate ball region 22 leading to the second chip region 12. 2B / R 1B related.

[0068] Step 13: If the ratio N1 / N2 obtained from formula (XII) is greater than 1, it means that the number of through holes required for the through hole region corresponding to the first power gate ball region 21 is greater than the number of through holes required for the through hole region corresponding to the second power gate ball region 22. Therefore, take the upper limit N1. 10 Then, the required number of through holes for the second power grid ball region 22 is obtained according to formula (xii). That is,

[0069]

[0070] For example:

[0071] Assume N 10 =80, N 20 =50, N1 / N2 = 2:1, then we get N1 = 80, N2 = 40. The remaining 10 power grid balls 40 in the second power grid ball region 22 are not connected to through holes. That is, the number of through holes in the through hole region corresponding to the first power grid ball region 21 is 80, and the number of through holes in the through hole region corresponding to the second power grid ball region 22 is 40. According to the normal design standard, 50 through holes need to be opened in the through hole region corresponding to the second power grid ball region 22 to accommodate 50 power grid balls 40. Now, through calculation, it is found that the number of power grid balls 40 required for the second power grid ball region 22 is only 40. Therefore, the number of through holes in the through hole region corresponding to the second power grid ball region 22 can also be reduced by 40. Thus, 10 fewer through holes can be opened in the through hole region corresponding to the second power grid ball region 22 on the printed circuit board 30. Furthermore, space on the second side of the printed circuit board 30 is saved for installing large-size, high-capacity capacitors.

[0072] Assume N 10 =50, N 20 =80, N1 / N2=2:1, then we get N1=50, N2=25. The remaining 55 power grid balls 40 in the second power grid ball area 22 that are not connected to the through holes mean that 55 fewer through holes can be opened on the printed circuit board 30. Furthermore, it saves space on the second side of the printed circuit board 30 for installing large-size, high-capacity capacitors.

[0073] Step 14: If the ratio N1 / N2 obtained from formula (XII) is less than 1, it means that the number of through holes required for the through hole region corresponding to the first power gate ball region 21 is less than the number of through holes required for the through hole region corresponding to the second power gate ball region 22. Therefore, take the upper limit N2. 20 Then, the required number of through holes in the first power grid ball region is obtained according to formula (12). That is,

[0074]

[0075] For example:

[0076] Assume N 10 =80, N 20 =50, N1 / N2=1:2, then we get N1=25, N2=50. The remaining 55 power grid balls 40 in the first power grid ball area 21 that are not connected to the through holes mean that 55 fewer through holes can be opened on the printed circuit board 30. Furthermore, it saves space on the second side of the printed circuit board 30 for installing large-size, high-capacity capacitors.

[0077] Assume N 10 =50, N 20 =80, N1 / N2=1:2, then we get N1=40, N2=80. The remaining 10 power grid balls in the first power grid ball area 21 that are not connected to the through holes mean that 10 fewer through holes can be opened on the printed circuit board 30. Furthermore, it saves space on the second side of the printed circuit board 30 for installing large-size, high-capacity capacitors.

[0078] Step 15: Depending on the required precision, steps 1 to 14 can be repeated to further divide the first power grid ball region 21 and the second power grid ball region 22 into two equal parts to obtain a more precise number of power grid balls 40 that need to be connected to the printed circuit board 30, that is, the number of through holes that need to be opened on the printed circuit board 30.

[0079] In some embodiments, the through-holes and portions of the power gate balls 40 are arranged in a one-to-one correspondence. When each power gate ball corresponds to a separate through-hole, the current path from the package substrate 20 to the internal power plane of the printed circuit board 30 is clear, concise, and one-to-one. This reduces the parasitic parameter differences between the power gate balls, making the current distribution more symmetrical and balanced, thereby improving the power integrity of the entire platform.

[0080] In some implementations, there are multiple capacitors 60, which are spaced apart. This spacing reduces parasitic coupling and electromagnetic interference between adjacent capacitors 60, allowing each capacitor 60 to perform its energy storage and decoupling functions more independently, thereby improving the power quality and signal integrity of the entire power network.

[0081] In some implementations, capacitor 60 is connected to the second side via pads. Directly connecting capacitor 60 to the second side via pads simplifies and streamlines the electrical path between capacitor 60 and the power / ground plane. This significantly reduces contact resistance and wiring length, improves the response speed of capacitor 60 under high-frequency or transient load changes, and reduces voltage noise and rapid drops caused by parasitic inductance and resistance.

[0082] This embodiment also provides an electronic device including the aforementioned chip module. This electronic device can be various types of smart terminals, computing devices, or communication devices, such as smartphones, tablets, laptops, servers, network routers, switches, and various high-performance computing and communication systems. By employing the aforementioned chip module, the power supply design and optimization method provided in this embodiment can ensure power quality and system reliability in various complex application scenarios.

[0083] The above description is merely a preferred embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A chip module, characterized in that, include: A printed circuit board, the printed circuit board including a first side and a second side arranged opposite to each other and a plurality of through holes passing through the first side and the second side; A chip packaging structure is disposed facing the first surface. The chip packaging structure includes a power gate ball region, on which a plurality of power gate balls are disposed. The chip packaging structure is connected to the plurality of through holes through a portion of the power gate balls. A capacitor is disposed facing the second surface, and a portion of the capacitor spans the area where the through hole is not provided and is connected to the printed circuit board.

2. The chip module according to claim 1, characterized in that, The printed circuit board is also provided with a power supply, and the direction of the power supply to the chip package structure is the current direction. Along the current direction, the chip package structure includes at least two power gate ball regions.

3. The chip module according to claim 2, characterized in that, The chip packaging structure includes an interconnected packaging substrate and a chip die. The power gate ball region is disposed on the packaging substrate. Along a direction perpendicular to the packaging substrate, the projection surface of the chip die on the packaging substrate coincides with the power gate ball region.

4. The chip module according to claim 3, characterized in that, The chip die is divided into at least two chip regions, and the at least two chip regions and the at least two power gate ball regions are arranged in a one-to-one correspondence.

5. The chip module according to claim 4, characterized in that, The through hole is divided into at least two through hole regions, and the at least two through hole regions are respectively arranged in a one-to-one correspondence with the at least two power grid ball regions, wherein the plurality of through holes in at least one through hole region are connected to all the power grid balls in its corresponding power grid ball region.

6. The chip module according to any one of claims 1 to 5, characterized in that, The through holes and a portion of the power grid balls are provided in a one-to-one correspondence.

7. The chip module according to any one of claims 1 to 5, characterized in that, The capacitor is connected to the second side via a solder pad.

8. The chip module according to any one of claims 1 to 5, characterized in that, The number of capacitors is multiple, and the multiple capacitors are arranged at intervals.

9. An electronic device, characterized in that, Includes the chip module according to any one of claims 1 to 8.

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