Power semiconductor module

Abstract

The utility model belongs to the technical field of power semiconductors, and particularly relates to a power semiconductor module which comprises a heat dissipation substrate, a carrier layer and power terminals, the carrier layer is arranged on the heat dissipation substrate, the power terminals are arranged on the carrier layer, and the power terminals comprise a negative power terminal and a positive power terminal which are arranged at intervals. The negative power terminal comprises a first folded plate, a second folded plate, a third folded plate, a fourth folded plate and a fifth folded plate which are vertically connected, the positive power terminal comprises a sixth folded plate, a seventh folded plate, an eighth folded plate and a ninth folded plate which are sequentially connected, the eighth folded plate is arranged on the side, close to the carrier layer, of the third folded plate in parallel, and the ninth folded plate is parallel to the fourth folded plate. Based on a magnetic circuit cancellation principle, the eighth folded plate and the third folded plate are designed into adjacent clearance fit parallel conductors, and the ninth folded plate and the fourth folded plate are designed into adjacent clearance fit parallel conductors, so that stray parameters of the power semiconductor module can be reduced, and the switching frequency of the power semiconductor module can be improved.

Description

Technical Field

[0001] This application belongs to the field of power semiconductor technology, and specifically relates to a power semiconductor module. Background Technology

[0002] Power semiconductors, as the core of power energy conversion, have been widely used in power systems, high-speed rail, aerospace, and industrial fields. Power semiconductors can efficiently convert and control energy, quickly converting energy into the electrical energy required by users. They also have excellent switching speed and frequency, enabling precise and efficient control of electrical energy, and are playing an increasingly important role in the field of energy conversion.

[0003] High density, high efficiency, and high reliability are the development trends of power electronic conversion systems. Adopting power semiconductor module packaging circuit topologies can effectively improve circuit reliability, power density, and reduce parasitic inductance. Silicon carbide (SiC), as a third-generation semiconductor material, possesses superior properties such as three times the bandgap and thermal conductivity of silicon, and ten times the breakdown field strength. Therefore, it exhibits higher voltage blocking capability, lower on-resistance, higher switching speed, higher operating temperature, and lower thermal resistance. Silicon carbide power semiconductor modules offer advantages such as high operating temperature, high power density, and high reliability.

[0004] The stray parameters of existing silicon carbide power semiconductor modules are generally above 20nH. In end-use applications, the switching frequency of silicon carbide power semiconductor modules is mostly between 20kHz and 50kHz. The large stray parameters limit the switching frequency of silicon carbide products in end-use applications. Power electronic converters are rapidly developing towards higher power density and smaller size, and the demand for silicon carbide modules with low stray parameters and high power is becoming increasingly urgent. Utility Model Content

[0005] The purpose of this application is to provide a power semiconductor module that reduces stray parameters and increases the switching frequency of the power semiconductor module.

[0006] To achieve the above objectives, this application provides a power semiconductor module, comprising:

[0007] Heat dissipation substrate;

[0008] A carrier layer is formed on one side of the heat dissipation substrate and is used to support at least the chip.

[0009] A power terminal is disposed on the side of the carrier layer away from the heat dissipation substrate. The power terminal includes a negative power terminal and a positive power terminal that are spaced apart along the length direction of the heat dissipation substrate.

[0010] The negative power terminal includes a first fold plate, a second fold plate, a third fold plate, a fourth fold plate, and a fifth fold plate connected vertically in sequence. The first fold plate is parallel to the carrier layer and disposed on the carrier layer. In the length direction of the heat dissipation substrate, the first fold plate and the third fold plate are located on opposite sides of the second fold plate, and the third fold plate and the fifth fold plate are located on the same side of the fourth fold plate.

[0011] The positive power terminal includes a 6th fold plate, a 7th fold plate, an 8th fold plate, and a 9th fold plate connected in sequence. The 6th fold plate is parallel to the carrier layer and disposed on the carrier layer. The 8th fold plate is parallel to the 6th fold plate and is located on the side of the 3rd fold plate near the carrier layer. The 9th fold plate is parallel to the 4th fold plate and is located on the side of the 9th fold plate near the 3rd fold plate.

[0012] Optionally, the distance between the third fold plate and the eighth fold plate is 0.5mm to 1.5mm, and the distance between the ninth fold plate and the fourth fold plate is 1.3mm to 2.3mm.

[0013] Optionally, the middle part of the seventh fold plate protrudes towards the second fold plate, and a semi-circular arc connects the sixth fold plate and the eighth fold plate.

[0014] Optionally, the distance between the seventh fold plate and the second fold plate is 0.5mm to 1.5mm.

[0015] Optionally, the positive power terminal further includes a 10th fold plate, an 11th fold plate, and a 12th fold plate connected vertically in sequence. The 10th fold plate is vertically connected to the 9th fold plate. In the length direction of the heat dissipation substrate, the 8th fold plate and the 10th fold plate are located on both sides of the 9th fold plate, and the 10th fold plate and the 12th fold plate are located on both sides of the 11th fold plate. The 5th fold plate and the 12th fold plate are used to connect to an external circuit.

[0016] Optionally, the power semiconductor module further includes a housing disposed on the heat dissipation substrate. The housing includes a top plate and multiple side plates, with the top plate and the heat dissipation substrate spaced apart. The side plates are located between the heat dissipation substrate and the top plate. The carrier layer is located within the area enclosed by the multiple side plates. A first insulating partition is disposed on the side of the top plate near the carrier layer. The ninth folding plate and the fourth folding plate are located on both sides of the first insulating partition.

[0017] Optionally, the distance between the fourth fold plate and the first insulating partition is 0.4mm to 0.6mm, and the distance between the ninth fold plate and the first insulating partition is 0.5mm to 1.5mm.

[0018] Optionally, the top plate has a plurality of protrusions on the side away from the heat dissipation substrate, the plurality of protrusions are spaced apart along the length direction of the heat dissipation substrate, a second insulating partition is provided between adjacent protrusions, the fifth fold plate and the twelfth fold plate are respectively located on the side of a protrusion away from the heat dissipation substrate, the fourth fold plate passes through the top plate and the protrusion and is connected to the fifth fold plate, and the eleventh fold plate passes through the top plate and the protrusion and is connected to the twelfth fold plate.

[0019] Optionally, the power terminal further includes an output terminal, which is disposed on the side of the negative power terminal away from the positive power terminal. The output terminal includes a 13th fold plate, a 14th fold plate, a 15th fold plate, a 16th fold plate, and a 17th fold plate connected vertically in sequence. The 13th fold plate is parallel to the carrier layer and disposed on the carrier layer. The 13th fold plate and the 15th fold plate are located on the side of the 14th fold plate away from the negative power terminal. In the length direction of the heat dissipation substrate, the 15th fold plate and the 17th fold plate are located on both sides of the 16th fold plate. The 17th fold plate is located on the side of a boss away from the heat dissipation substrate. The 16th fold plate passes through the top plate and the boss and connects to the 17th fold plate. The 17th fold plate is used to connect to an external circuit.

[0020] Optionally, the carrier layer includes a first conductive layer, an insulating layer, and a second conductive layer stacked sequentially on the heat dissipation substrate. The second conductive layer is patterned and divided into a P-region, an N-region, and an M-region. The N-region is located in the M-region, and the P-region is adjacent to the M-region. The P-region partially extends into the M-region and is adjacent to the N-region. The N-region serves as the source connection carrier for the negative power terminal and the lower-bridge silicon carbide chip. The P-region serves as the drain connection carrier for the positive power terminal and the upper-bridge silicon carbide chip. The M-region serves as the connection carrier for the output terminal, the source of the upper-bridge silicon carbide chip, and the drain of the lower-bridge silicon carbide chip.

[0021] The power semiconductor module disclosed in this application has the following beneficial effects:

[0022] The power semiconductor module in this application includes a heat dissipation substrate, a carrier layer, and power terminals. The carrier layer is disposed on the heat dissipation substrate, and the power terminals are disposed on the carrier layer. The power terminals include negative power terminals and positive power terminals spaced apart along the length of the heat dissipation substrate. The negative power terminals include a first fold plate, a second fold plate, a third fold plate, a fourth fold plate, and a fifth fold plate connected vertically in sequence. The positive power terminals include a sixth fold plate, a seventh fold plate, an eighth fold plate, and a ninth fold plate connected in sequence. The eighth fold plate is parallel to the third fold plate near the carrier layer, and the ninth fold plate is parallel to the fourth fold plate. Based on the principle of magnetic circuit cancellation, this application designs the eighth and third fold plates as adjacent gap-fitted parallel conductors, and the ninth and fourth fold plates as adjacent gap-fitted parallel conductors. This can reduce the stray parameters of the power semiconductor module and increase the switching frequency of the power semiconductor module.

[0023] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0026] Figure 1 This is a partial cross-sectional schematic diagram of the power semiconductor module in an embodiment of this application.

[0027] Figure 2 This is a top view of the power semiconductor module in an embodiment of this application.

[0028] Figure 3 This is a schematic diagram of the main structure of the power semiconductor module in an embodiment of this application.

[0029] Figure 4 This is a schematic diagram of the housing structure of the power semiconductor module in an embodiment of this application.

[0030] Figure 5 This is a schematic diagram illustrating the calculation principle of stray parameters of a current-carrying conductor in an embodiment of this application.

[0031] Figure 6 It is the parasitic inductance-frequency curve of an existing power semiconductor module.

[0032] Figure 7This is the parasitic inductance-frequency curve of the power semiconductor module in the embodiments of this application.

[0033] Figure 8 This is a schematic diagram of the planar structure of the carrier layer in an embodiment of this application.

[0034] Explanation of reference numerals in the attached figures:

[0035] 100. Heat dissipation substrate;

[0036] 200, Carrier layer; 210, Insulating layer; 220, Second conductive layer;

[0037] 310. Negative power terminal; 311. 1st folding plate; 312. 2nd folding plate; 313. 3rd folding plate; 314. 4th folding plate; 315. 5th folding plate;

[0038] 320. Positive power terminal; 321. 6th folding plate; 322. 7th folding plate; 323. 8th folding plate; 324. 9th folding plate; 325. 10th folding plate; 326. 11th folding plate; 327. 12th folding plate;

[0039] 330. Output terminal; 331. 13th folding plate; 332. 14th folding plate; 333. 15th folding plate; 334. 16th folding plate; 335. 17th folding plate;

[0040] 400. Outer shell; 410. Top plate; 420. Side plate; 430. First insulating partition; 440. Boss; 450. Second insulating partition;

[0041] 500. Rivets. Detailed Implementation

[0042] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0043] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0044] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0045] See Figures 1 to 4 As shown, in this embodiment, the power semiconductor module includes a heat dissipation substrate 100, a carrier layer 200, and power terminals. The heat dissipation substrate 100 can be made of a material with high thermal conductivity, such as copper (Cu), aluminum (Al), or aluminum silicon carbide (AlSiC). The carrier layer 200 is formed on one side of the heat dissipation substrate 100, and the carrier layer 200 is used to support at least the silicon carbide chip and the power terminals. The power terminals are disposed on the side of the carrier layer 200 away from the heat dissipation substrate 100, and the power terminals include a negative power terminal 310 and a positive power terminal 320 spaced apart along the length direction of the heat dissipation substrate 100. Both the negative power terminal 310 and the positive power terminal 320 can be formed by bending a thin metal sheet.

[0046] The negative power terminal 310 includes a first folding plate 311, a second folding plate 312, a third folding plate 313, a fourth folding plate 314, and a fifth folding plate 315 connected vertically in sequence, with adjacent folding plates connected by an arc transition. Along the length of the heat dissipation substrate 100, the first folding plate 311 and the third folding plate 313 are located on opposite sides of the second folding plate 312, and the third folding plate 313 and the fifth folding plate 315 are located on the same side of the fourth folding plate 314. The first folding plate 311 is parallel to the carrier layer 200 and is disposed on the carrier layer 200.

[0047] The positive power terminal 320 includes a sixth fold plate 321, a seventh fold plate 322, an eighth fold plate 323, and a ninth fold plate 324 connected in sequence, with adjacent fold plates connected by an arc transition. The sixth fold plate 321 is parallel to and disposed on the carrier layer 200, and the eighth fold plate 323 is parallel to the sixth fold plate 321. The eighth fold plate 323 is located on the side of the third fold plate 313 closest to the carrier layer 200, and the ninth fold plate 324 is parallel to the fourth fold plate 314. The eighth fold plate 323 is located on the side of the ninth fold plate 324 closest to the third fold plate 313.

[0048] In other words, the bending shapes of the 8th fold plate 323 and the 9th fold plate 324 are similar to the bending shapes of the 3rd fold plate 313 and the 4th fold plate 314, and the 8th fold plate 323 is located below the 3rd fold plate 313, while the 9th fold plate 324 is located to the right of the 4th fold plate 314.

[0049] Combination Figure 5 As shown, the principle for calculating the total loop stray parameters (including parasitic inductance) of current flowing through a parallel conductor is as follows:

[0050]

[0051] L = 2L1 - 2M

[0052] Where L1 is the self-inductance of the conductor, M is the mutual inductance of the parallel conductors, L is the total loop inductance of the current flowing through the two parallel conductors, μ0 is the free permeability, and μ0 is a constant; a is the height of the parallel conductors, b is the width of the parallel conductors, c is the length of the parallel conductors, and h is the distance between the two parallel conductors. The dimensions of a, b, and c are determined by the external structure of the power semiconductor module. According to the above formula, reducing the distance h between the parallel conductors can significantly reduce the mutual inductance between them, thereby reducing the total parasitic inductance of the current-carrying loop, and thus reducing the total stray parameters of the current-carrying loop.

[0053] In this embodiment, the power semiconductor module includes a heat dissipation substrate 100, a carrier layer 200, and power terminals. The carrier layer 200 is disposed on the heat dissipation substrate 100, and the power terminals are disposed on the carrier layer 200. The power terminals include a negative power terminal 310 and a positive power terminal 320 spaced apart along the length of the heat dissipation substrate 100. The negative power terminal 310 includes a first folding plate 311, a second folding plate 312, a third folding plate 313, a fourth folding plate 314, and a fifth folding plate 315 connected vertically in sequence. The positive power terminal 320 includes a sixth folding plate 321, a seventh folding plate 322, an eighth folding plate 323, and a ninth folding plate 324 connected in sequence. The eighth folding plate 323 is disposed parallel to the side of the third folding plate 313 near the carrier layer 200, and the ninth folding plate 324 is parallel to the fourth folding plate 314. Based on the principle of magnetic circuit cancellation, the eighth fold plate 323 and the third fold plate 313 are designed as adjacent gap-fitted parallel conductors, and the ninth fold plate 324 and the fourth fold plate 314 are designed as adjacent gap-fitted parallel conductors. This can reduce the stray parameters of the power semiconductor module and increase the switching frequency of the power semiconductor module.

[0054] In some embodiments, the distance between the third fold plate 313 and the eighth fold plate 323 is 0.5mm to 1.5mm, for example, 0.5mm, 1mm, 1.5mm, etc.; the distance between the ninth fold plate 324 and the fourth fold plate 314 is 1.3mm to 2.3mm, for example, 1.3mm, 1.8mm, 2.3mm, etc.

[0055] The gap fit between the third fold plate 313 and the eighth fold plate 323, and the gap fit between the ninth fold plate 324 and the fourth fold plate 314, can significantly reduce the mutual inductance between parallel and adjacent fold plates, thereby reducing the total parasitic inductance of the current-carrying loop, which in turn reduces the total stray parameters of the current-carrying loop.

[0056] In some embodiments, the middle part of the 7th fold plate 322 protrudes towards the 2nd fold plate 312, that is, the 7th fold plate 322 is bent into a semi-circular arc and the semi-circular arc connects the 6th fold plate 321 and the 8th fold plate 323.

[0057] The middle part of the 7th fold plate 322 protrudes towards the 2nd fold plate 312, which can reduce the distance between the 7th fold plate 322 and the 2nd fold plate 312, and help reduce the stray parameters of the power semiconductor module.

[0058] In some embodiments, the distance between the seventh fold plate 322 and the second fold plate 312 is 0.5mm to 1.5mm, for example, 0.5mm, 1mm, 1.5mm, etc.

[0059] The gap fit between the 7th fold plate 322 and the 2nd fold plate 312 can reduce the mutual inductance between the 7th fold plate 322 and the 2nd fold plate 312, thereby reducing the total parasitic inductance of the current-carrying loop, which in turn reduces the total stray parameters of the current-carrying loop.

[0060] In some embodiments, the positive power terminal 320 further includes a 10th fold plate 325, an 11th fold plate 326, and a 12th fold plate 327 connected vertically in sequence, with the 10th fold plate 325 perpendicularly connected to the 9th fold plate 324. Along the length of the heat dissipation substrate 100, the 8th fold plate 323 and the 10th fold plate 325 are located on either side of the 9th fold plate 324, and the 10th fold plate 325 and the 12th fold plate 327 are located on either side of the 11th fold plate 326. The 5th fold plate 315 and the 12th fold plate 327 are used to connect external circuitry.

[0061] Along the length of the heat dissipation substrate 100, the 10th fold plate 325 and the 12th fold plate 327 are located on both sides of the 11th fold plate 326, which can increase the distance between the 11th fold plate 326 and the 4th fold plate 314. This facilitates the connection of the 5th fold plate 315 and the 12th fold plate 327 to external circuits and can also reduce the total parasitic inductance of the current-carrying loop to a certain extent.

[0062] In some embodiments, the power semiconductor module further includes a housing 400 disposed on a heat dissipation substrate 100. The housing 400 includes a top plate 410 and a plurality of side plates 420 connected to each other. The top plate 410 and the heat dissipation substrate 100 are spaced apart, and the side plates 420 are located between the heat dissipation substrate 100 and the top plate 410. A carrier layer 200 is located within the area enclosed by the plurality of side plates 420. The side plates 420 and the heat dissipation substrate 100 can be connected by rivets 500. A first insulating partition 430 is disposed on the side of the top plate 410 near the carrier layer 200. The first insulating partition 430 is perpendicular to the heat dissipation substrate 100 and parallel to the fourth folding plate 314. A ninth folding plate 324 and the fourth folding plate 314 are located on opposite sides of the first insulating partition 430.

[0063] The distance between the fourth fold plate 314 and the first insulating partition 430 is 0.4mm to 0.6mm, for example, 0.4mm, 0.5mm, 0.6mm, etc., and the distance between the ninth fold plate 324 and the first insulating partition 430 is 0.5mm to 1.5mm, for example, 0.5mm, 1mm, 1.5mm, etc.

[0064] The 9th fold plate 324 and the 4th fold plate 314 are disposed on both sides of the 1st insulating partition 430, which can improve the insulation creepage capability of the housing 400.

[0065] In some embodiments, a plurality of protrusions 440 are provided on the side of the top plate 410 away from the heat dissipation substrate 100. The plurality of protrusions 440 are spaced apart along the length direction of the heat dissipation substrate 100, and a second insulating partition 450 is provided between adjacent protrusions 440. The fifth fold plate 315 and the twelfth fold plate 327 are respectively located on the side of a protrusion 440 away from the heat dissipation substrate 100. The fourth fold plate 314 passes through the top plate 410 and the protrusion 440 and is connected to the fifth fold plate 315. The eleventh fold plate 326 passes through the top plate 410 and the protrusion 440 and is connected to the twelfth fold plate 327. The protrusion 440 is provided with a groove for placing a nut. The fifth fold plate 315 and the twelfth fold plate 327 may be provided with circular through holes to facilitate the connection of external circuits to the fifth fold plate 315 and the twelfth fold plate 327.

[0066] A second insulating partition 450 is provided between adjacent bosses 440, which can improve the insulation creepage capability of the housing 400.

[0067] In some embodiments, the power terminal further includes an output terminal 330, which is disposed on the side of the negative power terminal 310 away from the positive power terminal 320. The output terminal 330 includes a 13th fold plate 331, a 14th fold plate 332, a 15th fold plate 333, a 16th fold plate 334, and a 17th fold plate 335 connected vertically in sequence. The 13th fold plate 331 is parallel to and disposed on the carrier layer 200, and a 1mm diameter circular through hole may be provided on the 13th fold plate 331 to improve the reliability of the connection between the 13th fold plate 331 and the carrier layer 200. Correspondingly, a 1mm diameter circular through hole may also be provided on the 1st fold plate 311 and the 6th fold plate 321.

[0068] The 13th fold plate 331 and the 15th fold plate 333 are located on the side of the 14th fold plate 332 away from the negative power terminal 310. Along the length of the heat sink substrate 100, the 15th fold plate 333 and the 17th fold plate 335 are located on either side of the 16th fold plate 334. The 17th fold plate 335 is located on the side of a boss 440 away from the heat sink substrate 100, and the 16th fold plate 334 passes through the top plate 410 and the boss 440 to connect to the 17th fold plate 335. The 17th fold plate 335 is used to connect to an external circuit; correspondingly, a circular through-hole can be formed on the 17th fold plate 335 to facilitate the connection of the external circuit.

[0069] See Figure 6 and Figure 7 As shown, the parasitic inductance between the positive and negative power terminals of a conventional power semiconductor module is 23.4063 nH at 10 MHz and 23.3146 nH at 30 MHz. In this application, the parasitic inductance between the positive and negative power terminals of the power semiconductor module is 10.1373 nH at 10 MHz and 10.0615 nH at 30 MHz. Therefore, this application, based on the principle of magnetic circuit cancellation, improves the power terminal design, which can reduce the stray parameters of the power semiconductor module and increase its switching frequency.

[0070] In some embodiments, the carrier layer 200 includes a first conductive layer, an insulating layer 210, and a second conductive layer 220 sequentially stacked on the heat dissipation substrate 100. The first and second conductive layers 220 are made of copper, and the insulating layer 210 is made of alumina (Al2O3) or silicon nitride (Si3N4). The second conductive layer 220 is patterned and divided into P-regions, N-regions, M-regions, H-G1, H-G2 regions, HS-regions, L-G1 regions, L-G2 regions, LS-regions, and T-regions, as shown below. Figure 8 As shown. Region N is located in region M, and region P is adjacent to region M. Region M is located on the left and region P is located on the right. The middle part of the left side of region P extends into region M and is adjacent to region N. Region N is the source connection carrier of negative power terminal 310 and lower bridge silicon carbide chip. Region P is the drain connection carrier of positive power terminal 320 and upper bridge silicon carbide chip. Region M is the connection carrier of output terminal 330, source of upper bridge silicon carbide chip and drain of lower bridge silicon carbide chip.

[0071] The H-G1 region is located to the right of the P region and serves as the connection carrier for the gate Kelvin lead of the upper-bridge silicon carbide chip. The H-G2 region is located to the right of the H-G1 region and serves as the connection carrier between the gate of the upper-bridge silicon carbide chip and external signal terminals. Surface mount resistors can be placed between the H-G1 and H-G2 regions. The HS region is located to the right of the H-G2 region, with its lower left portion extending into the H-G2 region. The HS region serves as the connection carrier between the source Kelvin lead of the upper-bridge silicon carbide chip and external signal terminals.

[0072] Region L-G1 is located to the left of region M, and serves as the connection carrier for the gate Kelvin lead of the lower-bridge silicon carbide chip. Region L-G2 is located to the left of regions M and L-G1, and above regions M, H-G1, H-G2, and HS. Region L-G2 serves as the connection carrier between the gate of the lower-bridge silicon carbide chip and external signal terminals. Surface mount resistors can be placed between regions L-G1 and L-G2. Region LS is located between region L-G2 and regions M, P, H-G1, H-G2, and HS. Region L-G1 is located between region L-G2 and region LS. Region LS serves as the connection carrier between the source Kelvin lead of the lower-bridge silicon carbide chip and external signal terminals. Region T is located at the upper left corner of the second conductive layer 220, and serves as the connection carrier between the thermistor and external signal terminals.

[0073] For a carrier layer 200 of the same size, the peak current of existing power semiconductor modules is about 200A. This application improves the overall power density of the power semiconductor module by arranging power terminals and silicon carbide chips on the carrier layer 200. The peak current of the power semiconductor module of this application can reach 300A.

[0074] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0075] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0076] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0077] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A power semiconductor module, characterized in that, include: Heat dissipation substrate; A carrier layer is formed on one side of the heat dissipation substrate and is used to support at least the chip. A power terminal is disposed on the side of the carrier layer away from the heat dissipation substrate. The power terminal includes a negative power terminal and a positive power terminal that are spaced apart along the length direction of the heat dissipation substrate. The negative power terminal includes a first fold plate, a second fold plate, a third fold plate, a fourth fold plate, and a fifth fold plate connected vertically in sequence. The first fold plate is parallel to the carrier layer and disposed on the carrier layer. In the length direction of the heat dissipation substrate, the first fold plate and the third fold plate are located on opposite sides of the second fold plate, and the third fold plate and the fifth fold plate are located on the same side of the fourth fold plate. The positive power terminal includes a 6th fold plate, a 7th fold plate, an 8th fold plate, and a 9th fold plate connected in sequence. The 6th fold plate is parallel to the carrier layer and disposed on the carrier layer. The 8th fold plate is parallel to the 6th fold plate and is located on the side of the 3rd fold plate near the carrier layer. The 9th fold plate is parallel to the 4th fold plate and is located on the side of the 9th fold plate near the 3rd fold plate.

2. The power semiconductor module according to claim 1, characterized in that, The distance between the third fold plate and the eighth fold plate is 0.5mm to 1.5mm, and the distance between the ninth fold plate and the fourth fold plate is 1.3mm to 2.3mm.

3. The power semiconductor module according to claim 1, characterized in that, The middle part of the seventh fold plate protrudes towards the second fold plate, and a semi-circular arc connects the sixth fold plate and the eighth fold plate.

4. The power semiconductor module according to claim 3, characterized in that, The distance between the seventh fold plate and the second fold plate is 0.5mm to 1.5mm.

5. The power semiconductor module according to claim 1, characterized in that, The positive power terminal also includes a 10th fold plate, an 11th fold plate, and a 12th fold plate connected vertically in sequence. The 10th fold plate is vertically connected to the 9th fold plate. In the length direction of the heat dissipation substrate, the 8th fold plate and the 10th fold plate are located on both sides of the 9th fold plate, and the 10th fold plate and the 12th fold plate are located on both sides of the 11th fold plate. The 5th fold plate and the 12th fold plate are used to connect to external circuits.

6. The power semiconductor module according to claim 5, characterized in that, The power semiconductor module further includes a housing disposed on the heat dissipation substrate. The housing includes a top plate and multiple side plates. The top plate and the heat dissipation substrate are spaced apart. The side plates are located between the heat dissipation substrate and the top plate. The carrier layer is located within the area enclosed by the multiple side plates. A first insulating partition is disposed on the side of the top plate near the carrier layer. The ninth folding plate and the fourth folding plate are located on both sides of the first insulating partition.

7. The power semiconductor module according to claim 6, characterized in that, The distance between the fourth fold plate and the first insulating partition is 0.4mm to 0.6mm, and the distance between the ninth fold plate and the first insulating partition is 0.5mm to 1.5mm.

8. The power semiconductor module according to claim 6, characterized in that, The top plate has a plurality of protrusions on the side away from the heat dissipation substrate. The plurality of protrusions are spaced apart along the length of the heat dissipation substrate. A second insulating partition is provided between adjacent protrusions. The fifth fold plate and the twelfth fold plate are respectively located on the side of a protrusion away from the heat dissipation substrate. The fourth fold plate passes through the top plate and the protrusion and is connected to the fifth fold plate. The eleventh fold plate passes through the top plate and the protrusion and is connected to the twelfth fold plate.

9. The power semiconductor module according to claim 8, characterized in that, The power terminal further includes an output terminal, which is disposed on the side of the negative power terminal away from the positive power terminal. The output terminal includes a 13th fold plate, a 14th fold plate, a 15th fold plate, a 16th fold plate, and a 17th fold plate connected vertically in sequence. The 13th fold plate is parallel to the carrier layer and disposed on the carrier layer. The 13th fold plate and the 15th fold plate are located on the side of the 14th fold plate away from the negative power terminal. In the length direction of the heat dissipation substrate, the 15th fold plate and the 17th fold plate are located on both sides of the 16th fold plate. The 17th fold plate is located on the side of a boss away from the heat dissipation substrate. The 16th fold plate passes through the top plate and the boss and connects to the 17th fold plate. The 17th fold plate is used to connect to an external circuit.

10. The power semiconductor module according to claim 1, characterized in that, The carrier layer includes a first conductive layer, an insulating layer, and a second conductive layer stacked sequentially on the heat dissipation substrate. The second conductive layer is patterned and divided into P-region, N-region, and M-region. The N-region is located in the M-region. The P-region is adjacent to the M-region. The P-region partially extends into the M-region and is adjacent to the N-region. The N-region is the source connection carrier for the negative power terminal and the lower bridge silicon carbide chip. The P-region is the drain connection carrier for the positive power terminal and the upper bridge silicon carbide chip. The M-region is the connection carrier for the output terminal, the source of the upper bridge silicon carbide chip, and the drain of the lower bridge silicon carbide chip.

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