Blasting data acquisition circuit based on FPGA (Field Programmable Gate Array)
By combining FPGA, ADC and ARM processor, an FPGA-based blasting data acquisition circuit was constructed, which solved the problems of low acquisition efficiency and accuracy in the existing technology, achieved high-precision and real-time data acquisition effect, and reduced system latency and power consumption.
Patent Information
- Application Number
- CN202520625013.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2035-04-03
AI Technical Summary
Existing blasting data acquisition circuits have low efficiency and accuracy, poor real-time performance, and cannot meet the requirements of high dynamic range and rapid changes in blasting signals.
A field-programmable gate array (FPGA) is combined with an analog-to-digital converter (ADC) and an ARM processor. The FPGA is used for data acquisition and preprocessing, while the ARM is used for subsequent processing. The circuit is also combined with analog filters and non-volatile memory devices to construct an FPGA-based blasting data acquisition circuit.
It improves the accuracy and real-time performance of data acquisition, reduces system latency and overall power consumption, and enhances system performance and throughput.
Smart Images
Figure CN223911237U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of blasting data collection, especially to a blasting data collection circuit based on FPGA. BACKGROUND
[0002] The blasting signal has a large dynamic range, changes fast and has a large data volume, and needs to be collected in real time. The existing collection circuit has low collection efficiency and precision and poor real-time performance. UTILITY MODEL CONTENT
[0003] The utility model aims at overcoming the defects of the prior art and providing a blasting data collection circuit based on FPGA.
[0004] The utility model discloses a blasting data collection circuit based on FPGA, which comprises a field programmable gate array (FPGA), an analog-to-digital converter (ADC) and an ARM processor.
[0005] Preferably, the external device comprises a status light, a 100M network port, a USB interface, a liquid crystal screen and a key.
[0006] Preferably, the utility model further comprises a power module, wherein the power module comprises a battery, the input end of the battery is connected with a 12V external power supply, and the output end of the battery is connected with the input end of a switch.
[0007] The utility model has the advantages that:
[0008] 1) The combination of FPGA, ADC and ARM can improve the precision, real-time performance and flexibility of data collection, reduce the overall power consumption and improve the overall performance.
[0009] 2) Using FPGA to process high-speed data and ARM to process subsequent data can reduce system delay and improve throughput.
[0010] 3) Using FPGA to process real-time tasks and ARM to enter low-power mode when idle can reduce overall power consumption. DRAWING DESCRIPTION
[0011] Fig. 1 It is a principle block diagram of the blasting data collection circuit based on FPGA;
[0012] Fig. 2The blasting data acquisition circuit based on FPGA. DETAILED DESCRIPTION
[0013] The technical solutions of the utility model will be described below in connection with the embodiments, obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by the person skilled in the art without creative labor belong to the protection scope of the utility model.
[0014] Reference Figs. 1-2 The utility model provides a technical scheme: a kind of blasting data acquisition circuit based on FPGA, including field programmable gate array FPGA, the field programmable gate array FPGA connects analog-digital converter ADC and ARM processor;The input end of the analog-digital converter ADC is connected with three 4-stage analog filters, and three 4-stage analog filters are used to filter X, Y, Z direction signals respectively;The ARM processor is connected with nonvolatile storage device FLASH, synchronous dynamic random access memory SDRAM and external device.
[0015] In the embodiment, in order to collect the data of low-frequency vibration, improve the collection efficiency and precision, and realize real-time processing of collected data, pre-analog signal conditioning, ADC driving circuit, 24-bit digital-analog conversion circuit, FPGA acquisition circuit, ARM control circuit and storage circuit are used on the circuit.
[0016] After three-way sensor signal enters acquisition instrument, it is preprocessed by signal conditioning circuit, which provides impedance conversion on one hand, and low-pass filtering according to actual application bandwidth on the other hand, controls the overall bandwidth of channel within the effective bandwidth of sensor, to reduce overall noise. 4-stage analog filter is filtered by 32-stage adaptive filter of FPGA.
[0017] ADC driving mainly converts single-ended signal processed by signal conditioning into differential signal connected to analog-digital converter, to meet the sampling level range of digital-analog converter. 24-bit analog-digital converter synchronously collects data.
[0018] FPGA is used for acquisition and signal preprocessing. Because the real-time performance of serial port processing of FPGA is much higher than that of other types of processing, it is used for data acquisition and signal preprocessing. FPGA filters, converts and processes the collected signals, and transmits data to ARM end through FSMC interface. The data obtained by ARM end is processed data. ARM controls state light, network port, interface, liquid crystal screen, key and the like.
[0019] In some embodiments, the external device comprises a status light, a 100M network interface, a USB interface, a liquid crystal screen and a key.
[0020] In some embodiments, a power module is further included, the power module comprising a battery, an input end of the battery being connected to a 12V external power supply, and an output end of the battery being connected to an input end of a switch; the input end of the switch being connected to the 12V external power supply, and an output end of the switch being connected to a power conditioning circuit.
[0021] The above description is only preferred embodiments of the present application, and it should be understood that the present application is not limited to the forms disclosed herein, and should not be considered as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concepts described herein, by the above teachings or related art or knowledge. Any modification and change made by those skilled in the art without departing from the spirit and scope of the present application shall be within the scope of protection of the appended claims of the present application.
Claims
1. An FPGA-based blasting data acquisition circuit, characterized in that: It comprises a field programmable gate array (FPGA) connected with an analog-to-digital converter (ADC) and an ARM processor; the input end of the ADC is connected with three fourth-order analog filters, which are respectively used for filtering X, Y and Z direction signals; the ARM processor is connected with a non-volatile storage device (FLASH), a synchronous dynamic random access memory (SDRAM) and external devices.
2. The FPGA-based blast data acquisition circuit of claim 1, wherein: The external devices comprise a status lamp, a 100M network port, a USB interface, a liquid crystal screen and a key.
3. The FPGA-based blast data acquisition circuit of claim 1, wherein: It also comprises a power module, which comprises a battery, the input end of the battery is connected with a 12V external power supply, and the output end of the battery is connected with the input end of a switch; the input end of the switch is connected with the 12V external power supply, and the output end of the switch is connected with a power conditioning circuit.