Knob encoder circuit capable of converting low section number into high section number

Abstract

The utility model relates to a knob encoder circuit capable of converting a low section number into a high section number. The knob encoder circuit comprises an encoder I SW1, a de-jitter processing circuit, a buffer U3 and an MCU (Microprogrammed Control Unit), wherein the encoder I is a low-section-number encoder; a pulse output signal of the encoder I is input to the buffer U3 through the de-jitter processing circuit, the buffer U3 performs signal processing and then outputs the signal to the MCU, and the MCU performs pulse width processing on the signal so as to simulate a high-section encoder. According to the knob encoder circuit for converting the low section number into the high section number, after the first encoder SW1 is processed by the jitter removing circuit of the knob encoder with the low section number, the signal is input into the U3 buffer for signal processing, and then is output into the MUC for pulse width processing to simulate the knob encoder with the high section number; a pulse signal output by the knob encoder with a low section number is input into the MCU, the pulse broadband is reprocessed, and the output of the knob encoder with a high section number is simulated.

Description

TECHNICAL FIELD

[0001] The utility model relates to encoder technical field especially is a kind of low number of turns high number of knob encoder circuit. BACKGROUND

[0002] Rotary encoder is a kind of actual mechanical parameter value conversion electric signal, and on the basis of processing electrical signal, the speed, position of device is detected.The rotary encoder is used to detect angle, speed, length, displacement and acceleration sensor in automation field.Rotary encoder has been widely applied, and it is usually one of the components required for the stable work of mechanical system and monitoring.

[0003] High number of knob encoder is in order to reach higher accuracy, so production cost and manufacturing complexity are more complex, cause high number of knob encoder Price is very high, and low number of knob encoder price is very cheap, price difference has several tens of times, its is not conducive to the promotion and application in market. UTILITY MODEL CONTENTS

[0004] Therefore, the utility model solves the technical problem to overcome the problem that high number of knob encoder cannot be widely applied due to high processing cost in prior art.

[0005] To solve the above technical problem, the utility model provides a kind of low number of turns high number of knob encoder circuit, including: encoder one SW1, de-bouncing processing circuit, buffer U3 and MCU;Wherein, encoder one, it is low number of encoder;The pulse output signal of the encoder one is input to buffer U3 by de-bouncing processing circuit, and the buffer U3 is output to MCU after signal processing, and the MCU is pulse width processing to simulate high number of encoder to signal.This low number of turns high number of knob encoder circuit of the utility model is simulated high number of knob encoder output by low number of knob encoder and knob encoder adapter board.

[0006] In an embodiment of the utility model, the low number of turns high number of knob encoder circuit further includes signal output end J2, the MCU is connected to signal output end J2, and the signal output end J2 outputs high number of encoder signal.

[0007] In one embodiment of the utility model, the debouncing processing circuit includes resistance R4, resistance R2, resistance R3, resistance R6, capacitor C12 and capacitor C8, one way pulse output signal of encoder one SW1 is connected resistance R4 in series, and the other way pulse output signal of encoder one SW1 is connected resistance R6 in series, one end of resistance R2 and resistance R3 is connected power supply, the other end of resistance R2 is crossed between resistance R4 and buffer U3, and the other end of resistance R2 is connected capacitor C12 in series and then grounded, the other end of resistance R3 is crossed between resistance R6 and buffer U3, and the other end of resistance R3 is connected capacitor C8 in series and then grounded.

[0008] In one embodiment of the utility model, the power supply connected in parallel with the resistance R2 and the resistance R3 is +5V.

[0009] In one embodiment of the utility model, the resistance value of the resistance R4, the resistance R2, the resistance R3 and the resistance R6 is 10KΩ.

[0010] In one embodiment of the utility model, the value of the capacitor C12 and the capacitor C8 is 100NF.

[0011] In one embodiment of the utility model, the VCC end of the buffer U3 is connected with a power supply circuit.

[0012] In one embodiment of the utility model, the power supply circuit includes voltage stabilizer U1, capacitor C5, inductor L1, capacitor C1, capacitor C2, capacitor C3 and capacitor C4, the input end of voltage stabilizer U1 is connected with +5V voltage, the inductor L1 is connected in series between +5V voltage and the input end of voltage stabilizer U1, the first end of capacitor C5 is grounded, and the second end of capacitor C5 intersects the line between inductor L1 and +5V voltage, the first end of capacitor C1 is grounded, and the second end of capacitor C1 intersects the line between inductor L1 and the input end of voltage stabilizer U1, the first end of capacitor C2 is grounded, and the second end of capacitor C2 intersects the line between inductor L1 and the input end of voltage stabilizer U1, the output end of voltage stabilizer U1 is connected with the VCC end of buffer U3, the first end of capacitor C3 is grounded, and the second end of capacitor C3 intersects the output end of voltage stabilizer U1, the first end of capacitor C4 is grounded, and the second end of capacitor C4 intersects the output end of voltage stabilizer U1.

[0013] In one embodiment of the utility model, the value of the capacitor C5, the capacitor C1 and the capacitor C3 is 10UF, and the value of the capacitor C2 and the capacitor C4 is 100NF.

[0014] In one embodiment of the utility model, the value of the inductor L1 is 10UH.

[0015] The above technical scheme of the utility model has the following beneficial effects compared with the prior art:

[0016] The low-bit number to high-bit number knob encoder circuit, when the pulse signals CHA and CHB output by the low-bit number knob encoder of the encoder one SW1 are processed by the R4, C12 and R6, C8 dithering circuit respectively, are input into the U3 buffer for signal processing and then output into the MUC for pulse width processing to simulate the high-bit number knob encoder, and finally are output through the J2, adopts the scheme, only needs to input the pulse signals output by the low-bit number knob encoder into the MCU, carries out the reprocessing of the pulse width, simulates the high-bit knob encoder output. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to make the content of the utility model more easily be clearly understood, the following is according to the specific embodiment of the utility model and combines the drawings, and the utility model is further detailed, wherein

[0018] Figure 1 It is the block diagram of the low-bit number to high-bit number knob encoder circuit in the preferred embodiment of the utility model;

[0019] Figure 2 It is the circuit diagram of the low-bit number to high-bit number knob encoder circuit in the preferred embodiment of the utility model;

[0020] Figure 3 It is the circuit diagram of the power supply circuit in the preferred embodiment of the utility model.

[0021] Description of the Drawings: encoder one SW1, dithering processing circuit 2, buffer U3, MCU 4, signal output end J2, resistance R4, resistance R2, resistance R3, resistance R6, capacitor C12, capacitor C8, power supply circuit 100, voltage stabilizer U1, capacitor C5, inductor L1, capacitor C1, capacitor C2, capacitor C3, capacitor C4. DETAILED DESCRIPTION

[0022] The utility model is further explained in combination with the drawings and specific embodiments, so that the person skilled in the art can better understand the utility model and can be implemented, but the embodiment is not as the limitation of the utility model. EMBODIMENT

[0023] Reference Figure 1 , 2The utility model discloses a low number of high number of knob encoder circuit of turning, comprising: encoder one SW1, debouncing processing circuit 2, buffer U3 and MCU 4, wherein, encoder one 1, it is low number of encoder, the pulse output signal of encoder one 1 is input to buffer U3 through debouncing processing circuit 2, buffer U3 is output to MCU 4 after signal processing, MCU 4 carries out pulse width processing to the signal to simulate high number of encoder.

[0024] Low number of high number of knob encoder circuit still includes signal output end J2, MCU 4 is connected to signal output end J2, and signal output end J2 exports high number of encoder signal.

[0025] Specifically, debouncing processing circuit 2 includes resistance R4, resistance R2, resistance R3, resistance R6, electric capacity C12 and electric capacity C8, one pulse output signal of encoder one SW1 is connected in series with resistance R4, and another pulse output signal of encoder one SW1 is connected in series with resistance R6, one end of resistance R2 and resistance R3 is connected with power supply, the other end of resistance R2 is crossed between resistance R4 and buffer U3, and the other end of resistance R2 is connected in series with electric capacity C12 and then grounded, the other end of resistance R3 is crossed between resistance R6 and buffer U3, and the other end of resistance R3 is connected in series with electric capacity C8 and then grounded.

[0026] The specific value of resistance R4, resistance R2, resistance R3, resistance R6, electric capacity C12 and electric capacity C8 in debouncing processing circuit 2 is that the resistance of resistance R4, resistance R2, resistance R3 and resistance R6 is all 10KΩ, the value of electric capacity C12 and electric capacity C8 is 100NF, the VCC end of buffer U3 is connected with power supply circuit 100, and the power supply connected with resistance R2 and resistance R3 is +5V.

[0027] In the above circuit, the model number of encoder one SW1 is PEC11R-4215F-N0024, the model number of buffer U3 is SN74LVC2G17DCKR, and the model number of MCU 4 is ATXMEGA32A4U-MHR. Embodiment

[0028] Based on the basis of embodiment one, refer to Figure 3As shown, the power supply circuit 100 includes a voltage regulator U1, a capacitor C5, an inductor L1, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4, an input terminal of the voltage regulator U1 is connected with a +5V voltage, the inductor L1 is connected in series between the +5V voltage and the input terminal of the voltage regulator U1, a first terminal of the capacitor C5 is grounded, and a second terminal of the capacitor C5 intersects a line between the inductor L1 and the +5V voltage, a first terminal of the capacitor C1 is grounded, and a second terminal of the capacitor C1 intersects a line between the inductor L1 and the input terminal of the voltage regulator U1, a first terminal of the capacitor C2 is grounded, and a second terminal of the capacitor C2 intersects a line between the inductor L1 and the input terminal of the voltage regulator U1, an output terminal of the voltage regulator U1 is connected with a VCC terminal of a buffer U3, a first terminal of the capacitor C3 is grounded, and a second terminal of the capacitor C3 intersects the output terminal of the voltage regulator U1, a first terminal of the capacitor C4 is grounded, and a second terminal of the capacitor C4 intersects the output terminal of the voltage regulator U1.

[0029] Specifically, the capacitor C5, the capacitor C1 and the capacitor C3 have a value of 10UF, and the capacitor C2 and the capacitor C4 have a value of 100NF. The inductor L1 has a value of 10UH.

[0030] In the above circuit, the voltage regulator U1 is a low-dropout voltage regulator, and specifically, the voltage regulator U1 has a model of LT1764AEQ-3.3.

[0031] Obviously, the above embodiments are only examples for clearly illustrating, and are not intended to limit the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A low-to-high prong knob encoder circuit, comprising: The application relates to a low-number-to-high-number knob encoder circuit. The encoder one is a low-number encoder; pulse output signals of the encoder one are input to a buffer U3 through a de-bouncing processing circuit; the buffer U3 performs signal processing and then outputs to an MCU; the MCU performs pulse width processing on the signals to simulate a high-number encoder. The low-number-to-high-number knob encoder circuit further comprises a signal output terminal J2, the MCU is connected to the signal output terminal J2, and the signal output terminal J2 outputs high-number encoder signals.

2. The low-to-high-bus factor knob encoder circuit of claim 1, wherein: The de-bouncing processing circuit comprises resistors R4, R2, R3, R6, a capacitor C12 and a capacitor C8; one pulse output signal of the encoder one SW1 is connected in series with the resistor R4, and another pulse output signal of the encoder one SW1 is connected in series with the resistor R6; one end of the resistor R2 and the resistor R3 are connected to a power supply; the other end of the resistor R2 intersects between the resistor R4 and the buffer U3, and the other end of the resistor R2 is connected in series with the capacitor C12 and then grounded; the other end of the resistor R3 intersects between the resistor R6 and the buffer U3, and the other end of the resistor R3 is connected in series with the capacitor C8 and then grounded.

3. The low-to-high-bus factor knob encoder circuit of claim 1, wherein: The power supply connected in parallel with the resistor R2 and the resistor R3 is +5V.

4. The low-to-high-bus factor knob encoder circuit of claim 3, wherein: The resistors R4, R2, R3 and R6 all have a resistance of 10K.

5. The low-to-high-bus factor knob encoder circuit of claim 3, wherein: The capacitors C12 and C8 have a value of 100NF.

6. The low-to-high-bus factor knob encoder circuit of claim 5, wherein: The VCC end of the buffer U3 is connected with a power supply circuit.

7. The low-to-high-bus factor knob encoder circuit of claim 1, wherein: The power supply circuit comprises a voltage stabilizer U1, capacitors C5, C1, C2, C3 and C4, and an inductor L1; the input end of the voltage stabilizer U1 is connected to a +5V voltage; the inductor L1 is connected in series between the +5V voltage and the input end of the voltage stabilizer U1; the first end of the capacitor C5 is grounded, and the second end of the capacitor C5 intersects a line between the inductor L1 and the +5V voltage; the first end of the capacitor C1 is grounded, and the second end of the capacitor C1 intersects a line between the inductor L1 and the input end of the voltage stabilizer U1; the first end of the capacitor C2 is grounded, and the second end of the capacitor C2 intersects a line between the inductor L1 and the input end of the voltage stabilizer U1; the output end of the voltage stabilizer U1 is connected to the VCC end of the buffer U3; the first end of the capacitor C3 is grounded, and the second end of the capacitor C3 intersects the output end of the voltage stabilizer U1; the first end of the capacitor C4 is grounded, and the second end of the capacitor C4 intersects the output end of the voltage stabilizer U1.

8. The low-to-high-bus factor knob encoder circuit of claim 7, wherein: The capacitors C5, C1 and C3 have a value of 10UF, and the capacitors C2 and C4 have a value of 100NF.

9. The low-to-high-bus factor knob encoder circuit of claim 8, wherein: The inductor L1 has a value of 10UH.

10. The low-to-high bit count knob encoder circuit of claim 8 or 9, wherein: ​

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