Multi-mode multi-frequency power amplifier

Abstract

The utility model relates to the technical field of wireless communication, and provides a multimode multi-frequency power amplifier, which comprises a substrate, a first chip, a second chip and a power supply, and is characterized in that the first chip and the second chip are oppositely arranged at an interval; a first power amplification unit, a second power amplification unit and a third power amplification unit are integrated on the first chip; a switch unit and a control unit are integrated on the second chip, and the control unit is used for providing bias signals for the first power amplification unit, the second power amplification unit and the third power amplification unit respectively; the first power amplification unit and the third power amplification unit are arranged on two short axis sides of the first chip, and the second power amplification unit is arranged on one long axis side, closer to the second chip, of the first chip. According to the multi-mode multi-frequency power amplifier, the product circuit layout of the multi-mode multi-frequency power amplifier can be optimized, the product circuit stability is improved, and the product performance is improved.

Description

Technical Field

[0001] This utility model relates to the field of wireless communication technology, and in particular to a multimode multi-frequency power amplifier. Background Technology

[0002] In 5G communication systems, multimode multiband (MMMB) power amplifiers (PAs) need to implement carrier aggregation (CA) in the MB (mid-band, frequency range from 1710MHz to 2025MHz) and HB (high-band, frequency range from 2300MHz to 2690MHz). If harmonics of some frequencies in the LB (low-band, frequency range from 663MHz to 915MHz) (where the second or third harmonic of the main frequency coincides with the CA frequency) leak to the MB and HB ports, they will interfere with the CA band signal and degrade the CA's receiving sensitivity.

[0003] Current CAT1 architecture 3mm x 3mm small-size MMMB PA products require the layout of the control unit, power amplifier unit, output matching network, and switching unit within a very small area. The control unit is responsible for providing bias voltage or current to the amplifier unit and controlling the switching unit; the power amplifier unit typically integrates power amplifiers for the LB, MB, and HB frequency bands; such as... Figure 1 As shown, LB is positioned below the chip, and MB and HB are positioned to the right and side by side. The output matching network connects to the output of the power amplifier unit, providing impedance matching for the power amplifier unit; the switching unit selects different switches as output ports according to the configuration of the control unit; and the layout of all units becomes difficult to complete within such a small area.

[0004] However, existing power amplifier units are mostly GaAa HBT (Gallium Arsenide Heterojunction Bipolar Transistor) chips U1, integrating power amplifiers for the LB, MB, and HB frequency bands; the control unit is a CMOS (Complementary Metal-Oxide-Semiconductor) chip U2; and the switching unit is mostly an SOI (Solar-Insulated) chip U3. In the output matching unit, the inductor is implemented by wire winding on the substrate, and the output matching capacitor is implemented on U1, or by using SMD (Surface Mount Device) capacitors, mostly 01005 inch in size (where 01 represents the length of the component and 005 represents the width of the component). Up to three chips are distributed in the product, with strict spacing requirements, occupying a large area; since the power amplifiers for the three frequency bands integrated in the product all need power, the power supply lines usually require three or more filter capacitors to maintain circuit stability, and these capacitors require a lot of space; some designs use 01005 inch SMD capacitors for matching capacitors, further compressing the space. Therefore, in conventional designs, the units are very crowded, and performance or stability must be sacrificed to achieve the layout, resulting in poor space for the circuit layout of each unit in the product. Utility Model Content

[0005] To address the shortcomings of the existing technology, this utility model proposes a multi-mode multi-frequency power amplifier to solve the problem of poor space layout for each unit circuit in existing multi-mode multi-frequency power amplifiers.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] This utility model provides a multimode multi-frequency power amplifier, which includes a substrate, a rectangular first chip and a second chip respectively disposed on the substrate, and a power supply. The first chip and the second chip are spaced apart and disposed opposite to each other, and the power supply supplies power to the first chip and the second chip respectively. The first chip integrates a first power amplification unit, a second power amplification unit, and a third power amplification unit. The second chip integrates a switching unit and a control unit. The first power amplification unit amplifies low-frequency signals, the second power amplification unit amplifies mid-frequency signals, and the third power amplification unit amplifies high-frequency signals. The control terminal of the switching unit is connected to the first power amplification unit, the second power amplification unit, and the third power amplification unit respectively, and the output terminal of the switching unit is connected to a signal output port. The switching unit is used to switch the outputs of the first power amplification unit, the second power amplification unit, and the third power amplification unit respectively. The control unit is used to provide bias signals to the first power amplification unit, the second power amplification unit, and the third power amplification unit respectively. The first power amplification unit and the third power amplification unit are disposed on two short axis sides of the first chip, and the second power amplification unit is disposed on one of the long axis sides of the first chip closer to the second chip.

[0008] Preferably, the first power amplification unit includes a first-stage low-frequency power amplifier, a second-stage low-frequency power amplifier, and a first output matching circuit connected in sequence; the first-stage low-frequency power amplifier and the second-stage low-frequency power amplifier are used to amplify the low-frequency signal, and the output terminal of the first output matching circuit is connected to the control terminal of the switching unit.

[0009] The second power amplifier unit includes a first-stage intermediate frequency power amplifier, a second-stage intermediate frequency power amplifier, and a second output matching circuit connected in sequence; the first-stage intermediate frequency power amplifier and the second-stage intermediate frequency power amplifier are used to amplify the intermediate frequency signal, and the second output matching circuit is used to match the signal output by the second-stage intermediate frequency power amplifier and output it to the control terminal of the switching unit;

[0010] The third power amplifier unit includes a first-stage high-frequency power amplifier, a second-stage high-frequency power amplifier, and a third output matching circuit connected in sequence. The first-stage high-frequency power amplifier and the second-stage high-frequency power amplifier are used to amplify the high-frequency signal, and the third output matching circuit is used to match the signal output by the second-stage high-frequency power amplifier and output it to the control terminal of the switching unit.

[0011] Preferably, the first output matching circuit includes a first inductor, a first capacitor, a second inductor, and a second capacitor;

[0012] The first terminal of the first capacitor serves as the input terminal of the first output matching circuit. The second terminal of the first capacitor is connected to the first terminal of the first inductor and the first terminal of the second inductor, respectively. The second terminal of the first inductor is grounded. The second terminal of the second inductor is connected to the first terminal of the second capacitor and serves as the output terminal of the first output matching circuit, which is connected to the control terminal of the switching unit. The second terminal of the second capacitor is grounded.

[0013] Preferably, the first power amplification unit further includes a first filter circuit and a second filter circuit; the input terminals of the first filter circuit and the second filter circuit are respectively connected to the power supply, and the output terminals of the first filter circuit and the second filter circuit are respectively connected to the first-stage low-frequency power amplifier and the second-stage low-frequency power amplifier; the first filter circuit and the second filter circuit are respectively used to provide filtered power supply voltages for the first-stage low-frequency power amplifier and the second-stage low-frequency power amplifier.

[0014] Preferably, the second filter circuit includes a third capacitor, a fourth capacitor, a third inductor, and a fourth inductor;

[0015] The first terminal of the fourth capacitor is connected to the first terminal of the fourth inductor and serves as the input terminal of the second filter circuit. The second terminal of the fourth inductor is connected to the first terminal of the third inductor and the first terminal of the third capacitor. The second terminal of the third capacitor is grounded, and the second terminal of the third inductor serves as the output terminal of the second filter circuit.

[0016] Preferably, the first filter circuit includes a fifth capacitor, a fifth inductor, and a sixth inductor;

[0017] The first end of the fifth inductor serves as the input terminal of the first filter circuit and is connected to the first end of the fourth inductor; the second end of the fifth inductor is connected to the first end of the fifth capacitor and the first end of the sixth inductor, respectively, and the second end of the sixth inductor serves as the output terminal of the first filter circuit.

[0018] Preferably, the first capacitor is disposed on the first chip, and the second capacitor is disposed on the second chip.

[0019] Preferably, the control unit and the first chip are electrically connected via a connecting wire.

[0020] Preferably, the multi-mode multi-frequency power amplifier further includes a harmonic suppression circuit, which is connected between the output terminal of the second-stage low-frequency power amplifier and the input terminal of the first output matching circuit. The harmonic suppression circuit is used to suppress harmonics output by the first-stage low-frequency power amplifier and the second-stage low-frequency power amplifier. The harmonic suppression circuit includes a sixth capacitor and a seventh inductor. The first terminal of the sixth capacitor is connected to the output terminal of the second-stage low-frequency power amplifier and the input terminal of the first output matching circuit, respectively. The second terminal of the sixth capacitor is connected to the first terminal of the seventh inductor, and the second terminal of the seventh inductor is grounded.

[0021] Preferably, the first power amplification unit, the second power amplification unit, and the third power amplification unit are integrated on the first chip using GaAa HBT technology; the control unit and the switching unit are integrated on the second chip using SOI technology.

[0022] Compared with related technologies, in the embodiments of this utility model, the first chip and the second chip are arranged opposite to each other and spaced apart; the first chip integrates a first power amplifier unit, a second power amplifier unit, and a third power amplifier unit; the second chip integrates a switching unit and a control unit. The first power amplifier unit amplifies low-frequency signals, the second power amplifier unit amplifies mid-frequency signals, and the third power amplifier unit amplifies high-frequency signals. The control terminal of the switching unit is connected to the first power amplifier unit, the second power amplifier unit, and the third power amplifier unit respectively, and the output terminal of the switching unit is connected to a signal output port. The switching unit is used to switch the outputs of the first power amplifier unit, the second power amplifier unit, and the third power amplifier unit. The control unit is used to provide bias signals to the first power amplifier unit, the second power amplifier unit, and the third power amplifier unit respectively. The first power amplifier unit and the third power amplifier unit are arranged on the relatively short axis side of the first chip, and the second power amplifier unit is arranged on the long axis side of the first chip and close to the side of the second chip. Through a highly integrated design, the layout space is optimized, and the performance and circuit stability are improved. At the same time, by oriented the three power amplifier units in different directions, the isolation of the three frequency bands is ensured, thereby improving product performance. Attached Figure Description

[0023] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description in conjunction with the following drawings. In the drawings:

[0024] Figure 1 This is a schematic diagram of the structure of an existing power amplifier chip;

[0025] Figure 2A schematic diagram of the layout of the substrate and chip of the multimode multi-frequency power amplifier provided in this embodiment of the utility model;

[0026] Figure 3 A circuit block diagram of a multimode multi-frequency power amplifier provided for an embodiment of this utility model;

[0027] Figure 4 The circuit diagram of the first power amplification unit of the multimode multifrequency power amplifier provided in the embodiment of this utility model.

[0028] Among them, 100 is a multi-mode multi-frequency power amplifier; 1 is a substrate; 2 is a first power amplifier unit; 21 is a first-stage low-frequency power amplifier; 22 is a second-stage low-frequency power amplifier; 23 is a harmonic suppression circuit; 24 is a first output matching circuit; 25 is a first filter circuit; 26 is a second filter circuit; 3 is a second power amplifier unit; 31 is a first-stage intermediate-frequency power amplifier; 32 is a second-stage intermediate-frequency power amplifier; 33 is a second output matching circuit; 4 is a third power amplifier unit; 41 is a first-stage high-frequency power amplifier; 42 is a second-stage high-frequency power amplifier; 43 is a third output matching circuit; 5 is a switching unit; 6 is a control unit; 7 is a first chip; 8 is a second chip; 9 is a connecting line; and 10 is a signal output port. Detailed Implementation

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0030] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0032] Please see Figures 2-4 As shown, this embodiment of the present invention provides a multi-mode multi-frequency power amplifier 100. The multi-mode multi-frequency power amplifier 100 includes a substrate 1, a first chip 7 and a second chip 8, each in a rectangular shape, respectively disposed on the substrate 1, and a power supply VCC1. The first chip 7 and the second chip 8 are spaced apart and disposed opposite to each other. The power supply VCC1 supplies power to the first chip 7 and the second chip 8 respectively. The first chip 7 integrates a first power amplification unit 2, a second power amplification unit 3, and a third power amplification unit 4; the second chip 8 integrates a switching unit 5 and a control unit 6. The first power amplification unit 2 amplifies low-frequency signals, the second power amplification unit 3 amplifies mid-frequency signals, and the third power amplification unit 4 amplifies high-frequency signals. The control terminal of the switching unit 5 is connected to the first power amplification unit 2, the second power amplification unit 3, and the third power amplification unit 4 respectively, and the output terminal of the switching unit 5 is connected to a signal output port 10. The switching unit 5 is used to switch the outputs of the first power amplification unit 2, the second power amplification unit 3, and the third power amplification unit 4. The control unit 6 provides bias signals to the first power amplifier unit 2, the second power amplifier unit 3, and the third power amplifier unit 4, respectively. The first power amplifier unit 2 and the third power amplifier unit 4 are located on two short axis sides of the first chip 7, and the second power amplifier unit 3 is located on one long axis side of the first chip 7 closer to the second chip 8. Specifically, the first power amplifier unit 2 is located at the lower part of the first chip 7, the third power amplifier unit 4 is located at the upper part of the first chip 7, and the second power amplifier unit 3 is located at the right side of the first chip 7. By integrating the control unit 6 and the switching unit 5 into a single second chip 8 using SOI technology, the control unit 6 provides bias signals (voltage or current) to the first power amplifier unit 2, the second power amplifier unit 3, and the third power amplifier unit 4. This highly integrated design optimizes layout space, improves performance and circuit stability, and ensures isolation between the three frequency bands by orienting the three power amplifier units in different directions, thereby enhancing product performance.

[0033] In this embodiment, the first power amplification unit 2 includes a first-stage low-frequency power amplifier 21, a second-stage low-frequency power amplifier 22, and a first output matching circuit 24, which are connected in sequence. The first-stage low-frequency power amplifier 21 and the second-stage low-frequency power amplifier 22 are used to amplify the low-frequency signal. The output terminal of the first output matching circuit 24 is connected to the control terminal of the switching unit 5. The first output matching circuit 24 performs impedance matching on the amplified signal output by the second-stage low-frequency power amplifier 22, and outputs an optimized radio frequency signal to the switching unit 5.

[0034] The second power amplification unit 3 includes a first-stage intermediate frequency (IF) power amplifier 31, a second-stage IF power amplifier 32, and a second output matching circuit 33, which are connected in sequence. The first-stage IF power amplifier 31 and the second-stage IF power amplifier 32 are used to amplify the IF signal. The second output matching circuit 33 is used to match the signal output by the second-stage IF power amplifier 32 and then output it to the control terminal of the switching unit 5. The second output matching circuit 33 performs impedance matching on the amplified signal output by the second-stage IF power amplifier 32, and outputs an optimized radio frequency (RF) signal to the switching unit 5.

[0035] The third power amplification unit 4 includes a first-stage high-frequency power amplifier 41, a second-stage high-frequency power amplifier 42, and a third output matching circuit 43, which are connected in sequence. The first-stage high-frequency power amplifier 41 and the second-stage high-frequency power amplifier 42 are used to amplify the high-frequency signal. The third output matching circuit 43 is used to match the signal output by the second-stage high-frequency power amplifier 42 and then output it to the control terminal of the switching unit 5. By performing impedance matching on the amplified signal output by the second-stage high-frequency power amplifier 42 through the third output matching circuit 43, an optimized radio frequency signal is output to the switching unit 5.

[0036] Optionally, the first output matching circuit 24, the second output matching circuit 33, and the third output matching circuit 43 have the same circuit structure and produce the same technical effect.

[0037] In this embodiment, the first output matching circuit 24 includes a first inductor L1, a first capacitor C1, a second inductor L2, and a second capacitor C2. The first terminal of the first capacitor C1 serves as the input terminal of the first output matching circuit 24. The second terminal of the first capacitor C1 is connected to both the first terminal of the first inductor L1 and the first terminal of the second inductor L2, and the second terminal of the first inductor L1 is grounded. The second terminal of the second inductor L2 is connected to the first terminal of the second capacitor C2 and serves as the output terminal of the first output matching circuit 24, connected to the control terminal of the switching unit 5. The second terminal of the second capacitor C2 is grounded. A CLLC-type matching circuit is implemented by interconnecting the first inductor L1, the first capacitor C1, the second inductor L2, and the second capacitor C2.

[0038] In this embodiment, the first power amplification unit 2 further includes a first filter circuit 25 and a second filter circuit 26; the input terminal of the first filter circuit 25 and the input terminal of the second filter circuit 26 are respectively connected to the power supply VCC1, and the output terminal of the first filter circuit 25 and the output terminal of the second filter circuit 26 are respectively connected to the first stage low-frequency power amplifier 21 and the second stage low-frequency power amplifier 22; the first filter circuit 25 and the second filter circuit 26 are respectively used to provide filtered power supply voltages for the first stage low-frequency power amplifier 21 and the second stage low-frequency power amplifier 22.

[0039] In this embodiment, the second filter circuit 26 includes a third capacitor C3, a fourth capacitor C4, a third inductor L3, and a fourth inductor L4. The first terminal of the fourth capacitor C4 is connected to the first terminal of the fourth inductor L4 and serves as the input terminal of the second filter circuit 26. The second terminal of the fourth inductor L4 is connected to both the first terminal of the third inductor L3 and the first terminal of the third capacitor C3. The second terminal of the third capacitor C3 is grounded, and the second terminal of the third inductor L3 serves as the output terminal of the second filter circuit 26. By using the third capacitor C3 and the fourth capacitor C4 as power supply filter capacitors for the second stage of power supply, harmonic components in the circuit can be filtered out, electromagnetic interference can be suppressed, and stable circuit operation can be ensured.

[0040] In this embodiment, the first filter circuit 25 includes a fifth capacitor C5, a fifth inductor L5, and a sixth inductor L6. The first end of the fifth inductor L5 serves as the input terminal of the first filter circuit 25 and is connected to the first end of the fourth inductor L4; the second end of the fifth inductor L5 is connected to the first end of the fifth capacitor C5 and the first end of the sixth inductor L6, respectively, and the second end of the sixth inductor L6 serves as the output terminal of the first filter circuit 25.

[0041] In this embodiment, the first capacitor C1 is disposed on the first chip 7, and the second capacitor C2 is disposed on the second chip 8. By implementing the first capacitor C1 on the first chip 7 and the second capacitor C2 on the second chip 8, it is unnecessary to use SMD surface-mount capacitors that occupy a large area, thus saving installation space.

[0042] In this embodiment, the control unit 6 and the first chip 7 are electrically connected via a connecting line 9 (Vreg line). Connecting the control unit 6 of the second chip 8 and the first chip 7 via the connecting line 9 eliminates the need for traces through the substrate 1; instead, the connecting line 9 provides an overhead connection, saving installation space. This optimizes the layout and improves performance and circuit stability. Optionally, the connecting line 9 is made of gold wire, which has excellent conductivity.

[0043] In this embodiment, the second output matching circuit 33 and the third output matching circuit 43 can make full use of the space between the first chip 7 and the second chip 8, especially the area under the connecting line 9, thereby improving space utilization.

[0044] In this embodiment, the multi-mode multi-frequency power amplifier 100 further includes a harmonic suppression circuit 23. The harmonic suppression circuit 23 is connected between the output terminal of the second-stage low-frequency power amplifier 22 and the input terminal of the first output matching circuit 24. The harmonic suppression circuit 23 is used to suppress harmonics output by the first-stage low-frequency power amplifier 21 and the second-stage low-frequency power amplifier 22. The harmonic suppression circuit 23 includes a sixth capacitor C6 and a seventh inductor L7. The first terminal of the sixth capacitor C6 is connected to both the output terminal of the second-stage low-frequency power amplifier 22 and the input terminal of the first output matching circuit 24. The second terminal of the sixth capacitor C6 is connected to the first terminal of the seventh inductor L7, and the second terminal of the seventh inductor L7 is grounded. By using the sixth capacitor C6 and the seventh inductor L7 as power supply filter capacitors for the second-stage power supply, harmonic components in the circuit can be filtered out, electromagnetic interference can be suppressed, and stable circuit operation can be ensured. The seventh inductor L7 has the characteristic of impeding current changes, which can suppress the passage of high-frequency harmonic currents; the sixth capacitor C6 can impede voltage changes, presenting low impedance to high-frequency harmonics, bypassing them to ground.

[0045] In this embodiment, the first power amplification unit 2, the second power amplification unit 3, and the third power amplification unit 4 are integrated on the first chip 7 using GaAa HBT (gallium arsenide heterojunction bipolar transistor) technology; the control unit 6 and the switching unit 5 are integrated on the second chip 8 using SOI technology. GaAs HBT is a gallium arsenide heterojunction bipolar transistor. It is a high-performance device developed based on the traditional bipolar transistor (BJT), which significantly improves device performance by forming a heterojunction between the emitter and base using different semiconductor materials. SOI (Silicon-On-Insulator) technology, through which an active silicon layer is isolated by an insulator, offers advantages such as low power consumption, high frequency, and radiation resistance.

[0046] In this embodiment, due to the optimized circuit layout space, four filter capacitors, namely the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6, can be placed on the substrate 1. This measure greatly improves the circuit stability of the product and enhances its performance.

[0047] It should be noted that the various embodiments described above with reference to the accompanying drawings are only illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be covered within the scope of the present invention. Furthermore, unless the context otherwise requires, singular terms include plural forms, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A multi-mode multi-frequency power amplifier, characterized in that, The multimode multi-frequency power amplifier includes a substrate, a rectangular first chip and a second chip respectively disposed on the substrate, and a power supply. The first chip and the second chip are spaced apart and disposed opposite to each other, and the power supply supplies power to the first chip and the second chip respectively. The first chip integrates a first power amplification unit, a second power amplification unit, and a third power amplification unit. The second chip integrates a switching unit and a control unit. The first power amplification unit amplifies low-frequency signals, the second power amplification unit amplifies mid-frequency signals, and the third power amplification unit amplifies high-frequency signals. The control terminal of the switching unit is connected to the first power amplification unit, the second power amplification unit, and the third power amplification unit respectively, and the output terminal of the switching unit is connected to a signal output port. The switching unit is used to switch the outputs of the first power amplification unit, the second power amplification unit, and the third power amplification unit respectively. The control unit is used to provide bias signals to the first power amplification unit, the second power amplification unit, and the third power amplification unit respectively. The first power amplification unit and the third power amplification unit are disposed on two short axis sides of the first chip, and the second power amplification unit is disposed on one of the long axis sides of the first chip closer to the second chip.

2. The multimode multi-frequency power amplifier according to claim 1, characterized in that, The first power amplification unit includes a first-stage low-frequency power amplifier, a second-stage low-frequency power amplifier, and a first output matching circuit that are connected in sequence. The first-stage low-frequency power amplifier and the second-stage low-frequency power amplifier are used to amplify the low-frequency signal, and the output terminal of the first output matching circuit is connected to the control terminal of the switching unit. The second power amplifier unit includes a first-stage intermediate frequency power amplifier, a second-stage intermediate frequency power amplifier, and a second output matching circuit connected in sequence; the first-stage intermediate frequency power amplifier and the second-stage intermediate frequency power amplifier are used to amplify the intermediate frequency signal, and the second output matching circuit is used to match the signal output by the second-stage intermediate frequency power amplifier and output it to the control terminal of the switching unit; The third power amplifier unit includes a first-stage high-frequency power amplifier, a second-stage high-frequency power amplifier, and a third output matching circuit connected in sequence. The first-stage high-frequency power amplifier and the second-stage high-frequency power amplifier are used to amplify the high-frequency signal, and the third output matching circuit is used to match the signal output by the second-stage high-frequency power amplifier and output it to the control terminal of the switching unit.

3. The multimode multi-frequency power amplifier according to claim 2, characterized in that, The first output matching circuit includes a first inductor, a first capacitor, a second inductor, and a second capacitor; The first terminal of the first capacitor serves as the input terminal of the first output matching circuit. The second terminal of the first capacitor is connected to the first terminal of the first inductor and the first terminal of the second inductor, respectively. The second terminal of the first inductor is grounded. The second terminal of the second inductor is connected to the first terminal of the second capacitor and serves as the output terminal of the first output matching circuit, which is connected to the control terminal of the switching unit. The second terminal of the second capacitor is grounded.

4. The multi-mode multi-frequency power amplifier according to claim 2, characterized in that, The first power amplifier unit further includes a first filter circuit and a second filter circuit; the input terminals of the first filter circuit and the second filter circuit are respectively connected to the power supply, and the output terminals of the first filter circuit and the second filter circuit are respectively connected to the first-stage low-frequency power amplifier and the second-stage low-frequency power amplifier; the first filter circuit and the second filter circuit are respectively used to provide filtered power supply voltages for the first-stage low-frequency power amplifier and the second-stage low-frequency power amplifier.

5. The multimode multi-frequency power amplifier according to claim 4, characterized in that, The second filter circuit includes a third capacitor, a fourth capacitor, a third inductor, and a fourth inductor; The first terminal of the fourth capacitor is connected to the first terminal of the fourth inductor and serves as the input terminal of the second filter circuit. The second terminal of the fourth inductor is connected to the first terminal of the third inductor and the first terminal of the third capacitor. The second terminal of the third capacitor is grounded, and the second terminal of the third inductor serves as the output terminal of the second filter circuit.

6. The multimode multi-frequency power amplifier according to claim 5, characterized in that, The first filter circuit includes a fifth capacitor, a fifth inductor, and a sixth inductor; The first end of the fifth inductor serves as the input terminal of the first filter circuit and is connected to the first end of the fourth inductor; the second end of the fifth inductor is connected to the first end of the fifth capacitor and the first end of the sixth inductor, respectively, and the second end of the sixth inductor serves as the output terminal of the first filter circuit.

7. The multimode multi-frequency power amplifier according to claim 3, characterized in that, The first capacitor is disposed on the first chip, and the second capacitor is disposed on the second chip.

8. The multimode multi-frequency power amplifier according to claim 1, characterized in that, The control unit is electrically connected to the first chip via a connecting wire.

9. The multimode multi-frequency power amplifier according to claim 2, characterized in that, The multi-mode multi-frequency power amplifier further includes a harmonic suppression circuit, which is connected between the output terminal of the second-stage low-frequency power amplifier and the input terminal of the first output matching circuit. The harmonic suppression circuit is used to suppress harmonics output by the first-stage low-frequency power amplifier and the second-stage low-frequency power amplifier. The harmonic suppression circuit includes a sixth capacitor and a seventh inductor. The first terminal of the sixth capacitor is connected to the output terminal of the second-stage low-frequency power amplifier and the input terminal of the first output matching circuit, respectively. The second terminal of the sixth capacitor is connected to the first terminal of the seventh inductor, and the second terminal of the seventh inductor is grounded.

10. The multimode multi-frequency power amplifier according to claim 1, characterized in that, The first power amplification unit, the second power amplification unit, and the third power amplification unit are integrated on the first chip using GaAa HBT technology; the control unit and the switching unit are integrated on the second chip using SOI technology.

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