Wafer heat treatment device

Abstract

A wafer heat treatment apparatus includes: a heat treatment plate; the plurality of conductive supporting columns are arranged on the heat treatment plate and used for placing a wafer to be treated, the wafer to be treated comprises a piezoelectric layer, an interdigital electrode structure located on the piezoelectric layer and a dielectric layer located on the interdigital electrode structure, and each conductive supporting column comprises a main body part and an end part located at the top of the main body part; the main body part is adjacent to the heat treatment plate, the end part is in a circular truncated cone shape, the end part is provided with an upper end face and a lower end face which are opposite, the lower end face is adjacent to the main body part, and the size of the upper end face is smaller than that of the lower end face, so that the abnormality that static electricity discharges through an interdigital electrode structure in a wafer to be treated is avoided; and possible mechanical damage of the conductive support columns to the surface of the to-be-processed wafer can be reduced.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a wafer heat treatment apparatus. Background Technology

[0002] Radio frequency (RF) front-end chips in wireless communication devices include power amplifiers, antenna switches, RF filters, multiplexers, and low-noise amplifiers. Among these, surface acoustic wave (SAW) filters have a high quality factor (Q value) and are currently the mainstream RF filters used in mobile phones, base stations, and other wireless communication devices.

[0003] A surface acoustic wave (SAW) filter typically includes a substrate, interdigitated electrode structures on the substrate, and a dielectric layer covering the interdigitated electrode structures. After forming the dielectric layer, it is etched using photolithography for electrical lead-out of the interdigitated electrode structures. The photolithography process involves coating a photoresist layer onto the dielectric layer surface. After high-temperature baking and curing, the photoresist layer is patterned through exposure and development. This patterned photoresist layer serves as a mask for etching the dielectric layer. The high-temperature baking and curing of the photoresist layer includes a baking process followed by a cooling process.

[0004] However, the process of cooling the photoresist layer using existing cooling devices severely affects the performance of surface acoustic wave filters and needs further improvement. Utility Model Content

[0005] The technical problem solved by this invention is to provide a wafer heat treatment device to improve the performance of surface wave filters.

[0006] To solve the above-mentioned technical problems, this utility model provides a wafer heat treatment apparatus, including: a heat treatment plate; and a plurality of conductive support pillars disposed on the heat treatment plate for placing a wafer to be processed. The wafer to be processed includes a piezoelectric layer, an interdigitated electrode structure located on the piezoelectric layer, and a dielectric layer located on the interdigitated electrode structure. Each conductive support pillar includes a main body and an end located at the top of the main body. The main body is adjacent to the heat treatment plate, and the end is frustum-shaped, having an upper end face and a lower end face opposite to each other. The lower end face is adjacent to the main body, and the size of the upper end face is smaller than the size of the lower end face.

[0007] Optionally, the diameter of the main body is equal to the diameter of the lower end face.

[0008] Optionally, the roughness of the upper surface ranges from 0.4 μm to 1.6 μm.

[0009] Optionally, the diameter of the upper end face ranges from 0.7 mm to 1.0 mm.

[0010] Optionally, the end face also has a side face, the angle between the side face and the lower end face being in the range of 20° to 30°.

[0011] Optionally, the heat treatment plate includes a circular area, and a plurality of conductive support pillars are placed in the circular area, with each conductive support pillar being equidistant from the center of the circular area.

[0012] Optionally, the number of conductive support pillars is greater than or equal to three.

[0013] Optionally, the number of conductive support pillars is three, and the positions of the three conductive support pillars form an equilateral triangle.

[0014] Optionally, the conductive support column can be raised and lowered.

[0015] Optionally, the heat treatment plate is a cold plate; it also includes a cold source for controlling the temperature of the cold plate.

[0016] Optionally, the heat treatment plate is a hot plate; it also includes a heat source for controlling the temperature of the hot plate.

[0017] Optionally, the heat source includes a heater, and the temperature of the hot plate can be adjusted by controlling the power of the heater.

[0018] Compared with the prior art, the technical solution of this utility model embodiment has the following beneficial effects:

[0019] In the wafer heat treatment apparatus provided by this utility model, a plurality of conductive support pillars are provided on the heat treatment plate. When the wafer to be processed is placed on the plurality of conductive support pillars, the static electricity in the wafer to be processed can be discharged by being conducted to the ground wire through the plurality of conductive support pillars, thereby avoiding abnormal discharge of static electricity through the interdigitated electrode structure in the wafer to be processed, which is beneficial to improving the performance of the surface wave filter formed by the wafer to be processed. In addition, the ends of the conductive support pillars are frustoconical, and the size of the upper end face is smaller than the size of the lower end face, which is beneficial to reducing the mechanical damage that the conductive support pillars may cause to the surface of the wafer to be processed.

[0020] Furthermore, the heat treatment plate is a cold plate. During the cooling process of the wafer to be processed, the static electricity in the wafer can be released by being guided to the ground wire through several of the conductive support pillars, thereby avoiding abnormal discharge of static electricity through the interdigitated electrode structure in the wafer.

[0021] Furthermore, the heat treatment plate is a hot plate. During the heating process of the wafer to be processed, the static electricity caused by the change in polarization intensity of the piezoelectric layer can be released by being guided to the ground wire through several of the conductive support pillars, thereby avoiding the accumulation of static electricity in the wafer to be processed and further reducing the abnormal discharge of static electricity through the interdigitated electrode structure in the wafer to be processed. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a cooling device.

[0023] Figures 2 to 5 A schematic diagram of the structure of a wafer heat treatment apparatus in one embodiment of this utility model. Detailed Implementation

[0024] It should be noted that the terms "surface" and "on" in this utility model are used to describe the relative spatial positional relationship and are not limited to whether there is direct contact.

[0025] As described in the background section, existing cooling devices require further improvement. A cooling device will now be described in conjunction with this description.

[0026] Figure 1 This is a schematic diagram of a cooling device.

[0027] Please refer to Figure 1 The cooling device includes a cold plate 100 and three support columns 101 disposed on the cold plate 100, and a cap 103 is provided at the top of each support column 101.

[0028] In the fabrication process of the surface wave filter, wafer 102 includes a piezoelectric layer, interdigitated electrode structures, and a dielectric layer covering the interdigitated electrode structures. During the etching process of the dielectric layer using photolithography, after coating the surface of wafer 102 with a photoresist layer, the photoresist layer is baked and cured using a heating device. Then, the photoresist layer is cooled using the aforementioned cooling device. Specifically, wafer 102 is placed on the cap 103 at the top of the support pillar 101, and the wafer 102 is cooled using a cooling plate 100. The cap 103 is made of polyimide and is used to prevent the end face of the support pillar 101 from causing scratches or other mechanical damage to wafer 102.

[0029] However, due to the temperature effect during the baking process, the polarization intensity of the piezoelectric layer changes. During the cooling process, free charges are released. Under the electrical isolation effect of the polyimide material, the static electricity in the wafer 102 cannot be released to the ground line, resulting in discharge at the interdigital electrode structure, which in turn affects the product yield.

[0030] To address the aforementioned technical problems, this utility model provides a wafer heat treatment apparatus in which a plurality of conductive support pillars are arranged on a heat treatment plate. When the wafer to be processed is placed on the plurality of conductive support pillars, the static electricity within the wafer can be discharged by being conducted to the ground wire through the plurality of conductive support pillars, thereby avoiding abnormal discharge of static electricity through the interdigitated electrode structure within the wafer and improving the performance of the surface wave filter subsequently formed from the wafer. In addition, the ends of the conductive support pillars are frustoconical, and the size of the upper end face is smaller than the size of the lower end face, which helps to reduce the mechanical damage that the conductive support pillars may cause to the surface of the wafer to be processed.

[0031] To make the above-mentioned objectives, features and beneficial effects of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0032] Figures 2 to 5 A schematic diagram of the structure of a wafer heat treatment apparatus in one embodiment of this utility model.

[0033] Please refer to Figures 2 to 5 , Figure 2 This is a top-down structural diagram. Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure along the EE1 direction. Figure 3 The dashed box indicates the placement of the wafer to be processed. Figure 4 This is a three-dimensional structural diagram of a conductive support column. Figure 5 The diagram shows the structure of the wafer to be processed. The wafer heat treatment apparatus includes: a heat treatment plate 201; and a plurality of conductive support pillars 202 disposed on the heat treatment plate 201 for placing the wafer to be processed 203. The wafer to be processed 203 includes a piezoelectric layer 2031, an interdigitated electrode structure 2032 located on the piezoelectric layer 2031, and a dielectric layer 2033 located on the interdigitated electrode structure 2032. Each conductive support pillar 202 includes a main body I and an end II located at the top of the main body I. The main body I is adjacent to the heat treatment plate 201. The end II is frustum-shaped and has an upper end face a and a lower end face b. The lower end face b is adjacent to the main body I. The size of the upper end face a is smaller than the size of the lower end face b.

[0034] Thus, the conductive support pillars 202 provided on the heat treatment plate 201 allow the static electricity within the wafer 203 to be grounded through the conductive support pillars 202 when the wafer 203 to be processed is placed on the conductive support pillars 202, thereby preventing abnormal discharge of static electricity through the interdigitated electrode structure 2032 within the wafer 203 and improving the performance of the surface wave filter formed from the wafer 203. In addition, the end II of the conductive support pillar 202 is frustoconical, and the size of the upper end face a is smaller than the size of the lower end face b, which helps to reduce the mechanical damage that the conductive support pillar 202 may cause to the surface of the wafer 203 to be processed.

[0035] In this embodiment, the conductive support column 202 is made of metal to obtain better conductivity.

[0036] In this embodiment, the main body I and the end portion II are integrally machined.

[0037] In other embodiments, the main body and the end portion may be processed separately and then connected by means of fastening or other methods.

[0038] The diameter r1 of the upper end face a ranges from 0.7 mm to 1.0 mm. In this embodiment, the diameter r1 of the upper end face a is 0.76 mm.

[0039] In this embodiment, the diameter r3 of the main body I is equal to the diameter r2 of the lower end face b.

[0040] In this embodiment, the roughness range of the upper surface a is 0.4 μm to 1.6 μm. The reason for choosing this roughness range is that a smaller roughness on the upper surface a helps reduce potential mechanical damage to the surface of the wafer 203 caused by the conductive support pillar 202. Furthermore, a roughness lower than 0.4 μm reduces the probability of scratches caused by displacement relative to the conductive support pillar 202 during wafer lifting. Additionally, a roughness greater than 1.6 μm facilitates cleaning of the conductive support pillar 202, reducing the probability of contamination on the back side of the wafer.

[0041] In this embodiment, the end portion II also has a side surface c, and the included angle α between the side surface c and the lower end surface b ranges from 20° to 30°.

[0042] In this embodiment, the heat treatment plate 201 includes a circular region 201C, and a plurality of conductive support pillars 202 are placed in the circular region 201C. Each conductive support pillar 202 is equidistant from the center A0 of the circular region 201C.

[0043] The number of conductive support columns 202 is greater than or equal to three.

[0044] In this embodiment, the number of conductive support pillars 202 is three.

[0045] In other embodiments, the number of conductive support pillars can be multiple. It should be noted that while a larger number of conductive support pillars allows for more stable placement of the wafer to be processed, it also increases costs and increases the risk of mechanical damage due to increased contact with the conductive support pillars. Therefore, an appropriate number of conductive support pillars can be selected based on the actual application.

[0046] In this embodiment, there are three conductive support pillars 202, and the three conductive support pillars 202 are located in an equilateral triangle.

[0047] In this embodiment, the conductive support column 202 is movable. The movable nature of the conductive support column 202 allows the wafer 203 to be processed to move away from or closer to the heat treatment plate 201, thereby adjusting the temperature rise or fall rate of the wafer 203.

[0048] In another embodiment, the conductive support pillar can be of a fixed height. The heating or cooling rate of the wafer to be processed can be controlled by adjusting the temperature of the heat treatment plate.

[0049] In this embodiment, the heat treatment plate 201 is a cold plate; the wafer heat treatment apparatus further includes a cold source (not shown in the figure) for controlling the temperature of the cold plate.

[0050] Here, the heat treatment plate 201 is used to cool down the wafer 203 to be processed. During the cooling process, the static electricity in the wafer 203 to be processed can be released by being conducted to the ground wire through a plurality of conductive support pillars 202, thereby avoiding abnormal discharge of static electricity through the interdigitated electrode structure 2032 in the wafer 203 to be processed.

[0051] In another embodiment, the heat treatment plate is a hot plate; the wafer heat treatment apparatus further includes a heat source for controlling the temperature of the hot plate. During the heating process of the wafer to be processed, the static electricity caused by the change in polarization intensity of the piezoelectric layer can be released by being guided to the ground wire through the several conductive support pillars, thereby avoiding the accumulation of static electricity in the wafer to be processed and further reducing the abnormal discharge of static electricity through the interdigitated electrode structure in the wafer to be processed.

[0052] The heat source includes a heater, and the temperature of the hot plate can be adjusted by controlling the power of the heater.

[0053] In other embodiments, when baking the wafer to be processed, the wafer to be processed can be placed on the hot plate provided by the present invention for heating, which can reduce the accumulation of static electricity in the wafer to be processed. After heating is completed, the wafer to be processed is placed on the cold plate provided by the present invention for cooling, which can be released by introducing the conductive support pillars to the ground wire, further reducing the abnormal discharge of static electricity through the interdigitated electrode structure in the wafer to be processed.

[0054] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A wafer heat treatment apparatus characterized by comprising: Comprising: a heat treatment plate; a plurality of conductive support columns disposed on the heat treatment plate for placing a wafer to be treated, the wafer to be treated comprising a piezoelectric layer, an interdigital electrode structure on the piezoelectric layer, and a dielectric layer on the interdigital electrode structure, each of the conductive support columns comprising a main body portion and an end portion on top of the main body portion, the main body portion being adjacent to the heat treatment plate, the end portion being frustoconical, and the end portion having opposite upper and lower end faces, the lower end face being adjacent to the main body portion, the upper end face having a smaller size than the lower end face.

2. The wafer heat treatment apparatus as recited in claim 1, wherein The diameter of the main body portion is equal to the diameter of the lower end face.

3. The wafer heat treatment apparatus as recited in claim 1, wherein The roughness of the upper end face ranges from 0.4 μm to 1.6 μm.

4. The wafer heat treatment apparatus as recited in claim 1, wherein The diameter of the upper end face ranges from 0.7 mm to 1.0 mm.

5. The wafer thermal processing apparatus of claim 1, wherein The end portion further has a side face, and the included angle between the side face and the lower end face ranges from 20° to 30°.

6. The wafer thermal processing apparatus of claim 1, wherein The heat treatment plate comprises a circular region, and each of the conductive support columns is disposed within the circular region at a distance equal to the distance from the center of the circular region.

7. The wafer thermal processing apparatus of claim 1, wherein The number of the conductive support columns is greater than or equal to three.

8. The wafer heat treatment apparatus as recited in claim 7, wherein The number of the conductive support columns is three, and the positions of the three conductive support columns form an equilateral triangle.

9. The wafer thermal processing apparatus of claim 1, wherein, The conductive support columns are liftable.

10. The wafer thermal processing apparatus of claim 1, wherein The heat treatment plate is a cold plate; further comprising a cold source for controlling the temperature of the cold plate.

11. The wafer thermal processing apparatus of claim 1, wherein The heat treatment plate is a hot plate; further comprising a heat source for controlling the temperature of the hot plate.

12. The wafer thermal processing apparatus of claim 11 wherein, The heat source comprises a heater, and the temperature of the hot plate can be adjusted by controlling the power of the heater.

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