Novel surge simulation device

Abstract

The utility model relates to a novel surge simulation device applied to the field of power supply technical devices, which comprises an input and output circuit, the input and output circuit comprises an input terminal J1, an output terminal J3, field-effect tubes Q1 to Q6, diodes D1 and D2, resistors R1 and R12 and capacitors C10-C13, grid electrodes of the field-effect tubes Q1 and Q2 are connected to a pin 1 and a pin 2 of the input terminal J1, and grid electrodes of the field-effect tubes Q1 and Q2 are connected to a pin 2 of the output terminal J3. The grid electrodes of the field effect transistors Q3, Q4 and Q6 are connected to the pins 3 and 4 of the input terminal J1, the diode D1 is connected to the source electrodes of the field effect transistors Q1 and Q2, and the terminal J2 is grounded. In the novel surge simulation device, the advantages of the device are obvious, the 60A current and 150V voltage can pass through the device, the surge signal simulation range is greatly widened, the test requirements of numerous devices are met, and the test efficiency is improved. And simple and reliable devices are adopted, so that the number of peripheral devices is reduced, the production cost is effectively reduced, and the function of passing through relatively large current and surge voltage is realized.

Description

Technical Field

[0001] This utility model relates to a surge simulation device, and more particularly to a novel surge simulation device applied in the field of power supply technology devices. Background Technology

[0002] Surge simulation devices typically operate on the principle of special processing of electrical energy to generate surge signals similar to those encountered in actual operating conditions. For example, some devices perform specific transformations and modulations on the input alternating current, while newer devices utilize external power signals, controlled and converted by internal circuitry, to generate surge voltages and currents according to set requirements, thereby simulating surge phenomena.

[0003] Chinese Patent Publication No. CN215375575U discloses a surge protector monitoring device. A switch quantity monitoring circuit is electrically connected to an MCU control unit. The switch quantity monitoring circuit collects switch quantity signals to monitor the switch quantity status; a temperature monitoring circuit collects analog signals from a temperature probe to monitor the surge protector temperature; and a leakage current monitoring circuit collects analog signals from a leakage current sensor to monitor the current leakage of the surge protector. This invention enables the monitoring of relevant parameters of the surge protector, achieving dynamic management of the surge protector, timely acquisition of status information to prevent faults, or immediate detection of faults.

[0004] While existing surge simulation devices on the market can simulate most conditions, for devices such as filters, existing surge testing equipment still has the drawback of being able to handle relatively small currents. In addition, these devices are expensive and, as power sources themselves, cannot directly output power signals, resulting in a waste of resources and costs. Utility Model Content

[0005] In view of the above-mentioned prior art, the technical problem to be solved by this utility model is that existing surge testing equipment still has the disadvantage of being able to pass relatively small currents. At the same time, such equipment is expensive and, as a power source itself, cannot directly output power signals, resulting in a waste of resources and costs.

[0006] To solve the above problems, this utility model provides a novel surge simulation device, including an input / output circuit. The input / output circuit includes an input terminal J1, an output terminal J3, field-effect transistors Q1-Q6, diodes D1 and D2, resistors R1 and R12, and capacitors C10-C13. The gates of field-effect transistors Q1 and Q2 are connected to pins 1 and 2 of the input terminal J1, the gates of field-effect transistors Q3, Q4, and Q6 are connected to pins 3 and 4 of the input terminal J1, diode D1 is connected to the source of field-effect transistors Q1 and Q2, and terminal J2 is grounded.

[0007] The aforementioned new surge simulation device has significant advantages. It can not only pass 60A current and 150V voltage, greatly expanding the surge signal simulation range and meeting the testing needs of many devices, but also effectively reduces production costs by using simple and reliable devices and reducing the number of peripheral devices, thus enabling it to pass larger currents and surge voltages.

[0008] As a further improvement to this application, capacitors C10, C11, C12, and C13 are connected to pins 1, 2, 3, and 4 of input terminal J1, respectively, and the other ends of each are grounded.

[0009] As a further improvement of this application, R1 and R12 are connected in series, with one end connected to D1, D2 and pins 1 and 2 of the output terminal J3, and the other end connected in parallel to the gate of the field-effect transistor Q5. The source of Q5 is grounded, and pins 3 and 4 of the output terminal J3 are grounded.

[0010] As a further improvement of this application, the input section is connected to the power supply voltage and surge voltage, and the power supply voltage supplies power to the lower-level power supply, as well as the MOSFET drive circuit and control circuit.

[0011] As another improvement of this application, Q3, Q4, and Q6 are switches for controlling the power supply voltage, and Q1 and Q2 are switches for controlling the surge voltage. The power supply is converted into a surge signal by connecting an external power supply through the input terminal J1.

[0012] As a further improvement to this application, Q5 is a switch for controlling the discharge circuit, used to quickly stop the surge signal.

[0013] As a further improvement to this application, the input / output circuit also includes control switches SW1, SW2, and SW3, which control the pulse width and frequency of the surge by controlling the switching sequence of SW1, SW2, and SW3.

[0014] In summary, in the input / output circuit, the field-effect transistors (Q1-Q6), diodes (D1, D2), resistors (R1, R12), and capacitors (C10-C13) are connected in a specific manner. For example, the gates of field-effect transistors Q1 and Q2 are connected to pins 1 and 2 of input terminal J1, and the gates of Q3, Q4, and Q6 are connected to pins 3 and 4 of J1. The input section is connected to the power supply voltage and surge voltage. The power supply voltage powers the lower-level power supply and related circuits. The power supply voltage is controlled by Q3, Q4, and Q6, and the surge voltage is controlled by Q1 and Q2. The input terminal J1 connects to an external power supply to convert power into a surge signal. Q5 controls the discharge circuit to quickly stop the surge signal. At the same time, by controlling the switching sequence of SW1, SW2, and SW3, the pulse width and frequency of the surge can be precisely adjusted. This device has significant advantages. It can not only handle 60A current and 150V voltage, greatly expanding the surge signal simulation range and meeting the testing needs of many devices, but also effectively reduces production costs by using simple and reliable components and reducing the number of external components, thus enabling the device to handle larger currents and surge voltages. Attached Figure Description

[0015] Figure 1 This is a circuit schematic diagram of the first embodiment of this application;

[0016] Figure 2 This is a schematic diagram of the switching circuit of the control discharge circuit according to the first embodiment of this application;

[0017] Figure 3 This is a schematic diagram of the output terminal J3 circuit according to the first embodiment of this application. Detailed Implementation

[0018] The two embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0019] First implementation method:

[0020] Figure 1-3 A novel surge simulation device is shown, including an input / output circuit. The input / output circuit includes an input terminal J1, an output terminal J3, field-effect transistors Q1-Q6, diodes D1 and D2, resistors R1 and R12, and capacitors C10-C13. The gates of field-effect transistors Q1 and Q2 are connected to pins 1 and 2 of the input terminal J1, the gates of field-effect transistors Q3, Q4, and Q6 are connected to pins 3 and 4 of the input terminal J1, diode D1 is connected to the source of field-effect transistors Q1 and Q2, and terminal J2 is grounded.

[0021] Figure 1-3The diagram shows capacitors C10, C11, C12, and C13 connected to pins 1, 2, 3, and 4 of input terminal J1, with the other ends grounded. R1 and R12 are connected in series, one end connected to D1, D2, and pins 1 and 2 of output terminal J3, and the other end connected in parallel to the gate of MOSFET Q5. The source of Q5 is grounded, and pins 3 and 4 of output terminal J3 are grounded. The input section is connected to the power supply voltage and surge voltage. The power supply voltage powers the lower-level power supply and also powers the MOSFET drive circuit and control circuit. Q3, Q4, and Q6 are switches that control the power supply voltage, and Q1 and Q2 are switches that control the surge voltage. The power supply is converted into a surge signal through the external power supply connected to input terminal J1. Q5 is a switch that controls the discharge circuit to quickly stop the surge signal. The input and output circuit also includes control switches SW1, SW2, and SW3. By controlling the switching sequence of SW1, SW2, and SW3, the pulse width and frequency of the surge are controlled.

[0022] Figure 1-3 This surge simulation device mainly consists of input and output circuits. In the schematic diagram of the input and output section, the gates of MOSFETs Q1 and Q2 are connected to pins 1 and 2 of input terminal J1, and the gates of MOSFETs Q3, Q4, and Q6 are connected to pins 3 and 4 of input terminal J1. Diode D1 is connected to the source of Q1 and Q2. Terminal J2 is grounded. Capacitors C10, C11, C12, and C13 are connected to pins 1, 2, 3, and 4 of J1, respectively, with the other end grounded. R1 and R12 are connected in series, with one end connected to D1, D2, and pins 1 and 2 of output terminal J3, and the other end connected in parallel to the gate of MOSFET Q5. The source of Q5 is grounded, and pins 3 and 4 of terminal J3 are grounded. The input section is connected to the power supply voltage and the surge voltage. The power supply voltage not only powers the lower-level power supply but also powers the MOSFET drive circuit and the control circuit. In this circuit, Q3, Q4, and Q6 are switches that control the power supply voltage, while Q1 and Q2 are switches that control the surge voltage. An external power supply connected to input terminal J1 can directly convert the power supply into a surge signal. Q5 is a switch that controls the discharge circuit, used to quickly stop the surge signal. By controlling the switching sequence of SW1, SW2, and SW3, the pulse width and frequency of the surge can be precisely controlled. The signal simulation range is wide and can handle large currents. This device can handle 60A of current and 150V of voltage, greatly expanding the range of simulating surge signals and meeting the testing needs of more devices. Surge signals are generated by controlling signals from a mature external power supply. The selected components are simple and reliable, and the number of peripheral components is small, effectively reducing production costs and enabling it to handle larger currents and larger surge voltages.

[0023] In light of current practical needs, the above-described embodiments adopted in this application are not limited to these. Any changes made within the scope of knowledge possessed by those skilled in the art without departing from the concept of this application still fall within the protection scope of this utility model.

Claims

1. A novel surge simulation device, characterized in that: The circuit includes an input / output circuit, which includes an input terminal J1, an output terminal J3, field-effect transistors Q1-Q6, diodes D1 and D2, resistors R1 and R12, and capacitors C10-C13. The gates of field-effect transistors Q1 and Q2 are connected to pins 1 and 2 of the input terminal J1, the gates of field-effect transistors Q3, Q4, and Q6 are connected to pins 3 and 4 of the input terminal J1, the diode D1 is connected to the source of field-effect transistors Q1 and Q2, and the terminal J2 is grounded.

2. The novel surge simulation device according to claim 1, characterized in that: The capacitors C10, C11, C12, and C13 are connected to pins 1, 2, 3, and 4 of the input terminal J1, respectively, and the other end of each is grounded.

3. The novel surge simulation device according to claim 1, characterized in that: R1 and R12 are connected in series, with one end connected to D1, D2 and pins 1 and 2 of the output terminal J3, and the other end connected in parallel to the gate of the field-effect transistor Q5. The source of Q5 is grounded, and pins 3 and 4 of the output terminal J3 are grounded.

4. The novel surge simulation device according to claim 1, characterized in that: The input section is connected to the power supply voltage and surge voltage, and the power supply voltage supplies power to the lower-level power supply, as well as the MOS transistor drive circuit and control circuit.

5. The novel surge simulation device according to claim 1, characterized in that: Q3, Q4, and Q6 are switches that control the power supply voltage, and Q1 and Q2 are switches that control the surge voltage. The power supply is converted into a surge signal by connecting an external power source through the input terminal J1.

6. The novel surge simulation device according to claim 3, characterized in that: Q5 is a switch for controlling the discharge circuit, used to quickly stop surge signals.

7. The novel surge simulation device according to claim 1, characterized in that: The input / output circuit also includes control switches SW1, SW2, and SW3. By controlling the switching sequence of SW1, SW2, and SW3, the pulse width and frequency of the surge are controlled.

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