Chip testing device
By designing a chip testing device, the problem of incomplete chip functional testing was solved, the integrity of the signal chain was achieved, an interface with the serializer was provided, and complete testing of the Deserializer chip was realized.
Patent Information
- Application Number
- CN202520095519.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-15
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2035-01-15
AI Technical Summary
In existing technologies, chip functional testing is incomplete, and there is a lack of interface with the serializer, resulting in an incomplete signal chain.
Design a chip testing device, including a system power supply circuit, a deserializer power supply circuit, peripheral components of the test board, a deserializer integrated circuit and a controller, set up multiple interfaces to realize electrical connection between modules, and reserve an interface with the serializer.
The complete testing of the Deserializer chip's functionality was achieved, ensuring the integrity of the signal chain.
Smart Images
Figure CN223955741U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to chip testing technical field, concretely relates to a chip testing device. BACKGROUND
[0002] The design of the high-frequency Serializer / Deserializer chip is to meet the needs of wide frequency band and long distance signal transmission in the industry and automotive field, and the transmission of bidirectional signals can be realized through the coaxial cable of not more than 15 meters at a frequency of dozens of GHz of the MIPI / CSI (Camera Serial Interface) / PHY (physical layer chip) protocol, so that the market needs are extremely high, but the design difficulty is extremely great.
[0003] In the prior art, the chip function test is incomplete, and the interface with the serializer is lacking, so that the signal chain is incomplete. UTILITY MODEL CONTENTS
[0004] The utility model aims at providing a chip testing device, and solves the problems of incomplete chip function test, lack of interface with the serializer and incomplete signal chain in the related art.
[0005] Therefore, the utility model provides a chip testing device, which comprises a system power supply circuit, a deserializer power supply circuit, test board peripheral components, a deserializer integrated circuit and a controller, the system power supply circuit is electrically connected with the test board peripheral components, the deserializer power supply circuit is electrically connected with the deserializer integrated circuit, the test board peripheral components are electrically connected with the deserializer integrated circuit, and the controller is electrically connected with the test board peripheral components and the deserializer integrated circuit.
[0006] Preferably, the power supply conversion device is electrically connected with the system power supply circuit and the deserializer power supply circuit.
[0007] Preferably, a voltage stabilizer is arranged in the system power supply circuit.
[0008] Preferably, a voltage stabilizer is arranged in the deserializer power supply circuit.
[0009] Preferably, the deserializer integrated circuit is provided with a first GPIO / I2C interface, a CSI interface, an SCCB interface and an APHY interface.
[0010] Preferably, the controller is provided with a second GPIO / I2C interface and a UART interface.
[0011] Preferably, the first GPIO / I2C interface on the deserializer integrated circuit is electrically connected with the second GPIO / I2C interface on the controller.
[0012] Preferably, further comprising a control host, the control host is electrically connected with the controller through a UART interface.
[0013] Preferably, further comprising a serializer, the deserializer integrated circuit is electrically connected with the serializer through an APHY interface.
[0014] Preferably, further comprising a control system, the control system is electrically connected with the deserializer integrated circuit through a CSI interface and a SCCB interface.
[0015] Advantages:
[0016] 1. The utility model provides a chip testing device, on the basis that the chip and circuit of each module have been completely verified, organically combines each module, realizes the complete test to Deserializer chip function, reserves the interface with Serializer simultaneously, can realize the complete test of signal chain. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to more clearly illustrate the technical scheme in the embodiment of the utility model or prior art, the following will be briefly introduced to the drawing needed to be used in the embodiment or prior art description, obviously, the drawing in the following description only some embodiments of the utility model, for ordinary skilled person in the art, under the premise of not paying creative labor, other drawings can also be obtained according to these drawings.
[0018] Figure 1 It is the circuit schematic diagram of embodiment 1 of a kind of chip testing device provided by the utility model.
[0019] Figure 2 It is the circuit schematic diagram of signal chain complete test of embodiment 1 of a kind of chip testing device provided by the utility model.
[0020] In the figure, 1-power conversion device, 2-system power supply circuit, 3-deserializer power supply circuit, 4-test board peripheral component, 5-deserializer integrated circuit, 51-first GPIO / I2C interface, 52-CSI interface, 53-APHY interface, 54-SCCB interface, 6-controller, 61-second GPIO / I2C interface, 62-UART interface, 7-control system, 8-control host, 9-serializer. DETAILED DESCRIPTION
[0021] The content of the present application can be more easily understood by referring to the following detailed description of the preferred embodiments of the present application and included drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In case of conflict, the present specification, including definitions, will control.
[0022] Embodiment 1
[0023] Provided is a chip testing device as shown in Figure 1 The chip testing device comprises:
[0024] The power supply circuit module comprises a power conversion device 1, a system power supply circuit 2 and a deserializer power supply circuit 3. The power conversion device 1 is electrically connected to the system power supply circuit 2 and the chip power supply.
[0025] The power conversion device 1 converts the input 12V voltage to 5V voltage. The system power supply circuit 2 and the deserializer power supply circuit 3 are provided with voltage stabilizers (LDO). The system power supply circuit 2 requires different voltages including 5V, 3.3V and 1.8V, and two 5V-3.3V LDO and 5V-1.8V LDO are set according to the circuit requirements, i.e. converting 5V voltage to 3.3V and 1.8V. The deserializer power supply circuit 3 requires different voltages including 1.8V, 1.1V and 2.5V, and 5V-1.8V LDO, 5V-1.1V LDO and 5V-2.5V LDO are set according to the circuit requirements.
[0026] The system power supply circuit 2 is electrically connected to the test board peripheral components 4, the deserializer power supply circuit 3 is electrically connected to the deserializer integrated circuit 5, the test board peripheral components 4 are electrically connected to the deserializer integrated circuit 5 (Deserializer IC), and the controller (MCU) 6 is electrically connected to the test board peripheral components and the deserializer integrated circuit 5.
[0027] The deserializer integrated circuit 5 is provided with a first GPIO / I2C interface 51, a CSI interface 52, an APHY interface 53 and an SCCB interface 54. The controller 6 is provided with a second GPIO / I2C interface 61 and a UART interface 62. The first GPIO / I2C interface 51 on the deserializer integrated circuit 5 is electrically connected to the second GPIO / I2C interface 61 on the controller 6.
[0028] The control host 8 is also included, which is electrically connected to the controller 6 through the UART interface 62.
[0029] Preferably, it also includes a serializer 9, the deserializer integrated circuit being electrically connected to the serializer 9 via an APHY interface 53.
[0030] Preferably, it also includes a control system 7 (Raspberry PI), which is electrically connected to the deserializer integrated circuit 5 via a CSI interface 52 and an SCCB interface 54.
[0031] like Figure 2 The diagram shows a complete signal chain transmission system and testing system. The control system 7 can communicate with the serializer 9 via Linux system software and USB / HDMI interfaces. The serializer 9 converts the video signal from the camera 7 into a serial signal and transmits it to a deserializer via a coaxial cable. The deserializer converts the transmitted signal into a parallel signal and finally imports it into the computer PC1 via the control system 7. The control host 8 is used solely to control the serializer 9 and the deserializer.
[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A chip testing apparatus characterized by comprising: The system comprises a system power supply circuit, a deserializer power supply circuit, test board peripheral components, a deserializer integrated circuit and a controller, the system power supply circuit is electrically connected with the test board peripheral components, the deserializer power supply circuit is electrically connected with the deserializer integrated circuit, the test board peripheral components are electrically connected with the deserializer integrated circuit, and the controller is electrically connected with the test board peripheral components and the deserializer integrated circuit. The system further comprises a power conversion device, which is electrically connected with the system power supply circuit and the deserializer power supply circuit.
2. The chip testing apparatus according to claim 1, wherein The system power supply circuit is provided with a voltage stabilizer.
3. The chip testing apparatus according to claim 2, wherein The deserializer power supply circuit is provided with a voltage stabilizer.
4. The chip testing apparatus according to claim 2, wherein The deserializer integrated circuit is provided with a first GPIO / I2C interface, a CSI interface, an SCCB interface and an APHY interface.
5. The chip testing apparatus according to claim 1, wherein The controller is provided with a second GPIO / I2C interface and a UART interface.
6. The chip testing apparatus according to claim 5, wherein The first GPIO / I2C interface on the deserializer integrated circuit is electrically connected with the second GPIO / I2C interface on the controller.
7. The chip testing apparatus according to claim 6, wherein The system further comprises a control host, which is electrically connected with the controller through the UART interface.
8. The chip testing apparatus according to claim 7, wherein The system further comprises a serializer, which is electrically connected with the deserializer integrated circuit through the APHY interface.
9. The chip testing apparatus according to claim 7, wherein The system further comprises a control system, which is electrically connected with the deserializer integrated circuit through the CSI interface and the SCCB interface.
10. The chip testing apparatus according to claim 7, wherein