DRAM (Dynamic Random Access Memory) and end-side equipment
By using the ONFI protocol and 3D packaging technology, the problems of SOC chip area and power consumption have been solved, enabling efficient control and expansion of DRAM memory, simplifying system structure, and improving storage density and data access efficiency.
Patent Information
- Application Number
- CN202520667759.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-09
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2035-04-09
AI Technical Summary
Existing SOC chips require different interfaces (such as UFS/eMMC, DDR) to connect to different storage media, resulting in large chip area overhead, increased power consumption and complex system architecture.
The ONFI protocol is used to control the DRAM memory, and the storage function and interface function are separated into different chips through three-dimensional packaging and CE Reduction mechanism. The refresh command of ONFI protocol is used to realize the refresh control of DRAM memory, shorten the interconnection distance, and share channel signals and control signals.
It reduces the area and power consumption of SOC chips, increases storage density and data transfer rate, simplifies system architecture, expands storage capacity, and meets diverse application needs.
Smart Images
Figure CN223956070U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to chip technology field, specifically relates to a DRAM memory and end side device. BACKGROUND
[0002] With the increasing richness of the function of system on chip (SOC) host, the storage demand of different types of data also continues to grow. In the selection of storage medium, it is mainly divided into flash (FLASH) and dynamic random access memory (DRAM) two kinds.
[0003] Flash (FLASH) is mainly used for storing data that needs to be saved after power failure. Among them, the NAND FLASH with large capacity is most widely used. The SOC chip is usually connected to the external storage system through the universal flash storage (UFS) or embedded multimedia card (eMMC) protocol. While in the internal storage system, the storage system control chip is connected to multiple FLASH dies through the open NAND flash interface (ONFI) protocol.
[0004] Dynamic random access memory (DRAM) is mainly used for the intermediate data that needs to be stored in the running process of the system. The SOC chip needs to be connected with DRAM through the double data rate (DDR) interface protocol.
[0005] However, the above storage scheme has the following problems:
[0006] Complex interface: the SOC chip needs different interfaces (such as UFS / eMMC, DDR) to connect to different storage media, resulting in large chip area overhead, especially the physical layer (PHY) part of DDR.
[0007] Increased power consumption: different interfaces and memory types increase the power consumption of the system.
[0008] System bloated: the existence of multiple memories and interfaces makes the system structure complex and bloated.
[0009] In view of the above problems, the present field needs a new storage scheme to reduce the area overhead of SOC chip, reduce power consumption and simplify the system structure. UTILITY MODEL CONTENT
[0010] In view of the above problems, the utility model provides a DRAM memory, which is characterized by comprising:
[0011] a plurality of memory blocks for storing data;
[0012] a plurality of memory block controllers corresponding to the plurality of memory blocks, each memory block controller being capable of controlling writing or reading data to or from the corresponding memory block;
[0013] an ONFI interface controller connected to the plurality of memory block controllers respectively, capable of sending instructions to the plurality of memory block controllers to control the operation of the plurality of memory blocks; and
[0014] an IO interface connected to the ONFI interface controller and configured to be connected to a main control circuit, receiving control signals of the main control circuit and sending to the ONFI interface controller.
[0015] The DRAM memory provided by the utility model, the IO interface is used for input and output conversion of ONFI signal of the main control circuit (host chip / SoC chip);The ONFI interface controller is used for distributing the received bus protocol naming and data to each memory block, receiving the data read from each memory block and gating output, and can also process the state of the DRAM memory and calibrate it. Since the ONFI protocol is simpler than the DDR protocol, the circuit structure of its controller is also simpler, and the power is also lower. In addition, the ONFI protocol control has fewer pins, which can save more main control circuit pins.
[0016] Optionally, the ONFI interface controller is configured to refresh the plurality of memory blocks using its refresh instruction.
[0017] The memory block controller mainly controls the reading and writing of each memory block and controls the refresh strategy of the internal memory array circuit of the memory block. Specifically, since the ONFI protocol instruction set itself contains an erase instruction originally used for data clearing of the FLASH memory, in the embodiment, the instruction is used for the refresh strategy control of the DRAM memory. Such design realizes the refresh control of the DRAM memory by using the existing ONFI protocol instructions without additional introduction of hardware resources, compared with the existing DRAM memory which needs to specially set a refresh signal generation circuit, saves space and cost.
[0018] Optionally, the plurality of memory blocks and the plurality of memory block controllers are integrated into at least one DRAM memory chip, and the IO interface and the ONFI interface controller are integrated into a control chip.
[0019] In the utility model, the circuit of storage function and the circuit of interface function are separately arranged in different chips, so that the circuit of interface function and the circuit of storage function can be manufactured by different processes, so that the DRAM storage chip has higher storage density, and when the DRAM storage chip is configured with multiple chips, the same control chip can be shared, so that the space of DRAM storage is saved and the cost is reduced.
[0020] Optionally, the at least one DRAM storage chip and the control chip are connected by a three-dimensional packaging process.
[0021] In this way, the following technical effects are achieved:
[0022] Reduce chip area: by three-dimensional packaging, the DRAM storage chip and the control chip are stacked together, thereby reducing the area occupied by them in the plane. This is particularly important for SOC chips with limited area.
[0023] Improve storage density: three-dimensional packaging can effectively improve the storage density and integrate more storage capacity in a limited space.
[0024] Shorten the interconnection distance: the DRAM storage chip and the control chip are connected by TSV (through silicon via) or Hybrid bonding, thereby shortening the interconnection distance between them and reducing signal transmission delay and power consumption.
[0025] Improve data transmission rate: due to the shortened interconnection distance, the data transmission rate can be improved, thereby improving the overall performance of the system.
[0026] In order to achieve the above-mentioned utility model purposes, the utility model provides a kind of end side equipment, application DRAM storage described above, comprising:
[0027] Main control circuit;And
[0028] At least one DRAM target, connected with the main control circuit, and can be based on the instruction of the main control circuit and run;
[0029] Wherein, each DRAM target includes multiple DRAM storage capable of synchronously receiving control signal.
[0030] Optionally, the multiple DRAM storage included by each DRAM target shares the same address.
[0031] Optionally, the external network interface and external node of adjacent DRAM storage are interconnected to form a daisy chain.
[0032] Optionally, the main control circuit accesses and controls the corresponding DRAM target based on the CE Reduction mechanism of the ONFI protocol and an address.
[0033] The technical effect of such arrangement is:
[0034] Expand DRAM storage capacity: Through the CE Reduction mechanism, multiple DLUNs can be connected together without the need to increase additional pins. In this way, the main control circuit (host / SoC chip) can connect more DRAM storage chips under the same number of pins, thereby expanding the DRAM storage capacity.
[0035] Share channel signals: Multiple DRAM targets can share one channel signal of the host, and different CE signals are used to distinguish between different DRAM targets. This way can effectively utilize channel resources and improve data transmission efficiency.
[0036] Flexible topology: The main control circuit can be provided with multiple channels, and the required DRAM storage size can be flexibly topological according to actual needs. This scheme can flexibly configure the DRAM storage capacity according to different application scenarios to meet different needs.
[0037] Optionally, the end-side device further comprises a FLASH memory and an external storage control chip, the DRAM memory and the FLASH memory are connected with the external storage control chip based on the ONFI protocol, and the external storage control chip is connected with the main control circuit.
[0038] Optionally, the main control circuit is an SoC chip, and the external storage control chip is connected with the SoC chip in a UFS protocol, an SD protocol or an emmc protocol.
[0039] The core of the utility model lies in using ONFI protocol to replace traditional DDR protocol to control DRAM memory, and a series of optimization and extension are carried out on this basis. Its main technical effect can be summarized as the following points:
[0040] Reduce the area and power consumption of the main control chip: Because the ONFI protocol is simpler than the DDR protocol, its controller circuit structure is also simpler, occupies less chip area, and has lower power consumption.
[0041] Reduce the number of pins of the main control chip: ONFI protocol control requires fewer pins, which can save the pin resources of the main control chip, so that it can be used for other functions.
[0042] Simplified DRAM memory control: The ONFI interface controller can manage multiple memory blocks uniformly, simplifying the control of DRAM memory by the host chip.
[0043] Implement DRAM memory refresh control: Using the existing refresh instruction of the ONFI protocol, the refresh control of the DRAM memory can be implemented without additional hardware resources, saving space and cost.
[0044] Increase storage density: By separating the circuit for storage function and the circuit for interface function on different chips and using three-dimensional packaging technology, the storage density of the DRAM memory can be improved.
[0045] Flexible storage configuration: Different types and capacities of memories can be flexibly configured according to actual needs to meet different application scenarios.
[0046] Improve data access efficiency: The external storage control chip can optimize the transmission and management of data between the DRAM memory and the FLASH memory, improving data access efficiency.
[0047] Easy to extend: The scheme is easy to extend, and the number and type of memories can be increased as needed to meet future application needs.
[0048] Simplify control logic: By grouping multiple DLUNs into a DRAM target, the host only needs to control one CE signal and one address to access all DLUNs in the target, simplifying the control logic.
[0049] Increase bandwidth: Since multiple DLUNs can be accessed simultaneously, this architecture can improve the bandwidth of the storage system.
[0050] Logical unity: Combining multiple DLUNs into a DRAM target can make the storage system more logically unified, facilitating management and use.
[0051] In summary, the utility model discloses a DRAM memory controlled by the ONFI protocol, combined with three-dimensional packaging, CEReduction mechanism and other technologies, which reduces cost, power consumption and chip area while improving storage density, data access efficiency and system flexibility, meeting diversified application needs. BRIEF DESCRIPTION OF DRAWINGS
[0052] Figure 1 is the structure schematic diagram of the DRAM memory and the end side equipment provided by the embodiment of the utility model.
[0053] Figure 2 is the structure schematic diagram of the DRAM memory and the end side equipment provided by the embodiment of the utility model.
[0054] Figure 3 is a structural schematic view of the DRAM memory and the end-side device provided in the embodiment of the present application.
[0055] Figure 4 is a structural schematic view of the DRAM target provided in the embodiment of the present application.
[0056] Figure 5 is a structural schematic view of the end-side device provided in the embodiment of the present application.
[0057] Figure 6 is a structural schematic view of the end-side device provided in the embodiment of the present application. DETAILED DESCRIPTION
[0058] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.
[0059] As shown in Figure 1 The present embodiment provides a DRAM memory 100, comprising: a plurality of memory blocks 10 for storing data; a plurality of memory block controllers 20 arranged corresponding to the plurality of memory blocks 10, capable of controlling the corresponding memory blocks 10 to write or read data; an ONFI interface controller 30 connected with the plurality of memory block controllers 20 respectively, capable of sending instructions to the plurality of memory block controllers 20 to control the operation of the plurality of memory blocks 10; an IO interface 40 connected with the ONFI interface controller 30 and configured to be connected with a main control circuit 200, receiving control signals of the main control circuit 200 and sending to the ONFI interface controller 30.
[0060] The DRAM memory 100 provided in the present embodiment, the IO interface 40 is used for input and output conversion of the ONFI signal of the main control circuit 200 (host chip / SoC chip); the ONFI interface controller 30 is used for distributing the received bus protocol naming and data to each memory block 10, receiving the data read from each memory block 10 and gating output, and also capable of processing the state of the DRAM memory 100 and performing calibration. Since the ONFI protocol is simpler than the DDR protocol, the circuit structure of the controller is also simpler, and the power is also lower. In addition, the ONFI protocol control has fewer pins, which can save more pins of the main control circuit 200.
[0061] Optionally, the ONFI interface controller 30 is configured to refresh the plurality of memory blocks using its refresh instructions.
[0062] The main function of the memory block controller 20 is to control the read and write operations of each memory block 10 and to control the refresh strategy of the internal storage array circuit of the memory block 10. Specifically, since the ONFI protocol instruction set itself contains erase instructions originally used to clear data from FLASH memory, in this embodiment, these instructions are used to control the refresh strategy of DRAM memory 100. With this design, the refresh control of DRAM memory 100 can be realized by using the existing instructions of the ONFI protocol without introducing new instructions. Compared with the existing DRAM memory that requires a dedicated refresh signal generation circuit, this saves space and cost.
[0063] Furthermore, since the ONFI protocol is simpler than the DDR protocol, its interface controller structure is simpler, resulting in lower power consumption for the DRAM memory 100. At the same time, because fewer pins are required for control based on the ONFI protocol, the host chip / SoC connected to the DRAM memory 100 can control the DRAM memory 100 using fewer pins.
[0064] Optionally, such as Figure 2 As shown, in another embodiment, the DRAM memory includes at least one DRAM memory chip 110 and a control chip 120. The control chip 120 includes an I / O interface 40 and an ONFI interface controller 30. The DRAM memory chip 110 includes multiple memory blocks 10 and multiple memory block controllers 20 corresponding to the multiple memory blocks 10. In this embodiment, the circuitry for the storage function and the circuitry for the interface function are separately disposed on different chips. This arrangement allows the circuitry for the interface function and the circuitry for the storage function to be manufactured using different processes. By placing the interface circuitry / control circuitry, which occupies a larger chip size, on the control chip 120, the DRAM memory chip 110 has more space to accommodate the storage array, thereby enabling the DRAM memory chip 110 to have a higher storage density. On the other hand, when multiple DRAM memory chips 110 are configured, the space of the DRAM memory is saved and the cost is reduced by sharing the same control chip 120.
[0065] Specifically, at least one DRAM memory chip 110 and a control chip 120 are connected using a three-dimensional packaging process, such as... Figure 3 As shown, when there are multiple DRAM memory chips 110, each DRAM memory chip 110 is connected to the control chip 120 through TSV, Hybrid bonding, or other means.
[0066] With such an arrangement, the following technical effects are achieved:
[0067] Reduced chip area: By 3D packaging, the DRAM memory chips and the control chip are stacked together, reducing the area they occupy on the plane. This is particularly important for SOC chips with limited area.
[0068] Improved storage density: 3D packaging can effectively improve storage density, integrating more storage capacity in limited space.
[0069] Shortened interconnection distance: DRAM memory chips and control chips are connected through TSV (Through Silicon Via) or Hybrid bonding, etc., shortening the interconnection distance between them, thereby reducing signal transmission delay and power consumption.
[0070] Improved data transmission rate: Due to the shortened interconnection distance, the data transmission rate can be improved, thereby improving the overall performance of the system.
[0071] Reduced power consumption: Shortening the interconnection distance can reduce energy loss during signal transmission, thereby reducing power consumption.
[0072] Optionally, Figures 1 to 3 Each DRAM memory shown in the figure is a DLUN (DRAM logic unit). In this embodiment, referring to Figure 4 , a plurality of DLUNs are grouped into a DRAM target, and the control signals (such as CE signals) of all DLUNs inside the DRAM target are connected together. This means that when the host accesses this DRAM target, all DLUNs that make up the target will be activated at the same time.
[0073] ONFI CE Reduction mechanism: The connection between DLUNs still follows the CE Reduction mechanism of the ONFI protocol, that is, the Eni (External Network Interface) and Eno (External Node) signals of adjacent DLUNs are interconnected to form a daisy chain.
[0074] Unified addressing: Each DRAM target is assigned a unique address when powered on. The host accesses the DRAM target through this address. Since the control signals of multiple DLUNs inside a DRAM target are connected together and share the same address, the host can access them as if they were a single storage unit.
[0075] Unlike traditional architectures where each DLUN corresponds to one or more DRAM targets, the architecture provided in this implementation combines multiple DLUNs into a single logical DRAM target. The advantages of this approach are:
[0076] Simplified control: Since the DLUNs within a DRAM target share the same control signal, in this embodiment, the host only needs to control one CE signal and one address to access all DLUNs within the target, thus simplifying the control logic.
[0077] Increased bandwidth: Since multiple DLUNs can be accessed simultaneously, this architecture may increase the bandwidth of the storage system.
[0078] Logical uniformity: Combining multiple DLUNs into a single DRAM target can make the storage system more logically unified, facilitating management and use.
[0079] In addition, multiple DLUNs can be connected together through the CE Reduction mechanism of the ONFI protocol without adding any pins; therefore, with the same pins, taking the main control circuit 200 as the host / SoC chip as an example, the main control circuit 200 can expand the DRAM storage capacity.
[0080] Optionally, this embodiment provides an end-side device, such as... Figure 5 As shown, it includes a main control circuit 200 and at least one DRAM target 300. When there is more than one DRAM target 300, each DRAM target 300 will be assigned an address. Multiple DRAM targets 300 can share a signal of one channel of the host. Different DRAM targets 300 are distinguished by different CE signals. The main control circuit 200 can be configured with multiple channels, and the DRAM storage size required by the topology can be determined according to actual needs.
[0081] The technical effect of this setting is:
[0082] Expanding DRAM storage capacity: Through the CE Reduction mechanism, multiple DLUNs can be connected together without adding extra pins. This allows the main control circuitry (host / SoC chip) to connect more DRAM memory chips with the same number of pins, thereby expanding the DRAM storage capacity.
[0083] Shared channel signals: Multiple DRAM Targets can share one channel signal of the host, and different DRAM Targets are distinguished by different CE signals. This way can effectively utilize channel resources and improve data transmission efficiency.
[0084] Flexible topology: The host control circuit can be provided with multiple channels, and the required DRAM storage size can be flexibly topological according to actual needs. This scheme can flexibly configure the DRAM storage capacity according to different application scenarios to meet different needs.
[0085] The technical scheme connects multiple DLUNs through the CE Reduction mechanism of the ONFI protocol, realizes the purpose of expanding the DRAM storage capacity under the same number of pins, and improves the utilization rate of storage resources and the flexibility of configuration. This scheme can effectively solve the problems of limited SOC chip area and increased power consumption, and meet the needs of different application scenarios for DRAM storage capacity.
[0086] Optionally, the embodiment also provides an end-side device, such as Figure 6 As shown, it includes a host control circuit 200, an external storage control chip 400, and a memory including a DRAM memory 100 and a FLASH memory 500, wherein the DRAM memory 100 and the FLASH memory 500 are connected to the external storage control chip 400 through the ONFI protocol, and the SoC chip is taken as an example of the host control circuit 200, and the SoC chip and the external storage control chip are connected through the UFS protocol, the SD protocol or the emmc protocol, etc.
[0087] The technical effect of such a setting is:
[0088] Unified storage interface: Through the ONFI protocol, the DRAM memory and the FLASH memory are connected to the external storage control chip. This makes the host control circuit (SoC chip) only need to communicate with the external storage control chip, without the need to directly manage different types of memory interfaces, thereby simplifying the design of the host control circuit and reducing its area overhead and power consumption.
[0089] Flexible storage configuration: Since the external storage control chip uniformly manages the DRAM memory and the FLASH memory, different types and capacities of memories can be flexibly configured according to actual needs to meet different application scenarios.
[0090] Efficient data access: The external storage control chip can optimize the transmission and management of data between the DRAM memory and the FLASH memory, improving the data access efficiency.
[0091] Extensibility: the scheme is easy to extend, and the number and type of memories can be increased as needed to meet the needs of future applications.
[0092] Thus far, the technical solutions of the present application have been described in conjunction with the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present application is obviously not limited to the above specific embodiments. Those skilled in the art can make equivalent changes or replacements to the relevant technical features without deviating from the principles of the present application, and the technical solutions after such changes or replacements will all fall within the scope of protection of the present application.
Claims
1. A DRAM memory, characterized by, Comprising: a plurality of memory blocks for storing data; a plurality of memory block controllers corresponding to the plurality of memory blocks, each memory block controller capable of controlling writing or reading data to or from the corresponding memory block; an ONFI interface controller connected to the plurality of memory block controllers, capable of sending instructions to the plurality of memory block controllers to control the operation of the plurality of memory blocks; and an IO interface connected to the ONFI interface controller and configured to be connected to a host control circuit, receiving control signals from the host control circuit and sending them to the ONFI interface controller.
2. The DRAM memory of claim 1, wherein, The ONFI interface controller is configured to refresh the plurality of memory blocks using its refresh instructions.
3. The DRAM memory of claim 1 or 2, wherein: The plurality of memory blocks and the plurality of memory block controllers are integrated into at least one DRAM memory chip, and the IO interface and the ONFI interface controller are integrated into a control chip.
4. The DRAM memory of claim 3, wherein, The at least one DRAM memory chip and the control chip are connected by a three-dimensional packaging process.
5. An end-side device characterized by comprising: The DRAM memory of any one of claims 1-4 is applied to a system comprising: a host control circuit; and at least one DRAM target connected to the host control circuit and capable of operating based on instructions from the host control circuit; wherein each DRAM target comprises a plurality of the DRAM memory capable of synchronously receiving control signals.
6. The end-side device according to claim 5, characterized by The plurality of DRAM memory included in each DRAM target share the same address.
7. The end-side device according to claim 5, characterized by The external network interfaces and external node interconnections of adjacent DRAM memory form a daisy chain.
8. The end-side device according to claim 6, characterized by The host control circuit controls the corresponding DRAM target based on the CEReduction mechanism and address access of the ONFI protocol.
9. The end-side device according to any one of claims 5 to 8, characterized by, Further comprising a FLASH memory and an external storage control chip, the DRAM memory and the FLASH memory are connected to the external storage control chip based on the ONFI protocol, and the external storage control chip is connected to the host control circuit.
10. The end-side device according to claim 9, characterized by The host control circuit is a SoC chip, and the external storage control chip is connected to the SoC chip in UFS protocol, SD protocol, or emmc protocol.