Kick-back elimination circuit, amplifier and chip

Abstract

The utility model discloses a kickback elimination circuit, an amplifier and a chip, the kickback elimination circuit is connected with a first differential input end of a differential pair structure, a second differential input end of the differential pair structure is used for receiving a first input signal, and the first differential input end of the differential pair structure is connected with an external circuit to receive a second input signal; the kickback elimination circuit comprises a slope generation unit and a coupling compensation unit, the slope generation unit is used for performing reverse amplification on a first input signal based on a reference voltage to generate a compensation signal, and the coupling compensation unit is used for coupling the compensation signal to a first differential input end of the differential pair structure. According to the kickback elimination circuit, the amplifier and the chip, the problem of overshoot caused by kickback of the first differential input end when the first input signal enters a rising slew state can be solved through the kickback elimination circuit, and all noise signals kicked back to the first differential input end through a parasitic capacitor of a differential pair structure can be counteracted; therefore, the malformation of the output response is corrected.

Description

TECHNICAL FIELD

[0001] The utility model belongs to integrated circuit technical field, concretely relates to a kind of kickback elimination circuit, amplifier and chip. BACKGROUND

[0002] The input of operational amplifier often encounters kickback problem, which eventually leads to glitch in output. The scene of heavy kickback, for example, two operational amplifiers simultaneously tap on a set of resistance string (reference Figure 1 ), if the resistance string is made under high voltage, in order to ensure power consumption, it will be designed very high resistance string resistance value, which will lead to kickback, thereby causing cross-talk between operational amplifiers.

[0003] The information disclosed in this section is intended only to increase an understanding of the general background of the present utility model and should not be construed as recognizing or implying that this information constitutes prior art with respect to the present utility model. SUMMARY

[0004] The utility model aims at providing a kind of kickback elimination circuit, amplifier and chip, which can solve the overshoot of operational amplifier output and the interference between operational amplifiers.

[0005] In order to achieve the above-mentioned purpose, the technical scheme provided by the utility model in one embodiment is as follows: a kickback elimination circuit is connected with the first differential input end of a differential pair structure, the second differential input end of the differential pair structure is used to receive a first input signal, and the first differential input end of the differential pair structure is also used to be connected with an external circuit to receive a second input signal; the kickback elimination circuit comprises a slope generation unit and a coupling compensation unit.

[0006] The slope generation unit is used to inversely amplify the first input signal based on a reference voltage to generate a compensation signal, the coupling compensation unit is connected with the output end of the slope generation unit and the first differential input end of the differential pair structure, and the coupling compensation unit is used to couple the compensation signal to the first differential input end of the differential pair structure.

[0007] In one or more embodiments of the utility model, the slope generation unit comprises a first operational amplifier and a feedback unit, the non-inverting input end of the first operational amplifier is used to receive a reference voltage, and the feedback unit is connected between the inverting input end of the first operational amplifier and the output end of the first operational amplifier.

[0008] In one or more embodiments of the utility model, the feedback unit includes first resistance and second resistance, the first end of first resistance is used for receiving first input signal, the second end of first resistance is connected with the first end of second resistance and the inverting input terminal of first operational amplifier, the second end of second resistance is connected with the output terminal of first operational amplifier.

[0009] In one or more embodiments of the utility model, the coupling compensation unit includes coupling capacitor, the first end of coupling capacitor is connected with the output terminal of slope generation unit, and the second end of coupling capacitor is connected with the first differential input terminal of differential pair structure.

[0010] In one or more embodiments of the utility model, the coupling compensation unit further includes coupling resistance, and the coupling capacitor and the coupling resistance are connected in series between the output terminal of slope generation unit and the first differential input terminal of differential pair structure.

[0011] In one or more embodiments of the utility model, the kickback elimination circuit further includes buffer unit, the input terminal of buffer unit is used for receiving first input signal, and the output terminal of buffer unit is connected with the input terminal of slope generation unit.

[0012] In one or more embodiments of the utility model, the buffer unit includes second operational amplifier, the noninverting input terminal of second operational amplifier is used for receiving first input signal, and the inverting input terminal of second operational amplifier is connected with the output terminal of second operational amplifier and the input terminal of slope generation unit.

[0013] In one or more embodiments of the utility model, the external circuit includes voltage division unit, and the voltage division end of voltage division unit is connected with the first differential input terminal of differential pair structure.

[0014] The utility model discloses still one kind of amplifier, including differential pair structure and the first differential input terminal of differential pair structure with the kickback elimination circuit described.

[0015] The utility model discloses still a kind of chip, including the amplifier described and / or the kickback elimination circuit described.

[0016] Compared with prior art, the kickback elimination circuit, amplifier and chip of the utility model, through kickback elimination circuit, can solve the overshoot caused by the kickback to the first differential input terminal when the first input signal enters slew (transition) state, can offset all noise signals that are kicked back to the first differential input terminal through the parasitic capacitor of differential pair structure, so as to correct the deformity of output response. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0018] Figure 1 The circuit schematic diagram containing the kickback elimination circuit, the differential pair structure and the external circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the person skilled in the art better understand the technical solutions in the present application, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the present application.

[0020] In the specification, "coupling" or "connection" or "connection" includes both direct connection and indirect connection. Indirect connection is the connection through an intermediate medium, such as the connection through an electrically conductive medium, which can have parasitic inductance or parasitic capacitance; indirect connection can also include the connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as the connection through circuits or components such as switches, follower circuits, etc. In addition, in the present application, words such as "first", "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply a certain actual relationship, quantity or order between the technical features.

[0021] In the detailed description of the specification, the drawings forming a part thereof are referred to, wherein the same reference signs always represent the same components, and wherein the exemplary embodiments can be shown by way of example. It should be understood that other embodiments can be utilized without departing from the scope of the present application, and structural or logical changes can be made. Therefore, the following detailed description should not be regarded as limiting.

[0022] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0023] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0024] Various components and devices may be referred to or shown in the singular (e.g., “MOS transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0025] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.

[0026] like Figure 1 As shown, in one embodiment of this utility model, a kickback cancellation circuit is connected to the first differential input terminal D1 of a differential pair structure. The second differential input terminal D2 of the differential pair structure is used to receive the first input signal Vin. The first differential input terminal D1 of the differential pair structure is also used to connect to an external circuit to receive the second input signal Vip.

[0027] The differential pair structure can be composed of a first transistor M1 and a second transistor M2. The first transistor M1 and the second transistor M2 can be P-channel MOS transistors. The control terminal (gate) of the first transistor M1 forms the first differential input terminal D1, and the control terminal (gate) of the second transistor M2 forms the second differential input terminal D2. The first terminal (source) of the first transistor M1 and the first terminal (source) of the second transistor M2 are connected to the current source A1, and the second terminal (drain) of the first transistor M1 and the second terminal (drain) of the second transistor M2 are connected to the subsequent circuit. Figure 1 The two Cgs in the figure are the parasitic capacitance between the control terminal and the first terminal of the first transistor M1, and the parasitic capacitance between the control terminal and the first terminal of the second transistor M2, respectively. In other embodiments, the first transistor M1 and the second transistor M2 can be N-channel MOS transistors.

[0028] The external circuit with the differential pair structure can be considered as an application scenario of the kickback elimination circuit. In an embodiment, the external circuit includes a voltage dividing unit and one or more operational amplifiers. The voltage dividing unit is connected to the first differential input terminal D1 of the differential pair structure. The voltage dividing unit is formed by three voltage dividing resistors Rf1, Rf2 and Rf3 connected in series. The connection nodes of the two voltage dividing resistors connected in series form voltage dividing terminals. One voltage dividing terminal is connected to the first differential input terminal D1, and the other voltage dividing terminals can be connected to other corresponding operational amplifiers OPAn. In other embodiments, the number of voltage dividing resistors can be increased or decreased as needed, and the external circuit can be a circuit of other structures.

[0029] As shown in FIG. 1, the kickback elimination circuit includes a buffer unit 10, a slope generation unit 20 and a coupling compensation unit 30. Figure 1

[0030] The input terminal of the buffer unit 10 is used to receive a first input signal Vin. The output terminal of the buffer unit 10 is connected to the input terminal of the slope generation unit 20. The buffer unit 10 is used to improve the driving capability of the first input signal Vin. If the driving capability of the first input signal Vin is strong enough, the buffer unit 10 can not be set.

[0031] The slope generation unit 20 is used to inversely amplify the signal output by the buffer unit 10 based on a reference voltage Vb to generate a compensation signal.

[0032] The coupling compensation unit 30 is connected to the output terminal of the slope generation unit 20 and the first differential input terminal D1 of the differential pair structure. The coupling compensation unit 30 is used to couple the compensation signal to the first differential input terminal D1 of the differential pair structure.

[0033] As shown in FIG. 1, the buffer unit 10 includes a second operational amplifier OPA2. The non-inverting input terminal of the second operational amplifier OPA2 is used to receive the first input signal Vin. The inverting input terminal of the second operational amplifier OPA2 is connected to the output terminal of the second operational amplifier OPA2 and the input terminal of the slope generation unit 20. Figure 1

[0034] The slope generation unit 20 includes a first operational amplifier OPA1 and a feedback unit. The non-inverting input terminal of the first operational amplifier OPA1 is used to receive the reference voltage Vb. The feedback unit is connected between the inverting input terminal of the first operational amplifier OPA1 and the output terminal of the first operational amplifier OPA1.

[0035] ​​The feedback unit comprises a first resistor R1 and a second resistor R2, a first end of the first resistor R1 is connected with an output end of the second operational amplifier OPA2, a second end of the first resistor R1 is connected with a first end of the second resistor R2 and an inverting input end of the first operational amplifier OPA1, and a second end of the second resistor R2 is connected with an output end of the first operational amplifier OPA1.

[0036] The coupling compensation unit 30 comprises a coupling capacitor CM and a coupling resistor RM, which are connected in series between the output end (the output end of the first operational amplifier OPA1) of the slope generation unit 20 and the first differential input end D1 of the differential pair structure.

[0037] The utility model discloses still disclose a kind of amplifiers, including above-mentioned differential pair structure and the first differential input end D1 of above-mentioned differential pair structure is connected with above-mentioned kickback elimination circuit.

[0038] The utility model discloses still disclose a kind of chip, including above-mentioned amplifier and / or above-mentioned kickback elimination circuit and / or external circuit.

[0039] As shown in Figure 1 When the first input signal Vin enters the rising slew state (the rising transition with the slope k), the common mode point also enters the slew state with the slope k, at this time, the signal is kicked back to the second input signal Vip through the parasitic capacitor Cgs of the first transistor M1, causing the second input signal Vip to be lifted, because the slope of the common mode point is fixed, the second input signal Vip is lifted by a fixed voltage deviation. Therefore, the establishment end point of the loop is lifted when the first input signal Vin changes, when the circuit approaches the wrong establishment final potential, the second input signal Vip starts to recover to the correct potential, then the first input signal Vin also recovers to the correct potential, finally, the glitch (glitch) of overshoot is generated; similar glitch (glitch) of undershoot is also generated when the signal falls. At the same time, the kickback generated by the path of the parasitic capacitor Cgs of the first transistor M1 and the second transistor M2 also affects other operational amplifiers OPAn connected with the same resistor string, thereby generating the cross-talk (cross-talk) problem.

[0040] When the first input signal Vin enters the rising slew state (the rising transition with the slope k), the signal with the inverse slope (-k*r2 / r1) of the first input signal Vin is generated by the slope generation unit 20 and added to the coupling capacitor CM, r2 is the resistance value of the second resistor R2, r1 is the resistance value of the first resistor R1, then the signal is injected into the first differential input end D1 through the coupling resistor RM, thereby the common mode point is added to the parasitic capacitor Cgs to offset the influence on the second input signal VIP at the first differential input end D1.

[0041] The kickback cancellation circuit directly detects the first input signal Vin (i.e., the source of the kickback) from the very beginning, so there will be no false triggering.

[0042] The coupling capacitor CM can be a MOS capacitor that matches the first transistor M1. If the potential on both sides of the coupling capacitor CM is uncertain, other types of capacitors can also be used, as long as the coupling capacitor CM is slightly larger than the parasitic capacitance Cgs. Since the entire circuit is a negative feedback control, injecting more charge into the coupling capacitor CM will cause the second input signal Vip to be established below the final value. Although this will increase the system setup time, it can still perfectly eliminate overshoot glitch.

[0043] The first operational amplifier OPA1 has very low requirements for noise, offset, and gain, and its output is a large ramp signal with minimal impact from errors. The ramp gain can be adjusted by changing the reference voltage Vb and the first resistor R1 and the second resistor R2 according to the output swing limit of the ramp generation unit 20, thereby reducing the value of the coupling capacitor CM and thus reducing the implementation cost of the circuit.

[0044] There is only an AC path between the ramp generation unit 20 and the main loop. By adding a coupling resistor RM, the influence of the first operational amplifier OPA1 of the ramp generation unit 20 on the frequency characteristics of the main loop can be completely isolated.

[0045] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0046] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A kickback cancellation circuit, characterized by, The first differential input of the differential pair structure is connected to an external circuit to receive a first input signal, and the second differential input of the differential pair structure is used to receive a second input signal. The kickback cancellation circuit comprises a slope generating unit and a coupling compensation unit. The slope generating unit is configured to inversely amplify the first input signal based on a reference voltage to generate a compensation signal, and the coupling compensation unit is connected to an output terminal of the slope generating unit and the first differential input of the differential pair structure, and is configured to couple the compensation signal to the first differential input of the differential pair structure.

2. The kickback cancellation circuit of claim 1, wherein, The slope generating unit comprises a first operational amplifier and a feedback unit, and the non-inverting input terminal of the first operational amplifier is configured to receive the reference voltage.

3. The kickback cancellation circuit of claim 2, wherein, The feedback unit comprises a first resistor and a second resistor, the first end of the first resistor is configured to receive the first input signal, the second end of the first resistor is connected to the first end of the second resistor and the inverting input terminal of the first operational amplifier, and the second end of the second resistor is connected to the output terminal of the first operational amplifier.

4. The kickback cancellation circuit of claim 1, wherein, The coupling compensation unit comprises a coupling capacitor, the first end of the coupling capacitor is connected to the output terminal of the slope generating unit, and the second end of the coupling capacitor is connected to the first differential input of the differential pair structure.

5. The kickback cancellation circuit of claim 4, wherein, The coupling compensation unit further comprises a coupling resistor, and the coupling capacitor and the coupling resistor are connected in series between the output terminal of the slope generating unit and the first differential input of the differential pair structure.

6. The kickback cancellation circuit of claim 1, wherein, The kickback cancellation circuit further comprises a buffer unit, the input terminal of the buffer unit is configured to receive the first input signal, and the output terminal of the buffer unit is connected to the input terminal of the slope generating unit.

7. The kickback cancellation circuit of claim 6, wherein, The buffer unit comprises a second operational amplifier, the non-inverting input terminal of the second operational amplifier is configured to receive the first input signal, and the inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier and the input terminal of the slope generating unit.

8. The kickback cancellation circuit of claim 1, wherein, The external circuit comprises a voltage dividing unit, and the voltage dividing end of the voltage dividing unit is connected to the first differential input of the differential pair structure.

9. An amplifier characterized by, The kickback cancellation circuit comprises a differential pair structure and a kickback cancellation circuit as claimed in any one of claims 1 to 7 connected to the first differential input of the differential pair structure.

10. A chip, characterized by The amplifier as claimed in claim 9 and / or the kickback cancellation circuit as claimed in any one of claims 1 to 8.

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