Module for reducing jitter of SDI output signal

Abstract

The utility model provides a module for reducing the jitter of an SDI output signal, which has lower requirements on a clock distribution chip and lower cost. The device comprises a video processing output module, a clock distribution chip, a clock generation module and an SDI sending module. A video signal output interface of the video processing output module is connected with a video signal receiving interface of the SDI sending module, and a clock signal output interface of the video processing output module is connected with a clock signal input interface of the SDI sending module; the device is characterized in that the output end of the clock generation module is respectively connected with the input end of the clock distribution chip and the input end of the SDI sending module; and the output end of the clock distribution chip is connected with the input end of the video processing output module.

Description

TECHNICAL FIELD

[0001] The utility model relates to a module that reduces SDI output signal jitter. BACKGROUND

[0002] SDI interface is a kind of serial digital video transmission interface, and SDI interface is divided into: SDI, HD-SDI, 3G-SDI, and HD-SDI interface is a kind of broadcast level high-definition digital input and output port, wherein HD indicates high-definition signal.SDI interface cannot directly transmit compressed digital signal, and after compressed signal recorded by digital video recorder, hard disk and other equipment is played back, must be decompressed and output by SDI interface to enter SDI system.If repeatedly decompressing and compressing, it will cause image quality to drop and delay to increase, so that various digital video recorders of different formats and the interface for directly transmitting compressed digital signal of their own are stipulated.

[0003] In the field of radio station, educational recording and broadcasting, video conference, HD-SDI and 3G-SDI are widely used, which is transmitted according to SMPTE292M and SMPTE424M at the signal rate of 1.485Gb / s or 1.485 / 1.001Gb / s, 2.97Gb / s or 2.97 / 1.001Gb / s.The specification specifies data format, channel coding mode, coaxial cable interface signal specification, connector and cable type and optical fiber interface, etc.SDI interface adopts coaxial cable as cable standard, and effective distance is 100M.

[0004] The traditional SDI sending module is greatly affected by the clock signal quality output by the video processing output module, when the clock signal quality output by the video processing output module is poor and the jitter is large, the signal jitter of SDI output is serious, which cannot meet the requirements of SDI specification, so that the transmission distance is short and the compatibility is poor in the system.

[0005] To solve the above technical problems, the applicant applied for a Chinese patent with patent number 202220904894.7, which provides a circuit for reducing SDI output signal jitter, and the SDI output signal jitter is low, which meets the requirements of SDI specification.The utility model discloses a video processing output circuit, SDI sending circuit, clock distribution chip, clock generating circuit, first matching resistance, second matching resistance and third matching resistance;Video processing output circuit is connected with SDI sending circuit;The output end of clock generating circuit is connected with the input end of clock distribution chip through first matching resistance;The output end of clock distribution chip is connected with the input end of SDI sending circuit through second matching resistance, and is connected with the input end of video processing output circuit through third matching resistance.

[0006] The clock distribution chip needs two outputs, one for the video processing output module and the other for the SDI sending module, the clock distribution chip with two outputs has requirements on the model and is relatively high in cost. Practical new type content

[0007] The module for reducing SDI output signal jitter has the advantages that the basic clock generated by the clock generation module is directly sent to the SDI sending module without passing through the clock distribution chip, so that the clock distribution chip only needs one output, the requirement on the clock distribution chip is lower, the cost is lower, and the applicability is stronger.

[0008] The technical scheme adopted by the utility model to solve above-mentioned problem is: a module for reducing SDI output signal jitter, including video processing output module, clock distribution chip, clock generation module and SDI sending module, the video signal output interface of video processing output module is connected with the video signal receiving interface of SDI sending module, the clock signal output interface of video processing output module is connected with the clock signal input interface of SDI sending module, its characterized in that: the output of clock generation module is connected with the input of clock distribution chip and the input of SDI sending module respectively, the output of clock distribution chip is connected with the input of video processing output module.

[0009] The utility model also includes first matching resistance, and the output of clock generation module is connected with the input of clock distribution chip through first matching resistance.

[0010] The utility model also includes second matching resistance, and the output of clock generation module is connected with the input of SDI sending module through second matching resistance.

[0011] The utility model also includes third matching resistance, and the output of clock distribution chip is connected with the input of video processing output module through third matching resistance.

[0012] The utility model also includes fourth matching resistance, and the clock signal output interface of video processing output module is connected with the clock signal input interface of SDI sending module through fourth matching resistance.

[0013] The configuration interface of clock distribution chip is connected with the configuration interface of video processing output module.

[0014] Compared with the prior art, the utility model has the following advantages and effects: the basic clock generated by the clock generation module is directly sent to the SDI sending module without passing through the clock distribution chip, so that the clock distribution chip only needs one output, the requirement on the clock distribution chip is lower, the cost is lower, and the applicability is stronger. DRAWINGS

[0015] Figure 1 It is the schematic diagram of the utility model embodiment. DETAILED DESCRIPTION

[0016] The utility model will be further explained in detail below in combination with the drawings and by examples, and the following examples are the explanation of the utility model, and the utility model is not limited to the following examples.

[0017] The embodiment of the utility model includes video processing output module A, clock distribution chip B, clock generation module C and SDI sending module D.

[0018] Video processing output module A is used for outputting the video signal and clock signal collected by the camera, the video signal output interface of video processing output module A is connected with the video signal receiving interface of SDI sending module D, SDI sending module D receives the video signal and clock signal output from video processing output module A, and outputs the SDI signal meeting the SDI standard. Wherein, the clock signal output interface of video processing output module A is connected with the clock signal input interface of SDI sending module D through the fourth matching resistance R4, and the clock signal generated by video processing output module A is sent to SDI sending module D, and the fourth matching resistance R4 is used to reduce the reflection of the clock signal output by video processing output module A, to meet the signal integrity requirement.

[0019] The output end of clock generation module C is connected with the input end of clock distribution chip B through the first matching resistance R1, and the basic clock generated by clock generation module C is sent to clock distribution chip B, and the first matching resistance R1 is used to reduce the reflection of the clock signal output by clock generation module C, to meet the signal integrity requirement. The clock oscillator is arranged in clock generation module C.

[0020] The output end of clock generation module C is connected with the input end of SDI sending module D through the second matching resistance R2, and the basic clock generated by clock generation module C is directly sent to SDI sending module D without passing through clock distribution chip B, so that clock distribution chip B only needs 1-way output, and the requirement for clock distribution chip B is lower, and the cost is lower. The second matching resistance R2 is used to reduce the reflection of the clock signal output by clock generation module C, to meet the signal integrity requirement.

[0021] The output end of clock distribution chip B is connected with the input end of video processing output module A through the third matching resistance R3, and the clock signal generated by clock distribution chip B is sent to video processing output module A, and the third matching resistance R3 is used to reduce the reflection of the clock signal output by clock distribution chip B, to meet the signal integrity requirement. The configuration interface of clock distribution chip B is connected with the configuration interface of video processing output module A, and video processing output module A can configure the different reference time output by clock distribution chip B, to meet different requirements.

[0022] Furthermore, it needs to explain, the specific embodiment described in this specification, the shape of zero, component, the name taken etc. can be different, the above contents described in this specification are only the example of the structure of the utility model. The equivalent change or simple change made according to the structure, features and principles described in the utility model patent concept are included in the protection scope of the utility model patent. The skilled in the art to which the utility model belongs can make various modifications or supplements or adopt similar ways to replace the specific embodiments described, as long as not deviating from the structure of the utility model or beyond the range defined in the claims, should belong to the protection scope of the utility model.

Claims

1. A module for reducing jitter of an SDI output signal, comprising a video processing output module, a clock distribution chip, a clock generation module and an SDI sending module; a video signal output interface of the video processing output module is connected with a video signal receiving interface of the SDI sending module, and a clock signal output interface of the video processing output module is connected with a clock signal input interface of the SDI sending module; characterized in that: The output end of the clock generation module is connected with the input end of the clock distribution chip and the input end of the SDI sending module respectively; the output end of the clock distribution chip is connected with the input end of the video processing output module. ​ 2. The module for reducing jitter of an SDI output signal of claim 1, wherein: The output end of the clock generation module is connected with the input end of the clock distribution chip through the first matching resistor.

3. The module for reducing jitter of an SDI output signal of claim 1, wherein: The output end of the clock generation module is connected with the input end of the SDI sending module through the second matching resistor.

4. The module for reducing jitter of an SDI output signal of claim 1, wherein: The output end of the clock distribution chip is connected with the input end of the video processing output module through the third matching resistor.

5. The module for reducing jitter in an SDI output signal of claim 1, wherein: The clock signal output interface of the video processing output module is connected with the clock signal input interface of the SDI sending module through the fourth matching resistor.

6. The module for reducing jitter of an SDI output signal of claim 1, wherein: The configuration interface of the clock distribution chip is connected with the configuration interface of the video processing output module.

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