Power supply automatic detection circuit for radio frequency switch
By employing a voltage sampling circuit composed of PMOS transistors, NMOS transistors, and resistors in the RF switch chip, combined with two-stage inverters, automatic detection under different supply voltages is achieved. This solves the high and low voltage compatibility problem of the RF switch chip, improves system compatibility and performance, and reduces power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2026-03-03
AI Technical Summary
Existing RF switch chips struggle to maintain compatibility with both high and low supply voltages without sacrificing performance when faced with differences in system supply voltages, leading to decreased system compatibility and chip performance.
The circuit design adopts direct power supply voltage, and uses a voltage sampling circuit composed of PMOS transistors, NMOS transistors and resistors, combined with two-stage inverters to realize automatic detection of power supply voltage. The output logic signal changes with the power supply voltage and is compatible with 1.2V/1.8V system operating voltage.
It improves system compatibility and chip performance, reduces layout area and power consumption, and enables low-cost dynamic power detection.
Smart Images
Figure CN223966634U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of power supply automatic detection circuit technology, and in particular relates to a power supply automatic detection circuit for radio frequency switches. Background Technology
[0002] In the field of radio frequency front-end, radio frequency switches are an important and widely used device; as chip integration becomes higher and higher and performance becomes stronger, the demand for reducing power consumption becomes more and more urgent.
[0003] Considering the specific application environment of the chip, different system applications may have different system supply voltages. On the one hand, some systems may use chips with smaller wafer fabrication process linewidths, such as 28nm or smaller, to improve performance, and the system will use a lower voltage, such as 1.2V, for power supply. Other system applications may use a higher supply voltage, such as 1.8V. Therefore, in order to improve the chip's system compatibility without sacrificing performance, the chip needs to be able to operate under both high and low supply voltages. To address this technical problem, the automatic voltage checking circuit of the RF switch in this technical solution provides a new technical solution. Utility Model Content
[0004] This invention provides an automatic power supply detection circuit for radio frequency switches. This solution proposes an efficient solution for automatically detecting power supply voltage, which is compatible with 1.2V / 1.8V system operating voltages. It has high practical value in terms of improving the system compatibility of the product and enhancing chip performance, thereby solving the problems in the background technology.
[0005] To solve the above-mentioned technical problems, this utility model is achieved through the following technical solution:
[0006] This utility model discloses an automatic power supply detection circuit for an RF switch. The detection circuit is directly powered by the power supply voltage and includes two inverters, a PMOS transistor, a resistor, a first NMOS transistor, and a second NMOS transistor.
[0007] The source terminal of the PMOS transistor is connected to the power supply voltage. The gate terminal and drain terminal of the PMOS transistor are connected together, and the drain terminal of the PMOS transistor is synchronously connected to one end of a resistor. The other end of the resistor is connected to the drain terminal of the first NMOS transistor, which synchronously connects the gate terminal and drain terminal of the first NMOS transistor together. The source terminal of the first NMOS transistor is connected to the drain terminal of the second NMOS transistor. The gate terminal of the second NMOS transistor serves as the input terminal of the enable signal, and the source terminal of the second NMOS transistor is grounded.
[0008] The two-stage inverter includes a first inverter and a second inverter connected in series, with the first inverter connected to the drain terminal of the PMOS transistor.
[0009] Furthermore, the power supply voltage is 1.2V or 1.8V.
[0010] Furthermore, when the power supply voltage is 1.8V, the output logic is high; when the power supply voltage is 1.2V, the output logic is low.
[0011] Furthermore, after the voltage is sampled by the sampling circuit consisting of a PMOS transistor, a resistor, a first NMOS transistor, and a second NMOS transistor, the voltage taken out at the drain terminal of the PMOS transistor is used as the sampling voltage. The sampling voltage is then shaped and output after being buffered by two stages of inverters.
[0012] Furthermore, the voltage is divided by connecting a PMOS transistor connected by a diode, a resistor, and a first NMOS transistor and a second NMOS transistor connected by a diode in series.
[0013] The present invention has the following advantages over the prior art:
[0014] (1) This solution proposes an efficient solution for automatically detecting power supply voltage for systems compatible with 1.2V / 1.8V operating voltages. It has high practical value in terms of improving the system compatibility of the product and enhancing chip performance.
[0015] (2) The layout area of this solution is greatly reduced compared to traditional power supply circuit detection, and the power supply detection circuit has a smaller power, usually less than 1uA, and the size is 1 / 15-1 / 20 of that of traditional power supply detection circuit.
[0016] (2) This scheme uses the power supply VDD to directly power the circuit and uses PMOS, NMOS and resistors to form a voltage sampling circuit; the output signal changes with the power supply voltage VDD and has dynamic detection characteristics.
[0017] (3) In this scheme, the drain terminal of the PMOS transistor is brought out as the sampling voltage, which is used as the initial sampling voltage to achieve voltage sampling. The sampling voltage is achieved by dividing the power supply voltage through a PMOS transistor connected in series with a diode, a resistor, and an NMOS transistor connected in series with a diode.
[0018] (4) The power supply detection circuit of this solution determines the two power supply voltages of 1.2V and 1.8V through the logic output signal. When the power supply voltage is 1.8V, the logic output signal is high, and when the power supply voltage is 1.2V, the logic output signal is low, thus realizing the function of the power supply detection circuit. Through circuit simulation, the detection circuit of this technical solution can effectively detect the power supply voltage and output the logic signal to complete the power supply detection output function.
[0019] Of course, any product implementing this utility model does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description
[0020] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a schematic diagram of a traditional power supply detection circuit.
[0022] Figure 2 This is a schematic diagram of an automatic power detection circuit for a radio frequency switch according to the present invention.
[0023] Figure 3 This is a power supply detection simulation curve of a specific embodiment of the present invention;
[0024] The attached diagram lists the components represented by each number as follows:
[0025] VDD - Power supply voltage, P - PMOS transistor, R - Resistor, N1 - First NMOS transistor, N2 - Second NMOS transistor, EN - Enable signal, Vs - Sampling voltage, INV1 - First inverter, INV2 - Second inverter, Vout - Output voltage, VCP - Output voltage of first-stage inverter, VCN - Output voltage of second-stage inverter, R1 - First resistor, R2 - Second resistor, C - Capacitor. Detailed Implementation
[0026] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.
[0027] In the description of this utility model, it should be understood that the terms "source end", "drain end", "gate end", "series", etc., which indicate orientation or positional relationship, are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.
[0028] like Figure 1The diagram shows the schematic of a traditional power supply detection circuit, which includes a resistor voltage divider and voltage sampling. The voltage divider is used to make the sampled signal change with the power supply voltage. It also includes a logic output section for the sampled voltage. The sampled voltage is passed through two stages of inverters to output the logic voltage: the first stage inverter output voltage VCP and the second stage inverter output voltage VCN. The specific circuit includes two resistors connected in series, a first resistor R1 and a second resistor R2, and a capacitor C connected in parallel across the second resistor R2.
[0029] Traditional power supply detection circuits mostly use a series resistor voltage divider method for voltage sampling. This traditional method has two drawbacks: firstly, it requires large resistors to achieve low module static power consumption; secondly, large-value resistors require very large sizes, consuming valuable chip area. For example, the resistor voltage divider method in traditional power supply detection circuits typically uses relatively large resistors (MΩ level) to meet static power consumption requirements, resulting in a layout area that is 1500%-2000% larger than the power supply detection circuit in this technical solution.
[0030] Traditional power supply testing methods are not highly reliable. They use a series resistor voltage divider method for sampling, where the sampled voltage is related to the power supply voltage via a resistor-based voltage divider relationship. Therefore, the sampled voltage fluctuates linearly with power supply voltage fluctuations, which can easily lead to sampling errors and cause power supply test failures.
[0031] The power detection circuit described in this paper detects that the output signal changes with the power supply voltage VDD, exhibiting dynamic detection characteristics. This power detection circuit also features low power consumption and small size, offering low cost and low power consumption advantages. The power consumption of the power detection circuit described in this paper is typically less than 1uA, and its size is 1 / 15 to 1 / 20 of that of traditional power detection circuits. Through circuit simulation, the power detection circuit described in this paper can effectively detect the power supply voltage and output logic signals under different power supply voltages (1.2V and 1.8V), thus completing the power detection output function.
[0032] Specifically, the technical solution is as follows:
[0033] Please see Figure 2 As shown, this utility model discloses an automatic power supply detection circuit for an RF switch, comprising two parts: a power supply voltage divider and a voltage sampling section, wherein the sampling voltage Vs after voltage division varies with the power supply voltage depending on the operating voltage VDD; and a voltage shaping and output section, wherein the sampling voltage Vs is shaped and logic-outputted by INV1 and INV2 to convert the sampling voltage into a logic output voltage Vout; when the power supply voltage is 1.8V, the logic output signal Vout is high, and when the power supply voltage is 1.2V, the logic output signal Vout is low.
[0034] The detection circuit is directly powered by the power supply voltage VDD and includes two inverters, a PMOS transistor P, a resistor R, a first NMOS transistor N1, and a second NMOS transistor N2.
[0035] The source of PMOS transistor P is connected to the power supply voltage VDD. The gate and drain of PMOS transistor P are connected together, and the drain of PMOS transistor P is synchronously connected to one end of resistor R. The other end of resistor R is connected to the drain of the first NMOS transistor N1, and the gate and drain of the first NMOS transistor N1 are synchronously connected together. The source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2. The gate of the second NMOS transistor N2 serves as the input of the enable signal EN, and the source of the second NMOS transistor N2 is grounded.
[0036] The two-stage inverter consists of a first inverter INV1 and a second inverter INV2 connected in series. The first inverter INV1 is connected to the drain terminal of the PMOS transistor P, and the second inverter INV2 is connected to the output voltage Vout.
[0037] The power supply voltage VDD is 1.2V or 1.8V.
[0038] Specifically, when the power supply voltage VDD is 1.8V, the output logic is high; when the power supply voltage VDD is 1.2V, the output logic is low.
[0039] The voltage is sampled by a sampling circuit consisting of a PMOS transistor P, a resistor R, a first NMOS transistor N1, and a second NMOS transistor N2. The voltage taken out from the drain terminal of the PMOS transistor P is used as the sampling voltage Vs. The sampling voltage Vs is then shaped and output after being buffered by two stages of inverters.
[0040] The voltage is divided by connecting a PMOS transistor P connected by a diode, a resistor R, and two NMOS transistors N1 and N2 connected by diodes in series to divide the power supply voltage VDD.
[0041] In order to achieve automatic power supply detection, the following technical steps are adopted to realize the entire circuit device: (1) The power supply voltage is sampled by voltage division using diodes in series with resistors, and the sampled voltage changes with the power supply; (2) After obtaining the initial sampled voltage, it is shaped and output through an inverter buffer; (3) The sampled and shaped output voltage is processed by logic operation. When the power supply voltage is 1.8V, the output logic is high, and when the power supply voltage is 1.2V, the output logic is low.
[0042] Logic Determination: The power supply detection circuit in this paper determines the power supply voltage (1.2V and 1.8V) through a logic output signal. When the power supply voltage is 1.8V, the logic output signal is high; when the power supply voltage is 1.2V, the logic output signal is low, thus realizing the function of the power supply detection circuit.
[0043] like Figure 3 The figure shows the simulation curves of the power supply detection circuit. The figure compares and simulates the output signal waveforms of the power supply detection circuit when the power supply voltage VDD is 1.8V and 1.2V respectively. Figure 3 When the power supply voltage VDD is 1.8V, the logic output signal Vout is 1.8V, which is a high level; when the power supply voltage VDD is 1.2V, the logic output signal Vout is 0V, which is a low level.
[0044] The preferred embodiments of this utility model disclosed above are merely illustrative of the present utility model. These preferred embodiments do not exhaustively describe all details, nor do they limit the utility model to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. This utility model is limited only by the claims and their full scope and equivalents.
Claims
1. An automatic power supply detection circuit for radio frequency switches, characterized in that, The detection circuit is directly powered by the power supply voltage (VDD) and includes two inverters, a PMOS transistor (P), a resistor (R), a first NMOS transistor (N1), and a second NMOS transistor (N2): The source terminal of the PMOS transistor (P) is connected to the power supply voltage (VDD). The gate terminal and drain terminal of the PMOS transistor (P) are connected together, and the drain terminal of the PMOS transistor (P) is synchronously connected to one end of the resistor (R). The other end of the resistor (R) is connected to the drain terminal of the first NMOS transistor (N1), and the gate terminal and drain terminal of the first NMOS transistor (N1) are synchronously connected together. The source terminal of the first NMOS transistor (N1) is connected to the drain terminal of the second NMOS transistor (N2). The gate terminal of the second NMOS transistor (N2) serves as the input terminal of the enable signal (EN), and the source terminal of the second NMOS transistor (N2) is grounded. The two-stage inverter includes a first inverter (INV1) and a second inverter (INV2) connected in series. The first inverter (INV1) is connected to the drain terminal of the PMOS transistor (P).
2. The power automatic detection circuit for an RF switch according to claim 1, characterized in that, The power supply voltage (VDD) is 1.2V or 1.8V.