Gate drive circuit and chip
By designing the gate drive circuit of high and low current limiting and voltage regulating devices, the problem of balancing low static power consumption and large turn-on current in the existing technology is solved, improving the turn-on current and speed of the power transistor, while reducing circuit complexity and cost.
Patent Information
- Application Number
- CN202520631956.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-07
- Publication Date
- 2026-03-03
- Estimated Expiration
- 2035-04-07
AI Technical Summary
Existing technologies struggle to balance low quiescent power consumption and high turn-on current, and LDO buck converters are complex and costly.
The gate drive circuit design employs high and low current limiting and voltage regulation devices, which enables the power transistor to be turned on quickly with high current and maintain the circuit state with low current, and reduces static power consumption by combining a delayed turn-off unit.
This achieved a several-fold increase in the turn-on current and speed of the power transistor, reduced static power consumption, simplified the circuit structure, and lowered costs.
Smart Images
Figure CN223967847U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of electronic circuit technology, and in particular relates to a gate driving circuit and chip. Background Technology
[0002] MCU (or SoC) chips typically operate at 5V or lower supply voltages, and their PWM pin drive capability is generally no more than 30mA. In contrast, MOSFETs and other power transistors typically operate at higher voltages. Due to their larger gate capacitance, their turn-on or turn-off generally requires hundreds of mA or even several amperes of drive current; the higher the current, the faster the turn-on or turn-off. Therefore, a gate drive circuit or gate drive chip is needed between the MCU and the power transistor to achieve level matching and to improve current drive capability.
[0003] Commonly used MOSFET power transistors are of two types: N-channel and P-channel. For low to medium power applications with medium voltage, P / N complementary power transistors are typically used in pairs. In these applications, the system high voltage (VHV) is usually within tens of volts. The source of the N-type power transistor is connected to GND (0V), and the source of the P-type power transistor is connected to the VHV high voltage. Their drains are connected together for push-pull power output. Since the gate voltage (between the source and gate voltage) of a MOSFET is typically no more than 20V, when turning on and off an N-type power transistor, a gate voltage of 0V and no higher than 12V should be provided, respectively. Similarly, when turning off and on a P-type power transistor, a gate voltage of VHV and no lower than VHV-12V should be provided, respectively.
[0004] Taking the gate drive of an N-type power transistor as an example (the principle is the same for P-type transistors), in order to achieve a gate drive voltage no higher than 12V, existing P / N type MOS gate drive chips incorporate a simple LDO step-down converter to reduce and regulate the VHV voltage within 12V, ensuring that the high-level gate drive voltage of the N-type transistor does not exceed 12V. Figure 1 As shown, the stronger the load-carrying capacity of the buck converter, the larger the gate charging current of the N-type power transistor and the faster the turn-on. However, the buck converter itself also needs to have a larger static power consumption to ensure the response speed and load-carrying capacity. Moreover, increasing the load-carrying capacity will increase the chip area and cost. The turn-off current of the existing P / N gate driver chip can reach about 300mA, but considering the chip cost and static power consumption, the turn-on current is only about 40mA. The turn-on time of the power transistor is about 7 times the turn-off time, which is not conducive to outputting a square wave and increasing the switching frequency.
[0005] Therefore, existing technologies struggle to balance low quiescent power consumption and high turn-on current, and LDO buck converters are complex and costly. Utility Model Content
[0006] Purpose of the utility model: In order to solve the problems of insufficient turn-on current and excessive static power consumption in the existing gate drive circuit, this utility model provides a gate drive circuit and chip.
[0007] Technical solution: A gate driving circuit, comprising:
[0008] The first MOS is connected as a source follower, and the source outputs the gate drive signal;
[0009] The first driving unit has a control signal connected to its input terminal and a gate of the first MOS connected to its output terminal.
[0010] The current limiting unit includes a first current limiting branch and a second current limiting branch, which are connected in parallel. A first switch is provided on the first current limiting branch, and the first switch is controlled by a control signal. Let the current of the first current limiting branch be I1, and let the current of the second current limiting branch be I2, where I1≥10*I2.
[0011] A voltage regulator, connected in series with a current limiting unit, is used to provide an internal voltage VZ, which serves as the power supply for the first driving unit.
[0012] Furthermore, it also includes a time-delay shutdown circuit, which includes a time-delay circuit, an inverter, and a second switch. The input of the time-delay circuit is the control signal of the first switch, the output of the time-delay circuit is connected to the inverter, the output of the inverter is connected to the control terminal of the second switch, and the second switch is connected in series in the first current-limiting branch.
[0013] Furthermore, it also includes a time-delay shutdown circuit, which is inserted into the control terminal of the first switch and is used to shut down the first switch after the first switch has been turned on for a period of time.
[0014] Furthermore, the first switch is one of NMOS and PMOS, and the device type of the first switch is opposite to that of the first MOS. The first driving unit includes a first inverter.
[0015] Furthermore, the first MOS is an NMOS with its drain connected to the power supply VHV; the first switch is a PMOS; one end of the voltage regulator is connected to GND, and the other end leads out the internal voltage VZ. The internal voltage VZ is connected to the positive power supply terminal of the first inverter, and the negative power supply terminal of the first inverter is connected to GND, with 5V≤VZ≤15V.
[0016] Furthermore, the first MOS is a PMOS with its drain connected to GND; the first switch is an NMOS; one end of the voltage regulator is connected to the power supply VHV, and the other end leads out the internal voltage VZ. The internal voltage VZ is connected to the negative power supply terminal of the first inverter, and the positive power supply terminal of the first inverter is connected to the power supply VHV, where VHV-5V≤VZ≤VHV-15V.
[0017] Furthermore, the first current-limiting branch includes a first current-limiting element, and the second current-limiting branch includes a second current-limiting element. Both the first and second current-limiting elements are constant current sources, and the common terminal of the two constant current sources is connected to the drain of the first MOS.
[0018] Furthermore, the first current-limiting branch includes a first current-limiting element, and the second current-limiting branch includes a second current-limiting element, both of which are resistors.
[0019] Furthermore, it also includes a second MOS, which is connected to the first MOS; the second MOS is controlled by a control signal and has the opposite switching state to that of the first MOS.
[0020] Furthermore, the second MOS is of the same device type as the first MOS, and the drain of the second MOS is connected to the source of the first MOS.
[0021] A gate drive chip includes three gate drive circuits in which the first MOS is NMOS and three gate drive circuits in which the first MOS is PMOS.
[0022] Compared with the prior art, the gate driving circuit and chip provided by this utility model have the following advantages:
[0023] (1) Compared with the existing technology, the buck converter circuit is complex and connected in series in the turn-on current path. In order to achieve higher current and response speed, a large static current is required. This utility model adopts two-level current limiting and a voltage regulator to maintain the circuit state with low current to avoid frequent charging and discharging and reduce static power consumption. With high current and source follower, a large current is directly pulled from VHV (for N-type power transistors, it is GND for P-type power transistors) to improve the instantaneous current driving capability of the output terminal, thereby increasing the turn-on current and turn-on speed of the power transistor by several times. At the same time, it achieves the effect of low static power consumption and large turn-on current.
[0024] (2) Compared with the prior art, the circuit structure of this utility model is simple, with fewer components and lower cost.
[0025] (3) A delay shutdown unit can be further added to ensure rapid turn-on with a pulse current for a period of time. After the delay shutdown, only a low current is needed to maintain the circuit state, thereby further reducing the power consumption during operation. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the structure of a gate drive circuit in the prior art;
[0027] Figure 2 This is a schematic diagram of the gate drive circuit of this utility model;
[0028] Figure 3 This is a schematic diagram of the gate drive circuit in Embodiment 1;
[0029] Figure 4 This is a schematic diagram of the gate drive circuit in Embodiment 2;
[0030] Figure 5 This is a schematic diagram of the gate drive circuit in Embodiment 3;
[0031] Figure 6 This is a schematic diagram of the gate drive circuit in Embodiment 4. Detailed Implementation
[0032] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.
[0033] Example 1:
[0034] A gate drive circuit, such as Figure 2 As shown, it includes:
[0035] The first MOS M1 is connected as a source follower, and the source outputs the gate drive signal LO.
[0036] The first driving unit has an input terminal connected to a control signal (or the inverse signal of the control signal, determined by logic), and an output terminal connected to the gate of the first MOS.
[0037] The current limiting unit includes a first current limiting branch and a second current limiting branch, which are connected in parallel. A first switch is provided on the first current limiting branch, and the first switch is controlled by a control signal. Let the current of the first current limiting branch be I1 and the current of the second current limiting branch be I2, where I1 ≥ 10 * I2. For example, in this embodiment, I1 is 400uA and I2 is 1uA. When the first MOS needs to be turned on, the first switch is turned on. The large current can increase the load capacity and speed up the drive.
[0038] A voltage regulator Z1, connected in series with the current limiting unit, provides an internal voltage VZ, which serves as the power supply for the first driving unit. The voltage regulator Z1 can be a diode with voltage regulation function, or an equivalent circuit with voltage regulation function constructed from a MOSFET or operational amplifier.
[0039] The first switch may be a MOS device, specifically one of NMOS or PMOS, and of the opposite type to the first MOS device. The first driving unit includes a first inverter X1, such that when the first switch is turned on, the first MOS device is also turned on.
[0040] The control signal can be the control signal L1 for driving the power transistor gate, or its inverted signal, such as... Figure 3As shown, an inverter X4 is added after LI so that the signals input to the first switch and the first drive unit are both inverted signals of the power transistor gate drive control signal LI.
[0041] like Figure 3 As shown, in this embodiment, the first MOS is an NMOS, and its drain is connected to the power supply VHV, which is the high voltage of the system. The first switch M3 is a PMOS, which is the opposite type of the first MOS device. One end of the voltage regulator is connected to GND, and the other end leads out the internal voltage VZ. The voltage regulator can stabilize the voltage at VZ, where 5V≤VZ≤15V. For example, in this embodiment, VZ=11V. The internal voltage VZ is connected to the positive power supply terminal of the first inverter, and the negative power supply terminal of the first inverter is connected to GND.
[0042] The first current-limiting branch includes a first current-limiting element, and the second current-limiting branch includes a second current-limiting element, such as... Figure 2 As shown, both the first and second current-limiting elements are constant current sources, and the common terminal of the two constant current sources is connected to the drain of the first MOS transistor. The first and second current-limiting elements can also be resistors, such as... Figure 3 As shown. Additionally... Figure 3 The lower end of the resistor R2 can also be directly connected to VZ.
[0043] The gate drive circuit should also include a second MOS M2, which is connected to the first MOS M1 and has the opposite switching state to the first MOS M1. The second MOS M2 cooperates with the first MOS M1 to output a gate drive signal LO. There are various specific methods to implement the function of the second MOS M2. Figure 3 This is just one example, and there are no limitations on it.
[0044] When the gate drive signal LO needs to be turned on, the first switch is turned on and the first MOS is turned on under the action of the control signal. At this time, the current is large to increase the load capacity and speed up the drive. When the gate drive signal LO does not need to be turned on, the first switch is turned off under the action of the control signal. At this time, the current is small to maintain the state with low power consumption, avoid temporary charging to reduce the speed, and save more static power consumption when idle.
[0045] Example 2:
[0046] In Example 2, specific examples of the second MOS M2 device type and connection relationships are given, such as... Figure 4As shown, the second MOS is of the same device type as the first MOS. The drain of the second MOS is connected to the source of the first MOS. The second MOS is controlled by a control signal and its switching state is opposite to that of the first MOS. Therefore, in order to ensure its correct logic relationship, it can be connected to the gate of the second MOS in sequence through two inverters X2 and X3 after X4, or directly connected to the gate of the second MOS. Figure 4 The connection method of the first switch M3 is just an example; its substrate end can be shorted to the source end or connected to VHV.
[0047] Example 3:
[0048] The difference between Embodiment 3 and Embodiment 2 is that Embodiment 3 also includes a delayed shutdown circuit, which is used to automatically disconnect the first current limiting branch after the first current limiting branch is turned on for a period of time. A pulse current for a period of time is used to ensure the rapid turn-on of the first MOS. After automatic shutdown, only a small current is needed to maintain the circuit state, which can reduce the power consumption during operation.
[0049] There are various implementations of time-delay shutdown circuits. For example, in this embodiment, a time-delay shutdown circuit connected in series in the first current-limiting branch is used as an example. Figure 5 As shown, the time-delay shutdown circuit includes a time-delay circuit, an inverter X5, and a second switch M4. The input terminal of the time-delay circuit is the control signal of the first switch M3. The output terminal of the time-delay circuit is connected to the inverter. The output terminal of the inverter is connected to the control terminal of the second switch M4. The second switch M4 is connected in series in the first current-limiting branch, thereby realizing automatic time-delay shutdown of the first current-limiting branch.
[0050] In addition, a time-delay shutdown circuit can be inserted into the control terminal of the first switch to automatically shut off the first switch after it has been turned on for a period of time.
[0051] Example 4:
[0052] The difference between Example 4 and Example 3 is that the first MOS and the second MOS in Example 4 are PMOS, such as... Figure 6 As shown, the drain of the first MOS M1 is connected to GND, and the source of the second MOS M2 is connected to the power supply VHV. The source of the first MOS M1 and the drain of the second MOS M2 are connected together and output a gate drive signal HO. The first switch and the second switch are NMOS. One end of the voltage regulator is connected to the power supply VHV, and the other end leads out the internal voltage VZ. The voltage regulator can stabilize the voltage at VZ, where VHV-5V≤VZ≤VHV-15V. For example, in this embodiment, VZ=VHV-11V. The internal voltage VZ is connected to the negative power supply terminal of the first inverter, and the positive power supply terminal of the first inverter is connected to the power supply VHV.
[0053] Example 5:
[0054] A gate driver chip includes three gate driver circuits as described in Embodiment 3 and three gate driver circuits as described in Embodiment 4, which are convenient for application in motor drives. The gate driver circuit of Embodiment 3 is used to drive N-type power transistors, and the gate driver circuit of Embodiment 4 is used to drive P-type power transistors. When applied to motors, since the static power consumption in the idle state is usually more important than the operating power consumption after power-on, the gate driver chip of this embodiment is more suitable for this requirement.
Claims
1. A gate driving circuit, characterized in that, include: The first MOS is connected as a source follower, and the source outputs the gate drive signal; The first driving unit has a control signal connected to its input terminal and a gate of the first MOS connected to its output terminal. The current limiting unit includes a first current limiting branch and a second current limiting branch, which are connected in parallel. A first switch is provided on the first current limiting branch, and the first switch is controlled by a control signal. Let the current of the first current limiting branch be I1, and let the current of the second current limiting branch be I2, where I1≥10*I2. A voltage regulator, connected in series with a current limiting unit, is used to provide an internal voltage VZ, which serves as the power supply for the first driving unit.
2. The gate driving circuit according to claim 1, characterized in that, It also includes a time-delay shutdown circuit, which includes a time-delay circuit, an inverter, and a second switch. The input of the time-delay circuit is the control signal of the first switch, the output of the time-delay circuit is connected to the inverter, the output of the inverter is connected to the control terminal of the second switch, and the second switch is connected in series in the first current-limiting branch.
3. The gate driving circuit according to claim 1, characterized in that, It also includes a time-delay shutdown circuit, which is inserted into the control terminal of the first switch and is used to shut down the first switch after the first switch has been turned on for a period of time.
4. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The first switch is one of NMOS and PMOS, and the device type of the first switch is opposite to that of the first MOS. The first driving unit includes a first inverter.
5. The gate driving circuit according to claim 4, characterized in that, The first MOS is an NMOS with its drain connected to the power supply VHV; the first switch is a PMOS; one end of the voltage regulator is connected to GND, and the other end leads out the internal voltage VZ. The internal voltage VZ is connected to the positive power supply terminal of the first inverter, and the negative power supply terminal of the first inverter is connected to GND. 5V≤VZ≤15V.
6. The gate driving circuit according to claim 4, characterized in that, The first MOS is a PMOS with its drain connected to GND; the first switch is an NMOS; one end of the voltage regulator is connected to the power supply VHV, and the other end leads out the internal voltage VZ. The internal voltage VZ is connected to the negative power supply terminal of the first inverter, and the positive power supply terminal of the first inverter is connected to the power supply VHV. VHV-5V≤VZ≤VHV-15V.
7. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The first current-limiting branch includes a first current-limiting element, and the second current-limiting branch includes a second current-limiting element. Both the first and second current-limiting elements are constant current sources or both are resistors. If both the first and second current-limiting elements are constant current sources, the common terminal of the two constant current sources is connected to the drain of the first MOS.
8. The gate driving circuit according to any one of claims 1 to 3, characterized in that, It also includes a second MOS, which is connected to the first MOS; the second MOS is controlled by a control signal and its switching state is opposite to that of the first MOS.
9. The gate driving circuit according to claim 8, characterized in that, The second MOS is of the same device type as the first MOS, and the drain of the second MOS is connected to the source of the first MOS.
10. A gate driver chip, characterized in that, It includes three gate drive circuits as described in claim 5 and three gate drive circuits as described in claim 6.