Test fixture and test system
By designing test fixtures and test systems compatible with multiple wafers, the problem that a single circuit cannot adapt to diverse wafer testing was solved, achieving the effects of simplified prototyping and reduced costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2026-03-06
AI Technical Summary
In existing technologies, a single specific circuit cannot meet the diverse wafer testing needs, resulting in the need to mass-produce memory chips with various combinations, which leads to a waste of manpower and time costs.
Design a test fixture including a first test board and a second test board. The second test board is equipped with a DIP switch and multiple detection circuits. The detection circuits can be adjusted by the DIP switch to adapt to different wafers. Combined with a programmer and a display, a test system is formed, which simplifies the prototyping process of different wafer combinations.
It enables compatibility testing for multiple wafers, saving time on prototyping substrates and packaging, and reducing costs.
Smart Images
Figure CN223977310U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing technology, and in particular to a test fixture and a test system. Background Technology
[0002] Before a chip can be used, it needs to undergo various tests to remove potential defects. These tests include applying voltage to it or testing it in high-temperature environments corresponding to thermal and mechanical environmental tests to make it work or store it, thereby screening out qualified and defective products. These tests are carried out in a non-destructive manner, and chip test fixtures are required for these various tests.
[0003] Due to the rapid development of the semiconductor industry, there are many types of memory chips, each with different controller configurations. Memory chips also require read / write operations, high / low temperature testing, and timing diagram capture for software debugging. eMMC packaging involves encapsulating both the controller and the wafer, followed by testing using specific circuitry. Because the wafer capacities vary, a single specific circuit cannot meet the testing requirements of various wafer solutions. This necessitates the mass production of various combinations of memory chips, resulting in significant manpower and time costs. Therefore, these problems urgently need to be addressed. Utility Model Content
[0004] The purpose of this application is to provide a test fixture and test system that are compatible with various wafer tests and reduce costs.
[0005] This application discloses a test fixture for testing a wafer to be inspected. The test fixture includes a first test board and a second test board. The first test board is disposed below the second test board and is electrically connected to the second test board. The second test board includes a second test board body, a DIP switch, and multiple detection circuits. The multiple detection circuits are disposed within the second test board body, and the DIP switch is disposed on the second test board body and is electrically connected to the multiple detection circuits. The wafer to be inspected is connected to the second test board, and the corresponding detection circuit is selected by the DIP switch to perform inspection on the wafer.
[0006] Optionally, the first test board includes a first test board body, a first interface, and multiple gold fingers. The first interface and the gold fingers are disposed on the first test board body and are far apart from each other. One end of the multiple detection circuits is connected to the multiple gold fingers, and the other end is connected to the first interface. The second test board further includes a main control module and a second interface. The main control module is disposed on one side of the DIP switch, and the DIP switch controls the multiple detection circuits through the main control module. The second interface is disposed on one side of the main control module and is electrically connected to the main control module. The first interface and the second interface are interlocked.
[0007] Optionally, the DIP switch is located on the front of the second test board body, and the main control module and the second interface are both located on the back of the second test board body. The second test board also includes multiple connection pads, which are electrically connected to multiple detection circuits. The wafer to be tested is connected to the connection pads.
[0008] Optionally, the first test board further includes multiple first test points, which are disposed on the body of the first test board and located between the first interface and the gold finger; the second test board further includes multiple second test points, which are disposed on the body of the second test board and located on the side of the main control module away from the second interface; one end of the first test point is connected to the pin of the first interface and the other end is connected to the gold finger, and the second test point is connected to the detection circuit.
[0009] Optionally, the test fixture further includes a test holder, which is disposed on the side of the second test board away from the first test board and is electrically connected to the second test board. The test holder includes a connecting plate and a limiting frame, which is disposed on the connecting plate and cooperates with the connecting plate to form a wafer placement position. The wafer placement position has a plurality of first connection points, and the side of the connecting plate away from the wafer placement position has a plurality of second connection points. The first connection points are electrically connected to the second connection points, and the second connection points are electrically connected to the connection pads. When the wafer to be tested is placed in the wafer placement position, the pads on the wafer are connected to the connection pads through the first connection points and the second connection points, and then connected to the detection circuit.
[0010] Optionally, the DIP switch includes a first pin, a second pin, a third pin, a fourth pin, and a fifth pin. The first pin, the second pin, the third pin, the fourth pin, and the fifth pin are all disposed on the second test board body. The voltage of the first pin, the second pin, the third pin, and the fifth pin is 3.5V, and the voltage of the fourth pin is 1.8V.
[0011] Optionally, the second test board is a BGA132 feature analysis board, and both the first and second test points are test points related to the eMMC 5.1 protocol.
[0012] Optionally, multiple first test points are arranged in a column, and multiple second test points are arranged in a column.
[0013] Optionally, the limiting frame and the second test plate are fixedly connected by a screw structure; the first interface is a male connector and the second interface is a female connector.
[0014] This application also discloses a test system, including a programmer, a display, and a test fixture as described above, wherein the test fixture is electrically connected to the programmer, and the programmer is electrically connected to the display.
[0015] Compared to traditional test fixtures that can only test a single wafer capacity, leading to incompatibility when testing wafers with diverse capacities, the test fixture of this application includes a first test board and a second test board. The first test board is positioned below the second test board and is electrically connected to it. The second test board includes a second test board body, a DIP switch, and multiple detection circuits. The multiple detection circuits are located within the second test board body, and the DIP switch is located on the second test board body and electrically connected to the multiple detection circuits. By connecting the wafer to be tested to the second test board and switching the DIP switch to the corresponding detection circuit, the wafer can be tested. This allows for testing of different wafers, simplifying the prototyping of different wafer combinations, saving time on prototyping substrates and packaging, and thus reducing costs. Attached Figure Description
[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:
[0017] Figure 1This is a block diagram of the testing system provided in the embodiments of this application;
[0018] Figure 2 This is a schematic diagram of the overall structure of the test fixture provided in the embodiments of this application;
[0019] Figure 3 yes Figure 2 A schematic diagram of the front structure of the second test board;
[0020] Figure 4 yes Figure 2 A schematic diagram of the structure of the first test board;
[0021] Figure 5 yes Figure 3 A schematic diagram of the back structure of the second test board;
[0022] Figure 6 This is a bottom view of the test stand provided in an embodiment of this application;
[0023] Figure 7 This is a schematic diagram of the testing principle of the testing fixture provided in the embodiments of this application;
[0024] Figures 8-9 This is an example of a timing diagram measured in an embodiment of this application.
[0025] The components are as follows: 10. Test system; 100. Test fixture; 110. First test board; 111. First test board body; 112. First interface; 113. Multiple gold fingers; 114. First test point; 120. Second test board; 121. Detection circuit; 122. DIP switch; 123. Second test board body; 124. Main control module; 125. Second interface; 126. Connecting pad; 127. Second test point; 128. First pin; 129. Second pin; 130. Third pin; 131. Fourth pin; 132. Fifth pin; 140. Test socket; 141. Connecting board; 142. Limiting frame; 143. Wafer placement position; 144. First connection point; 145. Second connection point; 146. Cover plate; 147. Bump; 150. Screw structure; 200. Programmer; 300. Display. Detailed Implementation
[0026] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.
[0027] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of indicated technical features. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean a non-exclusive inclusion, which may include or add one or more other features, integers, steps, operations, units, components, and / or combinations thereof. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0028] The present application will now be described in detail with reference to the accompanying drawings and embodiments.
[0029] Figure 1 This is a block diagram of the test system provided in the embodiments of this application, as shown below. Figure 1 As shown, this application discloses a testing system, including a programmer, a display, and a test fixture. The test fixture is used for testing a wafer to be tested. The test fixture is electrically connected to the programmer, and the programmer is electrically connected to the display. The test fixture is connected to the programmer, and the wafer to be tested is placed in the test fixture for testing. The test status can be directly observed through the display.
[0030] Specifically, Figure 2 This is a schematic diagram of the overall structure of the test fixture provided in the embodiments of this application. Figure 3 yes Figure 2 The diagram shows the front view of the second test board. The test fixture includes a first test board and a second test board. The first test board is positioned below the second test board and is electrically connected to it. The second test board includes a second test board body, a DIP switch, and multiple detection circuits. The multiple detection circuits are disposed within the second test board body, and the DIP switch is disposed on the second test board body and electrically connected to the multiple detection circuits. The wafer to be tested is connected to the second test board, and the corresponding detection circuit is selected via the DIP switch to perform testing on the wafer.
[0031] Compared to traditional test fixtures that can only test a single wafer capacity, leading to incompatibility when testing wafers with diverse capacities, the test fixture of this application includes a first test board and a second test board. The first test board is positioned below the second test board and is electrically connected to it. The second test board includes a second test board body, a DIP switch, and multiple detection circuits. The multiple detection circuits are located within the second test board body, and the DIP switch is located on the second test board body and electrically connected to the multiple detection circuits. By connecting the wafer to be tested to the second test board and switching the DIP switch to the corresponding detection circuit, the wafer can be tested. This allows for testing of different wafers, simplifying the prototyping of different wafer combinations, thereby saving time on prototyping substrates and packaging, and reducing costs.
[0032] The programmer is an SM333 programmer. Figure 4 yes Figure 2 A schematic diagram of the structure of the first test board is shown below. Figure 4 As shown, the first test board includes a first test board body, a first interface, and multiple gold fingers. The first interface and the gold fingers are disposed on the first test board body and are far apart from each other. One end of the multiple detection circuits is connected to the multiple gold fingers, and the other end is connected to the first interface. The gold fingers are used to connect to the SM333 programmer.
[0033] Figure 4 yes Figure 3 A schematic diagram of the back structure of the second test board is shown below. Figure 4 As shown, combined with Figure 2 The second test board also includes a main control module and a second interface. The main control module is located on one side of the DIP switch, and the DIP switch controls multiple detection circuits through the main control module. The second interface is located on one side of the main control module and is electrically connected to the main control module. The first interface and the second interface are interlocked. The first interface is a male connector, and the second interface is a female connector. Of course, it is also possible for the first interface to be female and the second interface to be male; the specific design depends on the requirements and is not limited here.
[0034] The main control module is the SM2730 main control module. If a specific SM2730 main control module is packaged with a specific combination of wafers, a new substrate for that combination needs to be prototyped. That is, different combinations of main control modules with different wafers require many different substrates. Now, by using a common main control module, it is simplified to only needing to prototypify the substrate corresponding to the wafer. If the substrate for prototyping is in stock, then only the wafer needs to be packaged. This saves the time for prototyping substrates and correspondingly saves the cost of packaging and prototyping substrates.
[0035] The DIP switch is located on the front of the second test board body, and the main control module and the second interface are both located on the back of the second test board body. The front is the side of the second test board body that is close to the test socket, and the back is the side of the second test board body that is away from the test socket.
[0036] like Figure 3 As shown, the second test board also includes multiple connection pads, which are electrically connected to multiple detection circuits, and the wafer to be tested is connected to the connection pads. The DIP switch includes a first pin, a second pin, a third pin, a fourth pin, and a fifth pin. The first pin, second pin, third pin, fourth pin, and fifth pin are all located on the body of the second test board. The voltage of the first pin, second pin, third pin, and fifth pin is 3.5V, and the voltage of the fourth pin is 1.8V. This allows adjustment of the voltage required by the corresponding detection circuit, facilitating various circuit selections.
[0037] The second test board is a BGA132 characteristic analysis board. The test socket is connected to the characteristic analysis board via a screw structure. Specifically, the second test board can have multiple fixing screw holes, and the test socket can also have corresponding fixing screw holes. Screws are used to connect and fix the test socket to the second test board. Of course, other connection and fixing methods can also be used, which are not limited here.
[0038] like Figure 2 As shown, the test fixture further includes a test holder for placing and fixing the wafer to be tested, and the wafer to be tested is not easily displaced, facilitating testing. The test holder is located on the side of the second test board away from the first test board and is electrically connected to the second test board. The test holder includes a connecting plate and a limiting frame. The limiting frame is located on the connecting plate and cooperates with the connecting plate to form a wafer placement position. Multiple first connection points are provided in the wafer placement position, and multiple second connection points are provided on the side of the connecting plate away from the wafer placement position. The first connection points are electrically connected to the second connection points, and the second connection points are electrically connected to the connecting pads. When the wafer to be tested is placed in the wafer placement position, the pads on the wafer to be tested are connected to the connecting pads through the first connection points and the second connection points, and then connected to the testing circuit.
[0039] like Figure 5As shown, the first test board further includes multiple first test points, which are disposed on the body of the first test board and located between the first interface and the gold finger; the second test board further includes multiple second test points, which are disposed on the body of the second test board and located on the side of the main control module away from the second interface; one end of each first test point is connected to a pin of the first interface, and the other end is connected to the gold finger, while the second test point is connected to the detection circuit. Both the first and second test points are eMMC 5.1 protocol-related test points. Different IO configurations can be adjusted via a DIP switch to support eMMC products with the SM2730 main control and various memory chip solutions. Switching the switch connects to a high voltage, and leaving it on connects to a low voltage. Of course, it can also be designed according to specific product models for testing wafers other than eMMC, which is not limited here.
[0040] like Figure 7 As shown, the testing principle of the test fixture is as follows: The epop_144 internally encapsulates the main controller SM2730. The SM2730 inputs VCC 3.3V (provided by the CN1 pin) and 1.8V through the epop_144 and outputs F-VCCQ (1.2V or 1.8V) and VCC 2.5V to the BGA132 wafer. When the BGA132 wafer uses 3.3V, it is provided by the CN1 pin. Physically, the selector switch JP4 controls the selection pin of the main controller SM2730, which is compatible with different wafer models, so that different wafers can be tested through this test fixture.
[0041] Figures 8-9 This is an example of a timing diagram measured according to an embodiment of this application, such as... Figure 8-9 As shown, the DAT0-7 signals are mainly used for data transmission between the Host and the eMMC. After the eMMC is powered on or soft-reset, only DAT0 can transmit data. After initialization, either DAT0-3 or DAT0-7 can be configured for data transmission, meaning the data bus can be configured in 4-bit or 8-bit mode. The CLK signal is used to output a clock signal from the Host side for data transmission synchronization and device operation driving.
[0042] Within one clock cycle, both the CMD and DAT0-7 signals can support the transmission of one bit, i.e., SDR (Single Data Rate) mode. Additionally, the DAT0-7 signal can also be configured for DDR (Double Data Rate) mode, which can transmit two bits within one clock cycle.
[0043] In single data rate mode, data is output by the device clock, and the host samples it on the rising edge of the clock. Each data line has only one parity bit. In dual data rate mode, data is output on both the rising and falling edges of the clock, with two additional parity bits added to each data line. All timing on the DAT lines should follow DDR timing patterns. The start bit, stop bit, and boot acknowledgment bit are only valid on the rising edge of the clock.
[0044] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.
[0045] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.
Claims
1. A test fixture for testing of a wafer to be inspected, characterized by, The test fixture comprises a first test plate and a second test plate, the first test plate is arranged below the second test plate and is in electrical connection with the second test plate, the second test plate comprises a second test plate body, a DIP switch and a plurality of detection circuits, the plurality of detection circuits are arranged in the second test plate body, the DIP switch is arranged on the second test plate body and is in electrical connection with the plurality of detection circuits; The wafer to be detected is connected with the second test plate, the corresponding detection circuit is adjusted through the DIP switch, and the wafer to be detected is detected.
2. The test fixture of claim 1, wherein, The first test plate comprises a first test plate body, a first interface and a plurality of gold fingers, the first interface and the gold fingers are arranged on the first test plate body and are away from each other, one end of the plurality of detection circuits is connected with the plurality of gold fingers, and the other end is connected with the first interface; The second test plate further comprises a master control module and a second interface, the master control module is arranged on one side of the DIP switch, the DIP switch controls the plurality of detection circuits through the master control module, and the second interface is arranged on one side of the master control module and is in electrical connection with the master control module; The first interface is in embedded connection with the second interface.
3. The test fixture of claim 2, wherein, The DIP switch is arranged on the front surface of the second test plate body, the master control module and the second interface are arranged on the back surface of the second test plate body, the second test plate further comprises a plurality of connection pads, the plurality of connection pads are in electrical connection with the plurality of detection circuits, and the wafer to be detected is connected with the connection pads.
4. The test fixture of claim 2, wherein, The first test plate further comprises a plurality of first test points, the plurality of first test points are arranged on the first test plate body and are located between the first interface and the gold fingers, and the second test plate further comprises a plurality of second test points, the plurality of second test points are arranged on the second test plate body and are located on one side of the master control module away from the second interface; One end of the first test point is connected with the pin of the first interface, and the other end is connected with the gold finger, and the second test point is connected with the detection circuit.
5. The test fixture of claim 3, wherein, The test fixture further comprises a test seat, the test seat is arranged on one side of the second test plate away from the first test plate and is in electrical connection with the second test plate; The test seat comprises a connecting plate and a limiting frame, the limiting frame is arranged on the connecting plate and cooperates with the connecting plate to form a wafer placing position, a plurality of first connecting points are arranged in the wafer placing position, a plurality of second connecting points are arranged on one side of the connecting plate away from the wafer placing position, the first connecting points are in electrical connection with the second connecting points, and the second connecting points are in electrical connection with the connection pads; When the wafer to be detected is placed in the wafer placing position, the pads on the wafer to be detected are connected to the connection pads through the first connecting points and the second connecting points, and then are connected to the detection circuits.
6. The test fixture of claim 3, wherein, The dial switch comprises a first pin, a second pin, a third pin, a fourth pin and a fifth pin, the first pin, the second pin, the third pin, the fourth pin and the fifth pin are arranged on the second test plate body, the voltage of the first pin, the second pin, the third pin and the fifth pin is 3.5V, and the voltage of the fourth pin is 1.8V.
7. The test fixture of claim 4, wherein, The second test plate is a BGA132 characteristic analysis plate, and the first test point and the second test point are both test points related to an eMMC 5.1 protocol.
8. The test fixture of claim 4, wherein, The first test points are arranged in a column, and the second test points are arranged in a column.
9. The test fixture of claim 5, wherein, The limiting frame is fixedly connected with the second test plate through a screw structure, the first interface is a male head, and the second interface is a female head.
10. A test system, characterized by The test tool comprises a burner, a display and the test tool according to any one of claims 1-9, the test tool is electrically connected with the burner, and the burner is electrically connected with the display.