800G OSFP DAC realizing Reset function based on comparator

Abstract

The utility model discloses an 800G OSFP DAC realizing a Reset function based on a comparator, which belongs to the technical field of integrated circuit design and comprises a low-speed pin Reset on a golden finger, a comparator chip, an EEPROM chip and an external adjustment evaluation board connected with the golden finger and providing low level for the low-speed pin Reset. The low-speed pin Reset is connected in parallel with the upper resistor and the lower resistor, is connected to the positive electrode of the input pin of the comparator chip, compares the reference voltage of the negative electrode of the input pin with the reference voltage of the output level EVCC, and then is connected to the EEPROM chip. According to the scheme, a new Reset function design circuit is provided, the connection mode has the advantages of being convenient to operate and reducing cost, and meanwhile long-term stability and reliability of products are guaranteed.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit design, specifically to an 800G OSFP DAC that implements a Reset function based on a comparator. Background Technology

[0002] The 800G OSFP DAC, also known as the 800G Small Molded Direct-Connect Copper DAC, can transmit 800 gigabits per second, providing massive bandwidth capacity to meet the high-bandwidth, high-speed data transmission needs of scenarios such as data centers. Despite its high-speed capabilities, it consumes very little power, making it an environmentally friendly choice for low-carbon, green data centers. The 800G OSFP DAC complies with OSFP MSA and IEEE 802.3ck specifications, using 16 pairs of copper cables to support 8 channels of 112GB / s bidirectional transmission and achieving backward compatibility. This product is fully compatible with NVIDIA devices and matches NVIDIA product specifications, offering inherent advantages in terms of cost, power consumption, transmission latency, and failure rate.

[0003] Currently, the reset function of an 800G OSFP DAC is generally implemented through a low-speed controller chip, using complex comparisons to determine the reset level. Existing patent CN116961665A discloses a high-speed SAR ADC employing dual comparators. Its technical solution involves two comparators working alternately to compare the voltage of the upper plate of the capacitor array during the SAR ADC conversion process. After the comparison is complete, the switching control logic directly switches the capacitors based on the comparison result, allowing the latching operation of the comparator comparison result in the SAR logic to be performed in parallel with the switching operation of the lower plate of the capacitors. However, this solution does not involve a new design for the reset function.

[0004] Given that the current 800G OSFP DAC requires a low-speed controller chip to perform complex comparisons and judgments using the Reset level to implement the Reset function, this solution is proposed. Utility Model Content

[0005] This invention aims to solve the problem that existing 800G OSFP DACs require a low-speed controller chip to perform complex comparisons and judgments using the Reset level to implement the Reset function. It proposes an 800G OSFP DAC that implements the Reset function based on a comparator. The low-speed pin Reset of the 800G OSFP DAC is connected to the reference voltage between the positive and negative input terminals of the comparator chip to compare the output level. The Reset function is achieved by externally adjusting Reset to a low level. This connection method is more convenient to operate, reduces costs, and ensures the long-term stability and reliability of the product.

[0006] To achieve the above-mentioned objectives, the technical solution of this utility model is as follows:

[0007] An 800G OSFP DAC based on a comparator to implement a Reset function includes a low-speed pin Reset on the gold fingers, a comparator chip, an EEPROM chip, and an external adjustment and evaluation board connected to the gold fingers and providing a low level to the low-speed pin Reset. The low-speed pin Reset is connected to the positive terminal of the input pin of the comparator chip while being connected to the upper and lower resistors in parallel. It is compared with the reference voltage of the negative terminal of the input pin to output a level EVCC, which is then connected to the EEPROM chip.

[0008] Furthermore, the low-speed pin Reset is connected in parallel with upper and lower resistors R1 and R3 respectively, with resistor R1 connected to the power supply and resistor R3 grounded.

[0009] Furthermore, the comparator includes an input pin positive terminal V+, an input pin negative terminal V-, an output level OUT, a power supply pin VCC, and a ground pin GND.

[0010] Furthermore, the EEPROM chip includes an I2C interface, a ground pin GND, a write protection pin WP, and a power supply pin VCC.

[0011] The working principle of this utility model is as follows:

[0012] Because the low-speed pin Reset is connected in parallel with upper and lower resistors, the Reset level remains high when it does not change. The high-level Reset positive voltage is higher than the negative reference voltage, and the high-level output provides the power supply for the EEPROM chip to work normally.

[0013] The gold fingers are connected to an external adjustment and evaluation board. The Reset pin of the external adjustment and evaluation board is low, which is supplied to the Reset pin on the product's gold fingers. The low-level Reset positive voltage is lower than the negative reference voltage, and the low-level output is supplied to the EEPROM chip power supply to malfunction, thus realizing the Reset function.

[0014] In summary, this utility model has the following advantages:

[0015] This invention proposes a novel Reset function design for an 800G OSFP DAC copper cable product. The low-speed Reset pin on the gold fingers of the 800G OSFP DAC product is connected to the reference voltage between the positive and negative input pins of the comparator chip to compare the output level. When the product is inserted into the evaluation board, due to the parallel connection of upper and lower resistors on the Reset low-speed pin, the Reset level remains high when not changed, thus disabling the Reset function. External adjustment of the Reset level to low enables the Reset function. This connection method offers significant advantages: ease of operation, reduced costs, and ensures long-term product stability and reliability. Attached Figure Description

[0016] Figure 1 The boxed portion is a schematic diagram of the gold fingers of an existing 800G OSFP DAC;

[0017] Figure 2 This is a schematic diagram of the comparator structure in this utility model;

[0018] Figure 3 This is a schematic diagram of the structure of the EEPROM chip in this utility model.

[0019] In the picture:

[0020] J1, gold finger; U2, EEPROM chip; U3, comparator chip. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0023] Example 1

[0024] To address the issue that existing 800G OSFP DACs require a low-speed controller chip to perform complex comparisons and judgments based on the Reset level to implement the Reset function, this embodiment proposes an 800G OSFP DAC that implements the Reset function based on a comparator, such as... Figure 1 As shown, it includes a low-speed pin Reset on the gold finger, a comparator chip, an EEPROM chip, and an external adjustment evaluation board connected to the gold finger and providing a low level to the low-speed pin Reset; the low-speed pin Reset is connected to the positive terminal of the input pin of the comparator chip while being connected to the upper and lower resistors in parallel, and is compared with the reference voltage of the negative terminal of the input pin to output the level EVCC, which is then connected to the EEPROM chip.

[0025] like Figure 1 The boxed portion shown is a schematic diagram of the gold fingers of an existing 800G OSFP DAC, which contains 60 pins based on the packaging protocol, with the low-speed pin Reset being the 44th pin.

[0026] The working principle of this utility model is as follows:

[0027] Because the low-speed pin Reset is connected in parallel with upper and lower resistors, with the upper resistor connected to the power supply and the lower resistor grounded to achieve a voltage divider effect, the Reset level remains high when it does not change. The high-level Reset positive terminal has a higher voltage than the negative reference terminal, and the high-level output provides the power supply for the EEPROM chip to operate normally.

[0028] The gold fingers are connected to an external adjustment and evaluation board. The Reset pin of the external adjustment and evaluation board is low, which is supplied to the Reset pin on the product's gold fingers. The low-level Reset positive voltage is lower than the negative reference voltage, and the low-level output is supplied to the EEPROM chip power supply to malfunction, thus realizing the Reset function.

[0029] Example 2

[0030] This embodiment provides an 800G OSFP DAC that implements a Reset function based on a comparator, including a low-speed pin Reset on the gold finger, a comparator chip, an EEPROM chip, and an external adjustment and evaluation board connected to the gold finger and providing a low level to the low-speed pin Reset; the low-speed pin Reset is connected to the positive terminal of the input pin of the comparator chip while being connected to the upper and lower resistors in parallel, and is compared with the reference voltage of the negative terminal of the input pin to output the level EVCC, which is then connected to the EEPROM chip.

[0031] Furthermore, the low-speed pin Reset is connected in parallel with upper and lower resistors R1 and R3 respectively, with resistor R1 connected to the power supply and resistor R3 grounded.

[0032] Furthermore, such as Figure 2The diagram shows the circuit structure of the comparator chip. Comparator U3 includes an input pin (positive V+), an input pin (negative V-), an output pin (OUT), a power supply pin (VCC), and a ground pin (GND). It should be noted that this solution is not limited to a specific model of comparator; any product with the same pin definitions and functions can be used as a substitute.

[0033] Furthermore, such as Figure 3 The diagram shows the circuit structure of an EEPROM chip. EEPROM chip U2 includes an I2C interface, a ground pin (GND), a write protection pin (WP), and a power supply pin (VCC). The low-speed pin (Reset) is connected to the comparator chip's input pin positive and compares the reference voltage output level (EVCC) with the input pin negative, which is then connected to the EEPROM chip's power supply pin (VCC). It should be noted that this solution is not limited to a specific EEPROM chip model; any product with the same pin definitions and functions can be used.

[0034] When the 800G OSFP DAC copper cable product of this solution is inserted into the external adjustment evaluation board, the Reset low-speed pin is connected in parallel with upper and lower resistors. When the Reset level remains unchanged, it remains high, and the Reset function is disabled. The Reset function is enabled when the external adjustment lowers the Reset level. This connection method offers advantages such as ease of operation and reduced costs, while ensuring the long-term stability and reliability of the product.

[0035] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present utility model shall fall within the protection scope of the present utility model.

Claims

1. An 800G OSFP DAC implementing a Reset function based on a comparator, characterized in that, The low-speed pin Reset on the golden finger, a comparator chip, an EEPROM chip, and an external adjusting evaluation board connected with the golden finger and providing a low level to the low-speed pin Reset are included; the low-speed pin Reset is connected to the positive input pin of the comparator chip in parallel with upper and lower resistors, compares the output level EVCC with the reference voltage of the negative input pin, and is connected to the EEPROM chip.

2. The 800G OSFP DAC implementing Reset function based on comparator according to claim 1, wherein, The low-speed pin Reset is connected to the positive input pin of the comparator chip in parallel with upper and lower resistors R1 and R3, respectively; the resistor R1 is connected to the power supply, and the resistor R3 is grounded.

3. The 800G OSFP DAC implementing Reset function based on comparator of claim 1, wherein, The comparator comprises a positive input pin V+, a negative input pin V-, an output level OUT, a power supply pin VCC, and a ground pin GND.

4. The 800G OSFP DAC implementing Reset function based on comparator of claim 1, wherein, The EEPROM chip comprises an I2C interface, a ground pin GND, a write protection pin WP, and a power supply pin VCC.

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