Breakdown voltage detection device

Abstract

According to the breakdown voltage detection device provided by the utility model, the lead-out region is not covered by the metal silicide layer and is in direct contact with the metal interconnection structure, so that the resistance value of the lead-out region is increased, and the voltage of the lead-out region is reduced, so that a longitudinal PNP structure QPNP in a latch loop is always in a cut-off state; the generation of a latch loop and the generation of a leakage path are avoided, so that the phenomenon of large leakage is solved, and the normal mass production of PMIC products is ensured.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a breakdown voltage detection device. Background Technology

[0002] In PMIC (Power Management Integrated Circuit) product design, it is necessary to detect the breakdown voltage of one of the NMOS transistors. For example... Figure 1 As shown, in current PMIC (Power Management Integrated Circuit) product breakdown voltage detection devices, transistors Q1 and Q2 are both PMOS transistors, while transistors Q3, Q4, and Q5 are all NMOS transistors. Transistor Q3 is the transistor being tested. Figure 1 In the circuit, when the input voltage Vin is greater than the source voltage VCC, transistors Q1 and Q2 turn on, and current flows from the input terminal through transistor Q1, then through transistor Q2, and finally into the gate of transistor Q3, causing transistor Q3 to turn on. When transistor Q3 turns on, a latch-up loop is formed in transistor Q3 between the input voltage Vin and ground GND. This causes the input voltage Vin to leak directly to ground GND through the latch-up loop, making transistor Q3 a leakage path. This results in a large leakage current between the input voltage Vin and ground GND, posing a serious risk, such as chip burnout, and potentially damaging the entire wafer, rendering it unusable and preventing the normal mass production of PMIC products. Utility Model Content

[0003] The purpose of this invention is to provide a breakdown voltage detection device that can solve the problem of large leakage current and ensure the normal mass production of PMIC products.

[0004] To address the above problems, this invention provides a breakdown voltage detection device, including an NMOS transistor under test. The NMOS transistor under test includes a first well region and a second well region disposed in a substrate. The first well region has a first doped region and a lead-out region, and the second well region has a second doped region. A gate structure is disposed on the substrate at the junction of the first well region and the second well region. The first doped region is arranged around the outside of the lead-out region. The first doped region and the lead-out region are in contact, and a metal silicide layer is disposed on the first doped region and the second doped region. A metal interconnect structure is disposed on the substrate, and the metal silicide layer and the lead-out region are in contact with the metal interconnect structure.

[0005] Optionally, the first well region, the first doped region, and the second doped region are all doped with N-type ions, and the second well region, the extraction region, and the substrate are all doped with P-type ions.

[0006] Optionally, a shallow trench isolation structure is provided in the first well region, the shallow trench isolation structure defines a first doped region, and the first doped region and the lead-out region are arranged sequentially from the outside to the inside in the substrate inside the shallow trench structure.

[0007] Optionally, a body region is provided in the second well region, the second doped region and the body region are spaced apart, and the second doped region is located between the first doped region and the body region; wherein, the body region is doped with P-type ions.

[0008] Furthermore, in the first well region, the metal silicide layer covers the first doped region and exposes the lead-out region; in the second well region, the metal silicide layer covers the second doped region and exposes the body region.

[0009] Optionally, the surface of the lead-out region is higher than the surface of the first doped region, and the surface of the lead-out region is flush with the surface of the metal silicide layer in the first well region.

[0010] Furthermore, a metal interconnect structure is also provided on the substrate. The metal interconnect structure includes a first conductive pillar and a second conductive pillar. The first conductive pillar is in contact with both the metal silicide layer of the first well region and the lead-out region. The second conductive pillar is connected to the metal silicide layer of the second well region.

[0011] Optionally, the breakdown voltage detection device includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein the first transistor and the second transistor are both PMOS transistors, and the third transistor, the fourth transistor, and the fifth transistor are all NMOS transistors, and the third transistor is the NMOS crystal to be tested;

[0012] One terminal of the first transistor and one terminal of the second transistor are simultaneously connected to the power supply VCC. The other terminal of the first transistor is connected to one terminal of the third transistor, one terminal of the fourth transistor, and the input terminal. The input terminal is connected to the input voltage. The gate terminal of the first transistor is simultaneously connected to the other terminal of the second transistor, the gate terminal of the third transistor, and one terminal of the fifth transistor. The gate terminal of the second transistor is connected to a gate voltage source and is also connected to the gate terminal of the fifth transistor. The other terminal of the fourth transistor, the other terminal of the third transistor, the substrate of the third transistor, and the other terminal of the fifth transistor are all grounded.

[0013] Furthermore, one connection terminal of the first transistor is a drain region and the other connection terminal is a source region; or, one connection terminal of the first transistor is a source region and the other connection terminal is a drain region.

[0014] One connection terminal of the second transistor is the drain region, and the other connection terminal is the source region; or, one connection terminal of the second transistor is the source region, and the other connection terminal is the drain region.

[0015] Furthermore, one connection terminal of the third transistor, one connection terminal of the fourth transistor, and one connection terminal of the fifth transistor are all drain regions; the other connection terminal of the third transistor, the other connection terminal of the fourth transistor, and the other connection terminal of the fifth transistor are all source regions.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] This invention provides a breakdown voltage detection device, including an NMOS transistor under test. The NMOS transistor under test includes a first well region and a second well region disposed in a substrate. The first well region has a first doped region and a lead-out region, and the second well region has a second doped region. A gate structure is disposed on the substrate at the junction of the first and second well regions. The first doped region is arranged around the outside of the lead-out region, and the first doped region and the lead-out region are in contact. A metal silicide layer is disposed on the first and second doped regions. A metal interconnect structure is disposed on the substrate, and the metal silicide layer and the lead-out region are in contact with the metal interconnect structure. This invention increases the resistance of the lead-out region and reduces its voltage by ensuring that the vertical PNP structure QPNP in the latch-up circuit is always in the off state. This avoids the generation of latch-up circuit and leakage path, thus solving the problem of large leakage and ensuring the normal mass production of PMIC products. Attached Figure Description

[0018] Figure 1 This is a circuit diagram of a breakdown voltage detection device for an NMOS transistor.

[0019] Figure 2 This is a schematic diagram of the circuit principle for generating a latching circuit.

[0020] Figures 3A-3B This is a schematic diagram of the structure of an NMOS transistor.

[0021] Figures 4A-4B This is a schematic diagram of the structure of the NMOS transistor under test provided in an embodiment of the present invention.

[0022] Explanation of reference numerals in the attached figures:

[0023] 10-Substrate; 11-First well region; 12-Second well region; 13-First doped region; 14-Lead-out region; 15-Second doped region; 16-Bulk region; 18-Metal silicide layer; 20-Gate structure; 31-First conductive pillar; 32-Second conductive pillar. Detailed Implementation

[0024] The following is a further detailed description of a breakdown voltage detection device according to the present invention. The present invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art can modify the present invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the present invention.

[0025] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would confuse the present invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0026] To make the objectives and features of this utility model clearer and easier to understand, the specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model.

[0027] like Figure 2 As shown, the principle of latch-up circuit generation is as follows: In the NMOS transistor between the input voltage Vin and ground GND, a low-impedance path is generated due to the interaction of the parasitic vertical PNP and lateral NPN bipolar BJT. The lateral NPN can gradually increase the conduction degree of the vertical PNP. The greater the conduction of the vertical PNP, the greater the current fed back to the lateral NPN (i.e., the greater the conduction of the lateral NPN). Finally, the lateral NPN and the vertical PNP are in a state of extremely low resistance conduction. At this time, the input voltage Vin and ground GND are approximately short-circuited, resulting in a large leakage current between the input terminal and ground GND.

[0028] like Figure 3AAs shown, during the breakdown voltage detection process, the P+ lead-out region 1 and the N-well region Nwell in transistor Q3, located at the input terminal connection position, are at the same potential, and the voltage is equal to the input voltage Vin (e.g., 5V), which is greater than the source voltage VCC. At this time, transistor Q3 is turned on, and vertically, the P+ lead-out region 1, the N-well region Nwell, and the P-type substrate Psub form a PNP structure Q. PNP Laterally, the N-well region (Nwell), the P-well region (Pwell), and the N+ doped region 2 located at the ground (GND) connection site constitute the NPN structure Q. NPN .

[0029] When transistor Q3 is turned on, a conductive channel is first formed in transistor Q3. This conductive channel shares the voltage of the N-well region, causing a drop in the N-well voltage at the input voltage Vin connection location. Then, a voltage drop exists between the P+ lead-out region 1 and the N-well region, and vertically, the PNP structure Q... PNP When the circuit is turned on, the input voltage Vin leaks directly to the P-type substrate Psub (i.e., ground GND); subsequently, the current on the P-type substrate Psub causes the lateral NPN structure Q to... NPN Conduction, finally the PNP structure Q PNP With NPN structure Q NPN This creates a latch-up loop, resulting in a large leakage current between the input terminal and ground (the leakage current changes from a specification of 20mA to a leakage current exceeding 100mA).

[0030] like Figures 4A-4B As shown, this embodiment provides a breakdown voltage detection device, including an NMOS transistor under test. The NMOS transistor under test includes a first well region 11 and a second well region 12 disposed in a substrate 10. The first well region 11 is provided with a first doped region 13 and a lead-out region 14. The second well region 12 is provided with a second doped region 15. A gate structure 20 is disposed on the substrate 10 at the junction of the first well region 11 and the second well region 12. The first doped region 13 is disposed around the outside of the lead-out region 14. The first doped region 13 and the lead-out region 14 are in contact. A metal silicide layer 18 is disposed on the first doped region 13 and the second doped region 15. A metal interconnect structure is disposed on the substrate 10. The metal silicide layer 18 and the lead-out region 14 are in contact with the metal interconnect structure.

[0031] The first well region 11, the first doped region 13, and the second doped region 15 are all doped with N-type ions, and the second well region 12, the lead-out region 14, and the substrate 10 are all doped with P-type ions.

[0032] In this embodiment, the lead-out region 14 is not covered by the metal silicide layer 18 and directly contacts the metal interconnect structure, which increases the resistance of the lead-out region 14 and reduces the voltage of the lead-out region 14. This ensures that the longitudinal PNP structure QPNP in the latch-up circuit is always in the off state, thus avoiding the generation of latch-up circuit and leakage path, thereby solving the large leakage phenomenon and ensuring the normal mass production of PMIC products.

[0033] Detailed, such as Figure 1 As shown, the breakdown voltage detection device includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, and a fifth transistor. The first transistor Q1 and the second transistor Q2 are both PMOS transistors, and the third transistor Q3, the fourth transistor Q4, and the fifth transistor are all NMOS transistors. The third transistor Q3 is the NMOS transistor to be tested.

[0034] One terminal of the first transistor Q1 and one terminal of the second transistor Q2 are simultaneously connected to the power supply VCC. The other terminal of the first transistor Q1 is connected to one terminal of the third transistor Q3, one terminal of the fourth transistor Q4, and the input terminal. The input terminal is connected to the input voltage. The gate terminal of the first transistor Q1 is simultaneously connected to the other terminal of the second transistor Q2, the gate terminal of the third transistor Q3, and one terminal of the fifth transistor. The gate terminal of the second transistor Q2 is connected to the gate voltage source and is also connected to the gate terminal Vg of the fifth transistor. The other terminal of the fourth transistor Q4, the other terminal of the third transistor Q3, the substrate 10 of the third transistor Q3, and the other terminal of the fifth transistor are all grounded to GND.

[0035] In this configuration, one connection terminal of the first transistor Q1 can be a drain region and the other connection terminal can be a source region; or, one connection terminal of the first transistor Q1 can be a source region and the other connection terminal can be a drain region. Similarly, one connection terminal of the second transistor Q2 can be a drain region and the other connection terminal can be a source region; or, one connection terminal of the second transistor Q2 can be a source region and the other connection terminal can be a drain region.

[0036] One connection terminal of the third transistor Q3, one connection terminal of the fourth transistor Q4, and one connection terminal of the fifth transistor are all drain regions; the other connection terminal of the third transistor Q3, the other connection terminal of the fourth transistor Q4, and the other connection terminal of the fifth transistor are all source regions.

[0037] like Figure 4AAs shown, the NMOS transistor under test includes a substrate 10, in which a first well region 11 and a second well region 12 are disposed adjacently and in contact. The first well region 11 and the second well region 12 both extend from one side surface of the substrate 10 into the substrate 10. The substrate 10 is a P-type substrate 10. The first well region 11 is doped with N-type ions, and the second well region 12 is doped with P-type ions.

[0038] A shallow trench isolation structure is provided in the first well region 11. The shallow trench isolation structure defines a first doped region 13, that is, the shallow trench structure is a ring structure. In the substrate 10 inside the shallow trench structure, the first doped region 13 and the lead-out region 14 are arranged sequentially from the outside to the inside. The first doped region 13 is doped with N-type ions, and the lead-out region 14 is doped with P-type ions.

[0039] The second well region 12 is provided with a second doped region 15 and a body region 16, which are spaced apart, with the second doped region 15 located between the first doped region 13 and the body region 16. The second doped region 15 is doped with N-type ions, and the body region 16 is doped with P-type ions.

[0040] A metal silicide layer 18 is disposed on the surface of the substrate 10. The metal silicide layer 18 covers the first doped region 13 and the second doped region 15. That is, in the first well region 11, the metal silicide layer 18 covers the first doped region 13 and exposes the lead-out region 14. In the second well region 12, the metal silicide layer 18 covers the second doped region 15 and exposes the body region 16.

[0041] The metal silicide layer 18 is, for example, a silicon-cobalt compound layer. In the first well region 11, the surface of the lead-out region 14 is higher than the surface of the first doped region 13, and the surface of the lead-out region 14 is flush with the metal silicide layer 18 on the first doped region 13.

[0042] The substrate 10 is further provided with a gate structure 20, which is located at the junction of the first well region 11 and the second well region 12, such that the gate structure 20 covers part of the first well region 11, part of the second well region 12 and part of the shallow trench isolation structure near the side of the second well region 12.

[0043] The substrate 10 surface is further provided with a metal interconnect structure, which includes a first conductive pillar 31 and a second conductive pillar 32. The first conductive pillar 31 is in contact with both the metal silicide layer 18 of the first well region 11 and the lead-out region 14, so that the input terminal is electrically connected to the first doped region 13 and the lead-out region 14 (that is, one connection terminal of the third transistor Q3 in the breakdown voltage detection circuit) in the NMOS transistor under test through the first conductive pillar 31. The second conductive pillar 32 is connected to the metal silicide layer 18 of the second well region 12, so that ground GND is electrically connected to the second doped region 15 (that is, the other connection terminal of the third transistor Q3 in the breakdown voltage detection circuit) in the NMOS transistor under test through the second conductive pillar 32.

[0044] In the prior art, both the lead-out region 14 and the first doped region 13 are covered with metal silicide, and the metal interconnect structure is connected through the metal silicide. For example... Figures 3A-3B As shown, when the input voltage Vin (e.g., 5V) is greater than the source voltage VCC, the voltage of the P+ lead-out region 141 and the voltage of the N-well region Nwell are both 5V, and the P-type substrate 10Psub is grounded. At this point, the silicon-cobalt compound on the voltage surface of the P+ lead-out region 141 in block diagram A has a voltage drop of U1 (e.g., 1V), and the silicon-cobalt compound on the surface of the N+ doped region surrounding the P+ lead-out region 141 also has a voltage drop of U1 (e.g., 1V). The voltage at the P+ lead-out region 141 is Vin-U1 (e.g., 4V), and the voltage at the N-well region is also Vin-U1 (e.g., 4V). Since the conductive channel of transistor Q3 is formed, the conductive channel voltage drop is U0 (e.g., 1V), which causes the N-well voltage to decrease, from U2 to Vin-U1-U0 (e.g., 3V). Thus, the voltage drop between the P+ lead-out region 141 and the N-well region is greater than 0V (e.g., from 4V to 3V), causing the PN junction formed by the P+ lead-out region 141 and the N-well region to be forward biased. Therefore, the vertical PNP structure Q... PNP The conduction caused a leakage path between the input terminal and body region 16 (i.e., ground GND), resulting in a large leakage current between the input terminal and ground GND.

[0045] like Figures 4A-4BAs shown, in the NMOS transistor under test in this embodiment, when the input voltage Vin (e.g., 5V) is greater than the source voltage VCC, the voltages of the lead-out region 14 and the first doped region 13 are the same and both Vin, and the substrate 10 is grounded. At this time, in block diagram B, the metal silicide on the surface of the first doped region 13 has a voltage drop U1 (e.g., 1V); since the surface of the lead-out region 14 is not covered by metal silicide, this increases the resistance R of the lead-out region 14, making the metal silicide voltage drop U1 on the surface of the first doped region 13 less than the voltage drop U11 (e.g., 2V) of the lead-out region 14, i.e., U11 > U1. Thus, the voltage at the lead-out region 14 drops from Vin to Vin-U11 (e.g., 3V), and the voltage of the first well region 11 is also Vin-U11. 1 (e.g., 4V), which makes the voltage drop between the lead-out region 14 and the first well region 11 less than 0V (e.g., from 3V to 4V, i.e., -1V). This prevents the PN junction between the lead-out region 14 and the first well region 11 from being forward biased due to the voltage division of the conductive channel in the NMOS transistor under test. Therefore, the vertical PNP structure QPNP forming the latch-up circuit is always in the off state, thereby avoiding the generation of latch-up circuit and leakage path, thus solving the large leakage phenomenon and ensuring the normal mass production of PMIC products.

[0046] In summary, this invention provides a breakdown voltage detection device, including an NMOS transistor under test. The NMOS transistor under test includes a first well region and a second well region disposed in a substrate. The first well region contains a first doped region and a lead-out region, and the second well region contains a second doped region. A gate structure is disposed on the substrate at the junction of the first and second well regions. The first doped region is arranged around the outside of the lead-out region, and the first doped region and the lead-out region are in contact. A metal silicide layer is disposed on the first and second doped regions. A metal interconnect structure is disposed on the substrate, and the metal silicide layer and the lead-out region are in contact with the metal interconnect structure. This invention increases the resistance of the lead-out region and reduces its voltage by ensuring that the vertical PNP structure QPNP in the latch-up circuit remains in the off state. This avoids the generation of latch-up circuits and leakage paths, thus solving the problem of large leakage and ensuring the normal mass production of PMIC products.

[0047] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0048] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the present invention without departing from the scope of the present invention, or equivalent embodiments can be modified based on the disclosed technical content. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A breakdown voltage detecting device, characterized by comprising: The device comprises a to-be-tested NMOS transistor, which comprises a first well region and a second well region arranged in a substrate, a first doped region and a lead-out region arranged in the first well region, a second doped region arranged in the second well region, a gate structure arranged on the substrate at the junction of the first well region and the second well region, the first doped region being arranged outside the lead-out region, the first doped region and the lead-out region being in contact, and a metal silicide layer arranged on the first doped region and the second doped region, a metal interconnection structure arranged on the substrate, and the metal silicide layer and the lead-out region being in contact with the metal interconnection structure.

2. The breakdown voltage detecting apparatus according to claim 1, wherein The first well region, the first doped region and the second doped region are doped with N-type ions, and the second well region, the lead-out region and the substrate are doped with P-type ions.

3. The breakdown voltage detecting apparatus according to claim 1, wherein The first well region is provided with a shallow trench isolation structure, the shallow trench isolation structure defining the first doped region, and the first doped region and the lead-out region being arranged in the substrate inside the shallow trench isolation structure from outside to inside.

4. The breakdown voltage detecting apparatus according to claim 1, wherein The second well region is provided with a body region, the second doped region and the body region being arranged separately, and the second doped region being located between the first doped region and the body region; wherein the body region is doped with P-type ions.

5. The breakdown voltage detecting apparatus according to claim 4, wherein In the first well region, the metal silicide layer covers the first doped region and exposes the lead-out region; in the second well region, the metal silicide layer covers the second doped region and exposes the body region.

6. The breakdown voltage detecting apparatus according to claim 1, wherein The surface of the lead-out region is higher than the surface of the first doped region, and the surface of the lead-out region is flush with the surface of the metal silicide layer in the first well region.

7. The breakdown voltage detecting apparatus according to claim 6, wherein The substrate is further provided with a metal interconnection structure, the metal interconnection structure comprising a first conductive column and a second conductive column, the first conductive column being in contact with the metal silicide layer of the first well region and the lead-out region at the same time, and the second conductive column connecting the metal silicide layer of the second well region.

8. The breakdown voltage detecting apparatus according to claim 1, wherein The breakdown voltage detection device comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor, the first transistor and the second transistor are PMOS transistors, the third transistor, the fourth transistor and the fifth transistor are NMOS transistors, and the third transistor is a to-be-tested NMOS transistor. One connection end of the first transistor and one connection end of the second transistor are connected to a power supply VCC at the same time, another connection end of the first transistor is connected to one connection end of the third transistor, one connection end of the fourth transistor and an input end, the input end is connected to an input voltage, a gate end of the first transistor is connected to another connection end of the second transistor, a gate end of the third transistor and one connection end of the fifth transistor at the same time, a gate end of the second transistor is connected to a gate voltage source and a gate end of the fifth transistor at the same time, another connection end of the fourth transistor, another connection end of the third transistor, a substrate of the third transistor and another connection end of the fifth transistor are all grounded.

9. The breakdown voltage detecting apparatus according to claim 8, wherein One connection terminal of the first transistor is a drain region, and the other connection terminal is a source region; or, one connection terminal of the first transistor is a source region, and the other connection terminal is a drain region. One connection terminal of the second transistor is a drain region, and the other connection terminal is a source region; or, one connection terminal of the second transistor is a source region, and the other connection terminal is a drain region.

10. The breakdown voltage detecting apparatus according to claim 8, wherein One connection terminal of the third transistor, one connection terminal of the fourth transistor and one connection terminal of the fifth transistor are all drain regions; the other connection terminal of the third transistor, the other connection terminal of the fourth transistor and the other connection terminal of the fifth transistor are all source regions.

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