TO247 packaging structure

By increasing the size of the drain and source pins in the TO-247 package structure, the problems of overheating and solder melt-off in power transistors were solved, improving current carrying capacity and reliability.

CN223979109UActive Publication Date: 2026-03-06GUANGDONG CHIPPACKING TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-03-24
Publication Date
2026-03-06

AI Technical Summary

Technical Problem

TO-247 packaged power transistors have overheating issues in some applications, especially the D pin, which gets too hot and causes solder melt.

Method used

By increasing the dimensions of the D and S pins of the lead frame, making their shoulder length and width larger than those of the G pin, the area is increased to improve current carrying capacity and reduce pin heating.

Benefits of technology

It effectively prevents overheating of the D and S pins, avoids the problem of molten solder and desoldering, and improves the reliability of the package structure.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model provides a TO-247 packaging structure, which comprises a lead frame base island, a lead frame D-pole pin arranged on one side of the lead frame base island, and a lead frame G-pole pin and a lead frame S-pole pin which are respectively arranged on two sides of the lead frame D-pole pin, the lengths of the lead frame D-pole pin, the lead frame G-pole pin and the lead frame S-pole pin are equal, each of the lead frame D-pole pin, the lead frame G-pole pin and the lead frame S-pole pin comprises a shoulder part adjacent to the lead frame base island and a foot part adjacent to the shoulder part, and the length of the shoulder part of the lead frame D-pole pin is equal to the length of the shoulder part of the lead frame S-pole pin. And the lengths of the shoulder parts of the G-pole pins of the lead frame are greater than those of the shoulder parts. According to the TO-247 packaging structure provided by the utility model, the heating of the pins can be reduced.
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Description

Technical Field

[0001] This utility model relates to the field of integrated circuit packaging, specifically a TO247 package structure that can reduce pin heat generation. Background Technology

[0002] The TO-247 package is a common high-power transistor package, widely used in high-power electronic devices due to its excellent heat dissipation and electrical performance. TO-247 packaged power transistors typically have three pins: gate (G), drain (D), and source (S).

[0003] like Figure 1 As shown, the middle pin (D pin) of the power semiconductor using the TO-247 package is designed to be wider at the top (3.0mm) and narrower at the bottom (1.2mm). When mounted on the circuit board, overheating issues have occurred in some application scenarios. In some cases, the temperature of the D pin exceeded 230 degrees Celsius during on-machine testing, resulting in solder melting. Utility Model Content

[0004] The purpose of this invention is to provide a TO247 package structure that can reduce pin heating.

[0005] In this embodiment of the present invention, a TO-247 package structure is provided, which includes a leadframe base island, a leadframe D-pin disposed on one side of the leadframe base island, and leadframe G-pins and leadframe S-pins disposed on both sides of the leadframe D-pin. The leadframe D-pin, the leadframe G-pin, and the leadframe S-pin are of equal length and each includes a shoulder adjacent to the leadframe base island and a foot adjacent to the shoulder. The shoulder length of the leadframe D-pin is equal to the shoulder length of the leadframe S-pin and is greater than the shoulder length of the leadframe G-pin.

[0006] In this embodiment of the invention, the shoulder width of the D-pin of the lead frame and the shoulder width of the S-pin of the lead frame are greater than the shoulder width of the G-pin of the lead frame.

[0007] In this embodiment of the present invention, the width of the lead frame D-pin and the lead frame S-pin is 2.0mm-3.0mm.

[0008] In this embodiment of the invention, the shoulder length of the D-pin and S-pin of the lead frame is 5.0mm-17.0mm.

[0009] In this embodiment of the invention, the shoulder length of the D-pin and the S-pin of the lead frame is 11.0 mm.

[0010] Compared with the prior art, the TO-247 package structure of this utility model increases the size of the lead frame drain (D) pin and lead frame source (S) pin, thereby increasing its ability to carry large currents and preventing the problem of overheating and solder meltdown of the drain (D) and source (S) pins of power semiconductors using the TO-247 package structure. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a planar structure of a power semiconductor in a prior art TO-247 package.

[0012] Figure 2 This is a schematic diagram of the planar structure of a power semiconductor using the TO-247 package structure of this utility model embodiment.

[0013] Figure 3 This is a schematic diagram of a power semiconductor using the TO-247 package structure of this utility model mounted on a circuit board.

[0014] Figure 4 This is a schematic diagram of the lead frame structure for implementing the TO-247 package structure of this utility model embodiment. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0016] The implementation of this utility model will be described in detail below with reference to specific embodiments.

[0017] like Figure 2 As shown in the embodiment of this utility model, a TO-247 package structure is provided, which includes a leadframe base island 1, a leadframe drain pin 2 disposed on one side of the leadframe base island 1, and leadframe gate pins 3 and sinker pins 4 disposed on both sides of the leadframe drain pin 2. The leadframe drain pin 2, the leadframe gate pin 3, and the leadframe sinker pin 4 are of equal length and each includes a shoulder 5 adjacent to the leadframe base island 1 and a foot 6 adjacent to the shoulder. The shoulder length of the leadframe drain pin 2 and the shoulder length of the leadframe sinker pin 4 are equal and both are greater than the shoulder length of the leadframe gate pin 3, thereby increasing the area of ​​the leadframe drain pin 2 and the leadframe sinker pin 4, improving their current carrying capacity, and reducing pin heat generation.

[0018] Specifically, in this embodiment of the invention, the shoulder length of the lead frame D-pin 2 and the lead frame S-pin 4 is 5.0mm-17.0mm. Preferably, the shoulder length of the lead frame D-pin 2 and the lead frame S-pin 4 is 11.0mm.

[0019] Furthermore, in order to increase the area of ​​the D-pin 2 and the S-pin 4 of the lead frame, in this embodiment of the invention, the shoulder width of the D-pin and the S-pin of the lead frame is increased to be greater than the shoulder width of the G-pin of the lead frame.

[0020] Furthermore, in order to increase the area of ​​the lead frame D-pin 2 and the lead frame S-pin 4, the width of the lead frame D-pin 2 and the lead frame S-pin 4 is increased from the traditional 1.2mm to 2.0mm-3.0mm.

[0021] The connection method between the power semiconductor and the PCB board using the TO-247 package structure of this utility model embodiment is as follows: Figure 3 As shown.

[0022] The lead frame for implementing the TO-247 package structure of this utility model embodiment is as follows: Figure 4 As shown.

[0023] In summary, by increasing the size of the lead frame drain (D) and source (S) pins, the TO-247 package structure of this invention increases the capacity to carry large currents and prevents overheating of the D and S pins of power semiconductors using the TO-247 package structure, which could lead to solder melt and desoldering.

[0024] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A TO-247 package structure, characterized by, The lead frame base island, the lead frame D pole pin arranged on one side of the lead frame base island, the lead frame G pole pin and the lead frame S pole pin arranged on both sides of the lead frame D pole pin respectively, the length of the lead frame D pole pin, the lead frame G pole pin and the lead frame S pole pin are equal, and all include a shoulder part adjacent to the lead frame base island and a foot part adjacent to the shoulder part, the shoulder part length of the lead frame D pole pin is equal to the shoulder part length of the lead frame S pole pin, and both are greater than the shoulder part length of the lead frame G pole pin.

2. The TO-247 package structure of claim 1, wherein, The shoulder part width of the lead frame D pole pin and the lead frame S pole pin is greater than the shoulder part width of the lead frame G pole pin.

3. The TO-247 package structure of claim 2, wherein, The foot part width of the lead frame D pole pin and the lead frame S pole pin is 2.0mm-3.0mm.

4. The TO-247 package structure of claim 1, wherein, The shoulder part length of the lead frame D pole pin and the lead frame S pole pin is 5.0mm-17.0mm.

5. The TO-247 package structure of claim 1, wherein, The shoulder part length of the lead frame D pole pin and the lead frame S pole pin is 11.0mm.