Semiconductor package structure and wafer level semiconductor structure

Abstract

An exemplary semiconductor package structure may include a first redistribution layer and a first semiconductor die attached to the first redistribution layer. The first semiconductor die may include a first front-side electrical contact and a first back-side electrical contact such that the first front-side electrical contact is electrically connected to the first redistribution layer. The semiconductor package structure may also include a second redistribution layer formed over the first semiconductor die such that the second redistribution layer is electrically connected to a first backside electrical contact of the first semiconductor die and a second semiconductor die attached to the second redistribution layer and vertically positioned over the first semiconductor die. The first semiconductor die may include at least two alignment marks spaced at least 50 microns. A coverage error between the alignment of the first semiconductor die and the second redistribution layer may be less than or equal to 0.5 microns.

Description

Technical Field

[0001] This utility model relates to a semiconductor packaging structure, a wafer-level semiconductor structure, and a method for forming the same. Background Technology

[0002] Semiconductor devices are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography and etching to pattern these material layers to form circuit elements and their components. Tens, hundreds, or thousands of integrated circuits are typically fabricated on a single semiconductor wafer. The individual dies on the wafer can be separated by sawing along dicing lines between the integrated circuits. For example, individual dies are often individually packaged in multi-chip modules or other types of packages.

[0003] As semiconductor packaging becomes more complex, package sizes tend to increase to accommodate a greater number of integrated circuits and / or each package die. These larger, more complex semiconductor packages present challenges for efficient and reliable interconnection between the various components within the package. Therefore, there is an ongoing need to improve semiconductor package design, focusing on reducing interconnect lengths to minimize ohmic losses, heat generation, and signal delay. One promising approach involves forming semiconductor packages through vertically stacked semiconductor dies. The semiconductor dies may include alignment marks, which allow for improved precision placement of the semiconductor dies and redistribution layers within the semiconductor package during stacking. Utility Model Content

[0004] According to some embodiments of this disclosure, a semiconductor package structure is provided. The semiconductor package structure may include a first redistribution layer and a first semiconductor die attached to the first redistribution layer. The first semiconductor die may include a first front-side electrical contact and a first back-side electrical contact, such that the first front-side electrical contact is electrically connected to the first redistribution layer. The semiconductor package structure may further include a second redistribution layer formed above the first semiconductor die, such that the second redistribution layer is electrically connected to the first back-side electrical contact of the first semiconductor die. The semiconductor package structure may further include a second semiconductor die attached to the second redistribution layer and vertically positioned above the first semiconductor die. According to various embodiments, the first semiconductor die may further include at least two alignment marks spaced at least 50 micrometers apart.

[0005] According to some embodiments of this disclosure, a wafer-level semiconductor structure is provided. The wafer-level semiconductor structure may include a first redistribution layer formed over a wafer having a first plurality of repeating units spatially staggered from each other. The wafer-level semiconductor structure may also include a first semiconductor die and a second semiconductor die electrically coupled to the first redistribution layer over each of the first plurality of repeating units, and a second redistribution layer formed over and electrically coupled to the first semiconductor die and the second semiconductor die. The second redistribution layer may include a second plurality of repeating units spatially staggered from each other, and each of the second plurality of repeating units may be spatially aligned with a corresponding region associated with the first semiconductor die and the second semiconductor die such that a coverage error is less than or equal to 0.5 micrometers.

[0006] According to some embodiments of this disclosure, a method for forming a wafer-level semiconductor structure is provided. This method includes: forming a first redistribution layer over a wafer, such that the first redistribution layer includes a first plurality of repeating units spatially offset from each other; attaching a first semiconductor die and a second semiconductor die to the first redistribution layer over each of the first plurality of repeating units, such that each of the first semiconductor die and the second semiconductor die is electrically coupled to the first redistribution layer; measuring the spatial position and orientation of a first alignment mark formed on the first semiconductor die and a second alignment mark formed on the second semiconductor die; determining the spatial position and orientation of corresponding regions associated with the first semiconductor die and the second semiconductor die based on the spatial position and orientation of the first alignment mark and the second alignment mark; and forming a second redistribution layer over the first semiconductor die and the second semiconductor die and electrically connected to the first semiconductor die.

[0007] The second semiconductor die is formed by performing the following operations: forming a second plurality of repeating units spatially offset from each other, each of the second plurality of repeating units including a redistribution layer electrical connection; spatially aligning each of the second plurality of repeating units with the corresponding regions associated with the first semiconductor die and the second semiconductor die based on the spatial position and orientation of the corresponding regions associated with the first semiconductor die and the second semiconductor die; and electrically connecting the redistribution layer to semiconductor die electrical connections formed on the first semiconductor die and the second semiconductor die.

[0008] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0009] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0010] Figure 1 This is a vertical cross-sectional view of a semiconductor package structure according to various embodiments.

[0011] Figure 2A This is a vertical cross-sectional view of an intermediate structure after the formation of a complementary metal-oxide-semiconductor (CMOS) transistor, a metal interconnect structure, and a dielectric material layer, according to various embodiments.

[0012] Figure 2B This is a vertical cross-sectional view of another intermediate structure during the formation of the front interconnect structure according to various embodiments.

[0013] Figure 3A This is a vertical cross-sectional view of an intermediate structure that can be used to form a device on a semiconductor wafer according to various embodiments.

[0014] Figure 3B This is a vertical cross-sectional view of another intermediate structure that can be used to form a device on a semiconductor wafer according to various embodiments.

[0015] Figure 3C This is a vertical cross-sectional view of another intermediate structure that can be used to form a device on a semiconductor wafer according to various embodiments.

[0016] Figure 3D This is a vertical cross-sectional view of another intermediate structure that can be used to form a device on a semiconductor wafer according to various embodiments.

[0017] Figure 4A This is a vertical cross-sectional view of an intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0018] Figure 4B This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0019] Figure 4C This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0020] Figure 4D This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0021] Figure 4E This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0022] Figure 4F This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0023] Figure 4G This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0024] Figure 4H This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0025] Figure 4I This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0026] Figure 4J This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0027] Figure 4K This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0028] Figure 4L This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0029] Figure 4M This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0030] Figure 4N This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package structure according to various embodiments.

[0031] Figure 5A This is a top view of a wafer-level structure that can be used to form multiple semiconductor package structures according to various embodiments.

[0032] Figure 5B This is a top view of another wafer-level structure that can be used to form multiple semiconductor package structures according to various embodiments.

[0033] Figure 5C This is a top view of another wafer-level structure illustrating placement errors according to various embodiments.

[0034] Figure 5D According to various embodiments Figure 5C An enlarged top view of a portion of the wafer-level structure.

[0035] Figure 5EThis is a top view of another wafer-level structure, according to various embodiments, that can be used to form multiple semiconductor package structures.

[0036] Figure 5F According to various embodiments Figure 5E A magnified top view of a portion of the wafer-level structure.

[0037] Figure 6A This is a top view of a configuration of a semiconductor die including back-side electrical contacts and alignment marks, according to various embodiments.

[0038] Figure 6B This is a top view of another configuration including two semiconductor dies according to various embodiments, each semiconductor die having a back-side electrical contact and alignment marks.

[0039] Figure 6C This is a top view of another configuration including three semiconductor dies according to various embodiments, each semiconductor die having a back-side electrical contact and alignment marks.

[0040] Figure 7A This is a vertical cross-sectional view of a semiconductor die including back-side electrical contacts and alignment marks according to various embodiments.

[0041] Figure 7B According to various embodiments Figure 7A A vertical cross-sectional view of a portion of a semiconductor die, showing details of the alignment marks.

[0042] Figure 8A This is a top view of alignment marks formed by multiple through-hole structures according to various embodiments.

[0043] Figure 8B This is a top view of another alignment mark formed by a plurality of through-hole structures according to various embodiments.

[0044] Figure 8C This is a top view of another alignment mark formed by a plurality of through-hole structures according to various embodiments.

[0045] Figure 8D This is a top view of another alignment mark formed by a plurality of through-hole structures according to various embodiments.

[0046] Figure 8E This is a top view of another alignment mark formed by a plurality of through-hole structures according to various embodiments.

[0047] Figure 8F This is a top view of another alignment mark formed by a plurality of through-hole structures according to various embodiments.

[0048] Figure 9This is a flowchart illustrating the operation of a method for forming a wafer-level semiconductor structure according to various embodiments.

[0049] Explanation of reference numerals in the attached figures

[0050] 8: Semiconductor substrate

[0051] 10: Semiconductor material layer

[0052] 11: Doped semiconductor material layer

[0053] 12: Shallow trench isolation structure

[0054] 13: Fin Structure

[0055] 14: Source / Drain Region

[0056] 15: Semiconductor Channel

[0057] 18: Metal-semiconductor alloy region

[0058] 20: Gate structure

[0059] 22: Gate Dielectric

[0060] 24: Gate electrode

[0061] 26: Dielectric gate spacer

[0062] 28: Gate cap dielectric

[0063] 31A: Planarized dielectric layer

[0064] 31B: First ILD layer

[0065] 32: Second ILD layer

[0066] 33: Third ILD layer

[0067] 41L: First metal wire

[0068] 42L: Second metal wire

[0069] 50: Device Area

[0070] 52: Surrounding Logic Area

[0071] 75: CMOS Circuit

[0072] 95: BEOL devices

[0073] 100: Semiconductor Packaging Structure

[0074] 102a: First redistribution layer

[0075] 102b: Second redistribution layer

[0076] 104a: First Semiconductor Die

[0077] 104b: Second semiconductor die

[0078] 104c, 105a: Third semiconductor die

[0079] 105b: Fourth Semiconductor Die

[0080] 105c: The fifth semiconductor die

[0081] 106: Front electrical contacts

[0082] 108: Rear side electrical contacts

[0083] 110: Top side electrical contact

[0084] 112: Bottom side electrical contact

[0085] 116: Bottom filling material

[0086] 118: Through-hole structure

[0087] 119: Through-hole structure, back-side floating through-hole, copper through-hole, silicon via

[0088] 120, 120a, 120b, 120c, 120d, 120e, 120f: Alignment markers

[0089] 140a: First molding material

[0090] 140b: Second molding material

[0091] 142: Perforation of molding material

[0092] 200a, 200b, 300a, 300b, 300c, 300d, 400a, 400b, 400c, 400d, 400e, 400f, 400g, 400h, 400i, 400l, 400m, 400n: intermediate structures

[0093] 301: Transistor Structure

[0094] 304L: Additional metal wire

[0095] 310L: First back side metal wire

[0096] 312: First back-side metallization layer

[0097] 401: Electrical interconnect structure

[0098] 402: Chip

[0099] 402a: First chip

[0100] 402b: Second chip

[0101] 404: Adhesive layer

[0102] 406: Solder Material Section

[0103] 408: Dielectric layer

[0104] 500a, 500b, 500c, 500e: Chip-level structure

[0105] 502a, 502b: Repeating units

[0106] 504a: Respective region

[0107] 504a1, 504a2: Zone 1

[0108] 504b: Second Region

[0109] 600a: First Configuration

[0110] 600b: Second Configuration

[0111] 600c: Third Configuration

[0112] 702: Alignment mark surface

[0113] 704: Interface

[0114] 706: Distance of indentation

[0115] 802: Mirror-symmetric plane

[0116] 900: Method

[0117] 902, 904, 906, 908, 910: Operation

[0118] L0: Contact hierarchy

[0119] L1: First interconnection layer structure

[0120] L2: Second interconnection layer structure

[0121] L3: Third interconnection layer structure

[0122] M1: First metal layer

[0123] V1: First through-hole layer Detailed Implementation

[0124] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these elements and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0125] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly. Unless otherwise expressly stated, each element having the same reference numerals is assumed to have the same material composition and thickness within the same thickness range.

[0126] The various embodiments disclosed herein can be advantageous by providing systems and methods for improving the placement accuracy of various components (e.g., semiconductor dies) in a semiconductor package. In this regard, the semiconductor package can be formed by attaching a semiconductor die onto a first redistribution layer and forming a second redistribution layer over the semiconductor die. Exemplary systems and methods provide alignment marks with detailed features, which allow for precise measurement of placement errors of the semiconductor die. Such measurements can then be used to adjust the features of the second redistribution layer to correct for semiconductor die placement errors.

[0127] An exemplary semiconductor package structure may include a first redistribution layer and a first semiconductor die attached to the first redistribution layer. The first semiconductor die may include a first front-side electrical contact and a first back-side electrical contact, such that the first front-side electrical contact is electrically connected to the first redistribution layer. The semiconductor package structure may further include a second redistribution layer formed above the first semiconductor die, such that the second redistribution layer is electrically connected to the first back-side electrical contact of the first semiconductor die and electrically connected to a second semiconductor die attached to the second redistribution layer and vertically positioned above the first semiconductor die. The first semiconductor die may include at least two alignment marks spaced at least 50 micrometers apart. The overlay error between the alignments of the first semiconductor die and the second redistribution layer may be less than or equal to 0.5 micrometers.

[0128] An exemplary wafer-level semiconductor structure may include a first redistribution layer formed over a wafer, such that the first redistribution layer includes a first plurality of repeating units spatially staggered from each other. The wafer-level semiconductor structure may also include a first semiconductor die and a second semiconductor die electrically coupled to the first redistribution layer over each of the first plurality of repeating units, and a second redistribution layer formed over and electrically coupled to the first and second semiconductor dies. The second redistribution layer may include a second plurality of repeating units spatially staggered from each other. Furthermore, each of the second plurality of repeating units may be spatially aligned with a corresponding region associated with the first and second semiconductor dies, such that a coverage error is less than or equal to 0.5 micrometers.

[0129] An exemplary method of forming a wafer-level semiconductor structure may include forming a first redistribution layer over a wafer, such that the first redistribution layer includes a first plurality of repeating units spatially offset from each other. The method may further include attaching a first semiconductor die and a second semiconductor die to the first redistribution layer over each of the first plurality of repeating units, such that each of the first semiconductor die and the second semiconductor die is electrically coupled to the first redistribution layer. The method may further include measuring the spatial position and orientation of a first alignment mark formed on the first semiconductor die and a second alignment mark formed on the second semiconductor die, and determining the spatial position and orientation of corresponding regions associated with the first semiconductor die and the second semiconductor die based on the spatial position and orientation of the first alignment mark and the second alignment mark. The method may further include forming a second redistribution layer over the first semiconductor die and the second semiconductor die and electrically connecting it to the first semiconductor die and the second semiconductor die by performing various additional operations.

[0130] Additional operations may include forming a second plurality of repeating units spatially offset from each other, each of which includes a redistribution layer electrical connection. The method may also include spatially aligning each of the second plurality of repeating units with a corresponding region associated with the first and second semiconductor dies based on the spatial location and orientation of the corresponding regions associated with the first and second semiconductor dies. The method may also include electrically connecting the redistribution layer to semiconductor die electrical connections formed on the first and second semiconductor dies.

[0131] As used herein, a “back-end-of-line” element or “BEOL” element refers to any element formed at a contact layer or metal interconnect layer. A “metal interconnect level” refers to a layer through which a metal interconnect structure, such as a metal wire or metal via, extends vertically. As used herein, a “front-end-of-line” element or “FEOL” element refers to any element formed before the formation of any contact level structure if a contact level structure is subsequently formed, or any element formed without the formation of a contact level structure or any metal interconnect structure (i.e., without the subsequent formation of any contact level structure or any metal interconnect structure).

[0132] Generally, an FEOL element refers to a semiconductor device element that can be formed during a CMOS process prior to the formation of any via structures on the nodes of field-effect transistors (FETs), while a BEOL element refers to a semiconductor device element that can be formed during the earliest via process or subsequent CMOS processes for forming any via structures on the nodes of FETs. In any embodiment where exemplary manufacturing steps are integrated into a CMOS manufacturing process, an element formed prior to the formation of any via structures on the nodes of FETs can be referred to as an FEOL element, and an element formed during or after the earliest via process for forming via structures on the nodes of FETs can be referred to as a BEOL element.

[0133] Generally, FEOL devices can be formed within, directly on, or indirectly on a semiconductor substrate without any metal interconnect structure between the semiconductor substrate and the device. Examples of FEOL devices include planar field-effect transistors, fin field-effect transistors (FinFETs), gate-around field-effect transistors, and any device element that includes a portion of the semiconductor substrate (whose lateral extent is larger than the lateral extent of the corresponding device element). Typically, for each FEOL device, no metal interconnect structure extends vertically from a first horizontal plane including the top surface of the FEOL device to a second horizontal plane including the bottom surface of the FEOL device, or the FEOL device is laterally surrounded or contacted by a semiconductor material layer having a lateral extent larger than that of the FEOL device.

[0134] Examples of BEOL devices may include any dielectric material layer in which metal via structures or metal wire structures are formed, any metal interconnect structure, memory cells formed without using any portion of a semiconductor substrate, selector cell semiconductor substrates formed without using any portion of a semiconductor substrate, thin film transistors formed without using any portion of a semiconductor substrate (but may include patterned semiconductor material portions having a lateral extent not exceeding that of a single thin film transistor or a merged thin film transistor cluster), and pads. Typically, for each BEOL device, at least one metal interconnect structure extends vertically from a first horizontal plane including the top surface of the BEOL device to a second horizontal plane including the bottom surface of the BEOL device, and the BEOL device is not laterally surrounded by or in contact with a semiconductor material layer having a lateral extent larger than that of the BEOL device.

[0135] Figure 1 This is a vertical cross-sectional view of a semiconductor package structure 100 according to various embodiments. See below for reference. Figures 4A to 5F In more detail, the semiconductor package structure 100 can be formed by performing a wafer-level process, wherein multiple similar semiconductor package structures 100 can be formed on a wafer. The wafer can be diced to produce multiple similar semiconductor package structures 100. The semiconductor package structure 100 may include a first redistribution layer 102a and a second redistribution layer 102b.

[0136] The semiconductor package structure 100 may further include a first semiconductor die 104a and a second semiconductor die 104b electrically coupled to the first redistribution layer 102a. See below for reference. Figures 3A to 3DAs described, the first semiconductor die 104a and the second semiconductor die 104b may include a front-side electrical contact 106 and a back-side electrical contact 108. As shown, the front-side electrical contact 106 may be electrically coupled to the first redistribution layer 102a and the back-side electrical contact 108 may be electrically connected to the second redistribution layer 102b.

[0137] The first redistribution layer 102a may include top-side electrical contacts 110 and bottom-side electrical contacts 112. The first dimensions and spacing of the top-side electrical contacts 110 may be smaller than the second dimensions and spacing of the bottom-side electrical contacts 112. Therefore, the first redistribution layer 102a may have a fan-out configuration. In this respect, the first semiconductor die 104a and the second semiconductor die 104b may be formed separately and attached to the first redistribution layer 102a using a flip-chip bonding process. The smaller dimensions and spacing of the top-side electrical contacts 100 can be adapted to the bonding of the front electrical contacts 106 of the first semiconductor die 104a and the second semiconductor die 104b, while the larger dimensions and spacing of the bottom-side electrical contacts 112 can be used to bond the semiconductor package structure 100 to a support structure, such as a printed circuit board (not shown).

[0138] The semiconductor package structure 100 may further include a first molding material 140a formed around the first semiconductor die 104a and the second semiconductor die 104b. The first molding material 140a may be further mechanically attached to the first redistribution layer 102a and the second redistribution layer 102b and may provide mechanical support for the semiconductor package structure 100. Figure 1 As shown, the semiconductor package structure 100 may include through-molding-material vias 142. The through-molding-material vias 142 can provide a direct electrical connection between the first redistribution layer 102a and the second redistribution layer 102b. The through-molding-material vias 142 can be configured as shown in the following reference. Figure 4B A more detailed description of the process is required to form it.

[0139] like Figure 1 As shown, the semiconductor package structure 100 may further include one or more additional semiconductor dies (105a, 105b, 105c) electrically coupled to the second redistribution layer 102b. In this respect, the semiconductor package structure 100 may include a third semiconductor die 105a, a fourth semiconductor die 105b, and a fifth semiconductor die 105c formed on and electrically coupled to the second redistribution layer 102b. Thus, the semiconductor package structure 100 can be configured as a three-dimensional integrated circuit having a plurality of semiconductor dies (104a, 104b, 105a, 105b, 105c) arranged in a vertically stacked structure.

[0140] Various semiconductor dies (104a, 104b, 105a, 105b, 105c) can be configured to provide corresponding functions. For example, according to some embodiments, the first semiconductor die 104a and the second semiconductor die 104b can be logic dies, system-on-chip, etc., providing a first function. Similarly, additional semiconductor dies (105a, 105b, 105c) can provide a second function. In this respect, the additional semiconductor dies (105a, 105b, 105c) can be configured as memory dies. In various embodiments, the additional semiconductor dies (105a, 105b, 105c) can each provide the same function. Alternatively, each of the additional semiconductor dies (105a, 105b, 105c) can provide a different corresponding function (e.g., various levels of memory).

[0141] As shown, each of the additional semiconductor dies (105a, 105b, 105c) may include a front-side electrical contact 106 electrically connected to a top-side electrical contact 110 of the second redistribution layer 102b. In various embodiments, the additional semiconductor dies (105a, 105b, 105c) may be single-sided dies having only the front-side electrical contact 106. In other embodiments, the additional semiconductor dies (105a, 105b, 105c) may also include a back-side electrical contact (not shown) that may allow the additional semiconductor dies (105a, 105b, 105c) to be electrically connected to additional circuitry elements subsequently formed above the additional semiconductor dies (105a, 105b, 105c).

[0142] The semiconductor package structure 100 may further include a second molding material 140b formed around the third semiconductor die 105a, the fourth semiconductor die 105b, and the fifth semiconductor die 105c. The second molding material 140b may be mechanically attached to the second redistribution layer 102b and may provide additional mechanical support for the semiconductor package structure 100. As shown, the semiconductor package structure 100 may further include an underfill material 116 formed in the space between the semiconductor dies (104a, 104b, 105a, 105b, 105c) and the respective surfaces of the first redistribution layer 102a and the second redistribution layer 102b. The underfill material 116 may be formed prior to the formation of the respective first molding material 140a and second molding material 140b, as described in more detail below (e.g., see...). Figure 4E and 4F ).

[0143] Each of the semiconductor dies (104a, 104b, 105a, 105b, 105c) can be attached to the corresponding first redistribution layer 102a and second redistribution layer 102b using a pick-and-place process, as shown in the reference below. Figure 4C and 4D To describe in more detail. Thus, some or all of the semiconductor dies (104a, 104b, 105a, 105b, 105c) may include various alignment marks 120, which can be used for the precise placement of the various semiconductor dies (104a, 104b, 105a, 105b, 105c). For example, the first semiconductor die 104a and the second semiconductor die 104b may each include at least one alignment mark 120, which may be formed as a metal structure within the respective semiconductor substrate 8 of the first semiconductor die 104a and the second semiconductor die 104b, such as... Figure 1 As shown. According to various embodiments, each alignment mark 120 can be formed as a copper via 119 or a silicon via 119 (e.g., see...). Figure 3D and 7B In other embodiments, each alignment mark 120 may include a group of multiple metal structures, as referenced below. Figures 8A to 8F A more detailed description is provided below. Furthermore, each alignment mark 120 may include one or more metallic structures with recessed surfaces, as referenced below. Figure 8A and 8B To describe in more detail.

[0144] As described above, the semiconductor package structure 100 can be formed as one of a plurality of such semiconductor package structures 100 in a wafer-level process. In this regard, the first redistribution layer 102a can be formed on the wafer 402 (e.g., a carrier substrate), as referenced below. Figure 4A Described in more detail. The first redistribution layer 102a may include a first plurality of repeating units spatially displaced from each other above the wafer 402. Each of the first plurality of repeating units 502a may include a first semiconductor die 104a and a second semiconductor die 104b electrically coupled to the first redistribution layer 102a above each of the first plurality of repeating units, for example as Figure 5A and Figure 5B As shown.

[0145] However, due to errors in the pick-and-place process, misalignment may exist between the positions of the first semiconductor die 104a and the second semiconductor die 104b and the positions of the first plurality of repeating units 502a. Such errors can be corrected during the formation of the second redistribution layer 102b using precise measurements of the positions of the first semiconductor die 104a and the second semiconductor die 104b. These precise measurements can be obtained by imaging the positions of the alignment marks 120, as described below. Figure 5E and 5F A more detailed description.

[0146] In this respect, the second redistribution layer 102b can be formed on the first semiconductor die 104a and the second semiconductor die 104b, and can be electrically coupled to the first semiconductor die 104a and the second semiconductor die 104b, such that the second redistribution layer 102b includes a second plurality of repeating units 502b, which are spatially offset from each other and spatially associated with corresponding regions 504a. (See, for example, the first semiconductor die 104a and the second semiconductor die 104b). Figure 5E and 5F (and related descriptions). In some embodiments, the overlay error may be less than or equal to 0.5 micrometers, as described in more detail below. References below Figures 4A to 4N Various processes are described for forming the semiconductor package structure 100.

[0147] Figure 2A This is a vertical cross-sectional view of an intermediate structure 200a after the formation of complementary metal-oxide-semiconductor (CMOS) transistors, metal interconnect structures, and dielectric material layers, according to various embodiments. The intermediate structure 200a may include a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may include at least a semiconductor material layer 10 on its upper portion. The substrate 8 may include a bulk semiconductor substrate, such as a silicon substrate, wherein the semiconductor material layer 10 extends continuously from the top surface of the substrate 8 to the bottom surface of the substrate 8, or the semiconductor material layer 10 serves as a semiconductor-on-insulator (SOI) layer covering a top semiconductor layer buried with an insulating layer (e.g., a silicon oxide layer). This structure may include various device regions 50, where devices may subsequently be formed.

[0148] This structure may also include a surrounding logic region 52, in which various devices and electrical connections between various surrounding circuits, including field-effect transistors, can subsequently be formed. During FEOL operation, semiconductor devices such as field-effect transistors (FETs) can be formed on and / or therein on the semiconductor material layer 10. For example, a shallow trench isolation structure 12 can be formed in the upper portion of the semiconductor material layer 10 by forming shallow trenches and subsequently filling the shallow trenches with a dielectric material such as silicon oxide. Other suitable dielectric materials are also within the scope of this disclosure. Various doped wells (not explicitly shown) can be formed in various regions of the upper portion of the semiconductor material layer 10 by performing a masked ion implantation process.

[0149] Gate structures 20 can be formed above the top surface of substrate 8 by depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate capdielectric dielectric layer. Each gate structure 20 may include a vertical stack of gate dielectric 22, gate electrode 24, and gate capdielectric 28, referred to herein as gate stacks (22, 24, 28). Ion implantation processes can be performed to form extended implantation regions, which may include source extension regions and drain extension regions. Dielectric gate spacers 26 may be formed around the gate stacks (22, 24, 28). Each component of the dielectric gate spacers 26 and the gate stacks (22, 24, 28) can constitute a gate structure 20. Gate structures 20 can be used as self-aligned implantation masks to perform additional ion implantation processes to form deep active regions.

[0150] Such a deep active region may include a deep source region and a deep drain region. The upper portion of the deep active region may partially overlap with the extended implantation region. Depending on the bias voltage, each combination of the extended implantation region and the deep implantation active region may constitute the source / drain region 14. A semiconductor channel 15 may be formed beneath each gate stack (22, 24, 28) between adjacent pairs of source / drain regions 14. A metal-semiconductor alloy region 18 may be formed on the top surface of each source / drain region 14.

[0151] Field-effect transistors (FETs) can be formed on the semiconductor material layer 10. Each FET may include a gate structure 20, a semiconductor channel 15, a pair of source / drain regions 14 (one serving as the source region and the other as the drain region), and an optional metal-semiconductor alloy region 18. CMOS circuitry 75 may be disposed on the semiconductor material layer 10, and may include peripheral circuitry for the transistor array, such as thin-film transistors (TFTs) and phase-change material (PCM) switches.

[0152] In one embodiment, substrate 8 may include a single-crystal silicon substrate, and CMOS circuit 75 may include a corresponding portion of the single-crystal silicon substrate as a semiconductor channel. As used herein, a "semiconductor" element refers to an element with a conductivity of 1.0 × 10⁻⁶. -6 S / cm up to 1.0×10 5 Components in the S / cm range. As used herein, "semiconductor material" refers to a material having a density of 1.0 × 10⁻⁶ S / cm in the absence of electrical dopant. -6 S / cm up to 1.0×10 5 Materials with electrical conductivity in the range of S / cm and capable of producing doped materials. After appropriate doping with an electrical dopant, they exhibit conductivity from 1.0 S / cm to 1.0 × 10⁻⁶. 5 Conductivity in the range of S / cm.

[0153] Various interconnect-level structures can then be formed, which can form the front interconnect layer as described above. The interconnect-level structure can be referred to as the lower interconnect-level structure (L0, L1, L2) and can be formed before any additional BEOL devices (such as additional memory devices). In some embodiments, one or more additional devices can be formed above one or more interconnect-level metal lines. For example, one or more additional devices may include TFTs, memory devices, or PCM switches.

[0154] The lower interconnect hierarchy (L0, L1, L2) may include a contact hierarchy L0, a first interconnect hierarchy L1, and a second interconnect hierarchy L2. The contact hierarchy L0 may include a planarized dielectric layer 31A and various contact via structures 41V. The planarized dielectric layer 31A includes a planarizable dielectric material such as silicon oxide. The various contact via structures 41V contact a corresponding one of the source / drain regions 14 or the gate electrode 24 and are formed within the planarized dielectric layer 31A.

[0155] The first interconnect layer structure L1 may include a first interconnect level dielectric (ILD) layer 31B and a first metal line 41L formed within the first ILD layer 31B. The first ILD layer 31B is also referred to as a first line-level dielectric layer. The first metal line 41L may contact a corresponding one of the contact via structures 41V. The second interconnect layer structure L2 may include a second ILD layer 32 and a stack of a first via-level dielectric material layer and a second line-level dielectric material layer or a line-and-via-level dielectric material layer. The second ILD layer 32 may include a second interconnect level metal interconnect structure (42V, 42L) therein, which includes a first metal via structure 42V and a second metal line 42L. The top surface of the second metal line 42L may be coplanar with the top surface of the second ILD layer 32.

[0156] Figure 2B This is a vertical cross-sectional view of another intermediate structure 200b structure during the formation of one or more additional BEOL devices (e.g., phase change material switches, memory devices, etc.) according to various embodiments. One or more additional BEOL devices may be formed in device region 50 above the second interconnect hierarchy L2. A third ILD layer 33 may be formed during the formation of one or more additional BEOL devices 95. The collection of all structures formed at the level of one or more BEOL devices 95 may be referred to as the third interconnect hierarchy L3. In other embodiments, various additional interconnect layers may be formed above the intermediate structure 200b as needed, based on circuit design considerations.

[0157] Figures 3A to 3D This is a vertical cross-sectional view of intermediate structures (300a, 300b, 300c, 300d) that can be used to form semiconductor dies (104a, 104b) according to various embodiments. Intermediate structure 300a may include a semiconductor material layer 10 having a plurality of transistor structures 301 formed on a semiconductor substrate 8 in a FEOL process, as referenced above. Figure 2A and Figure 2B As described. In this example embodiment, transistor structure 301 is shown as a FinFET transistor; however, other types of transistor structures may be formed in semiconductor material layer 10. For example, in other embodiments, semiconductor material layer 10 may include CMOS circuitry 75, as referenced above. Figure 2A and 2B As described.

[0158] The semiconductor material layer 10 may include a doped semiconductor material layer 11, from which various fin structures 13 may be formed. The doped semiconductor material layer 11 may be formed by introducing n-type or p-type dopant atoms into the semiconductor substrate 8 through diffusion, ion implantation, plasma doping, or the like. The resulting doped semiconductor material layer 11 may then be patterned and etched to form the fin structures 13. The fin structures 13 formed in this way may have a conductivity corresponding to the conductivity of the doped semiconductor material layer 11. Thus, each channel region (not shown) of the fin structure 13 may have a corresponding conductivity. In this regard, if the doped semiconductor material layer 11 contains an n-type dopant, an N-channel FinFET structure 301 may subsequently be formed; if the doped semiconductor material layer 11 contains a p-type dopant, a P-channel FinFET structure 301 may subsequently be formed. In other embodiments, the doped semiconductor material layer 11 may be omitted, and the resulting fin structures 13 may be nominally undoped.

[0159] For example, the fin structure 13 can be further doped by ion implantation to form corresponding source and drain regions (not shown). In this regard, the respective ends of the fin structure 13 extending into and out of the plane can be doped before or after forming the fin structure 13 to form the source and drain regions. Then, a dielectric material such as silicon oxide can be deposited over the resulting structure to form shallow trench isolation structures 12 that can separate the individual fin structures 13. Other suitable dielectric materials are also within the scope of this disclosure.

[0160] Multiple gate structures 20 can then be formed over the multiple fin structures 13. As described above, the gate structure 20 can be formed by depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate cap dielectric layer. The channel region (not shown) formed under each fin structure 13 below each gate structure 20 can be further doped to fine-tune the conductivity of the channel region to meet desired device characteristics. The intermediate structure 300a may also include a planarization dielectric layer 31A, which includes a planarizable dielectric material such as silicon oxide. Other suitable dielectric materials are also within the scope of this disclosure.

[0161] Figure 3B The intermediate structure 300b can be formed by removing the top portion of the planarized dielectric layer 31A above the top surface of the transistor structure 301 and by forming a via structure 118 through the semiconductor material layer 10. Figure 3A An intermediate structure 300a is formed. As shown, a via structure 118 can be formed in a shallow trench isolation structure 12 in the region between transistor structures 301. The via structure 118 can have a width in the range of 10 nm to 20 nm, but narrower or wider via structures 118 can be used. Figure 3BAs shown, the via structure 118 can be formed to pass through the semiconductor material layer 10 and enter the semiconductor substrate 8. In other embodiments, the via structure 118 can be formed at locations other than between the transistor structures 301.

[0162] Figure 3C The intermediate structure 300c can be formed by an additional layer of planarized dielectric layer 31A above the via structure 118. Figure 3B The intermediate structure 300b is formed. Then, a first via 304V can be formed in the planarized dielectric layer 31A. Thus, as... Figure 3C As shown, a first via layer V1 and a first metal layer M1 can be formed. (As illustrated...) Figure 3C As shown, the first via layer V1 may represent the top structure of the semiconductor material layer 10, while the first metal layer M1 may be the first layer in the subsequently formed front-side interconnect structure. In various embodiments, one or more additional metal lines 304L and vias 304V may be formed over the first via layer V1 and the first metal layer M1. For example, in some embodiments, the resulting front-side interconnect structure may include 10 to 20 interconnect layers (not shown) formed in 10 to 20 corresponding front-side dielectric layers.

[0163] Figure 3D This is a vertical cross-sectional view of another intermediate structure 300d, which can be used to form semiconductor dies (104a, 104b), according to various embodiments. In this respect, Figure 3C The intermediate structure 300c can be inverted (for example, see...). Figure 3D This allows additional BEOL processes to be performed to form the back-side interconnect structure 108 (e.g., see...). Figure 1 In this regard, the back side portion of substrate 8 can be removed through a planarization process, and multiple via cavities (not shown) can be formed in the remaining portion of substrate 8. For example... Figure 3D As shown, a first back-side via 310V can then be formed. A first back-side metallization layer 312, including a first back-side metal line 310L, can then be formed. Additionally, a back-side floating via 119 can be formed in the substrate 8. The back-side floating via 119 can form part of an alignment mark 120, as shown below. Figure 7A and 7B More detailed description.

[0164] like Figure 3DAs shown, the back-side portion of the substrate 8, including the first back-side via 310V, together with the first back-side metallization layer 312, can form a first element of a back-side interconnect structure. In some embodiments, a plurality of additional metal lines and vias can then be formed over the first back-side via 310V together with the first back-side metallization layer 312 to form additional elements of the back-side interconnect structure. For example, in some embodiments, the resulting back-side interconnect structure may include 5 to 10 interconnect levels (not shown) formed in 5 to 10 corresponding back-side dielectric layers. Back-side electrical contacts 108 can then be formed over the back-side interconnect structure (e.g., see...). Figure 1 ).

[0165] Figure 4A This is a vertical cross-sectional view of an intermediate structure 400a that can be used to form a semiconductor package structure 100 according to various embodiments. The intermediate structure 400a may correspond to a similar structure that can be formed on a wafer 402 (e.g., see...). Figure 5A and 5B A single repeating unit 502a in a two-dimensional array. In this way, multiple semiconductor package structures 100 can be formed simultaneously for mass production. For simplicity in the following description, reference is made to a single package structure 100 (e.g., see...). Figure 1 The formation of ) is used to describe the processing operation.

[0166] The intermediate structure 400a may include a first redistribution layer 102a (having an electrical interconnect structure 401 formed in a dielectric layer 408) formed over the wafer 402 (e.g., a carrier substrate). The wafer 402 may also include an adhesion layer 404 on the surface of the wafer 402 located between the wafer 402 and the first redistribution layer 102a. In some embodiments, the wafer 402 may include, for example, a polymer, a silicon-based material (e.g., glass, ceramic, or silicon oxide), or other materials (e.g., alumina), or any combination of these materials. The wafer 402 may include one or more semiconductor dies (e.g., Figure 1 The first semiconductor die 104a and the second semiconductor die 104b shown can be configured to have flat surfaces to accommodate the attachment of one or more semiconductor dies.

[0167] An adhesive layer 404 can be placed on wafer 402 to removably attach a cover structure (e.g., the first redistribution layer 102a) to wafer 402. In an exemplary embodiment, adhesive layer 404 may include a UV adhesive, which may be configured to lose its adhesive properties when exposed to UV light. In other embodiments, other types of adhesives may also be used, such as pressure-sensitive adhesives, radiation-curable adhesives, photothermal conversion release coatings (LTHC), epoxy resins, combinations thereof, etc. Adhesive layer 404 may be placed on wafer 402 in a semi-liquid or gel form and may be easily deformable under pressure. In some embodiments, a semiconductor package structure 100 may be formed on adhesive layer 404. In some embodiments, the first redistribution layer 102a may be configured as an integrated fan-out (InFO) package, but other types of packages may be used in other embodiments. In this respect, the first redistribution layer 102a may have a fan-out configuration, as described above.

[0168] The first redistribution layer 102a may include at least one insulating layer (not shown). The insulating layer may be placed on top of the first redistribution layer 102a and can be used to provide protection for, for example, the first semiconductor die 104a and the second semiconductor die 104b once they have been attached. In embodiments, the insulating layer may include polybenzoxazole (PBO), but any suitable material, such as polyimide or a polyimide derivative, may also be used alternatively. The insulating layer may be placed using, for example, a spin-coating process to deposit a film with a thickness in the range of about 2 micrometers to about 15 micrometers (e.g., about 5 micrometers), but any suitable method and thickness may also be used alternatively. In some embodiments, the first redistribution layer 102a may also include a circuit layer for electrically connecting the first semiconductor die 104a and the second semiconductor die 104b to the first redistribution layer 102a.

[0169] Figure 4B This is a vertical cross-sectional view of another intermediate structure 400b that can be used to form a semiconductor package structure 100 according to various embodiments. The intermediate structure 400b can be formed from the intermediate structure 400a by forming a plurality of molding material vias 142 over the first redistribution layer 102a. The molding material vias 142 can be configured to surround at least one device region, wherein a first semiconductor die 104a and a second semiconductor die 104b can subsequently be attached. The molding material vias 142 can be formed on and electrically connected to the first redistribution layer 102a located on the wafer 402. In other embodiments, the molding material vias 142 can be pre-formed as separate structures and then attached to the carrier first redistribution layer 102a.

[0170] The molding material perforation 142 can be formed over the first redistribution layer 102a as follows. A seed layer (not shown) can be formed over the first redistribution layer 102a. The seed layer can be a thin layer of conductive material that facilitates the formation of a thicker layer during subsequent processing steps. For example, the seed layer can include a titanium layer on which a copper layer is formed. The titanium can have a thickness of about 100 nm and the copper can have a thickness of about 500 nm. Various processes can be used to deposit the seed layer, such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD), depending on the material chosen for the seed layer.

[0171] Photoresist (not shown) can then be formed over the seed layer using, for example, spin coating. The photoresist can then be patterned by exposing it to a patterning energy source (e.g., a patterning light source), causing physical changes to those portions of the photoresist exposed to the patterning light source. A developer can then be applied to the exposed photoresist to selectively remove the exposed or unexposed portions of the photoresist according to the desired pattern. The pattern formed in the photoresist can then be used to create molding material vias 142. Molding material vias 142 can be formed at locations surrounding regions where the first semiconductor die 104a and the second semiconductor die 104b can subsequently be attached.

[0172] The molding material through-hole 142 can then be formed by depositing a conductive material not masked by the photoresist in the region. The conductive material used to form the molding material through-hole 142 may include copper, tungsten, or other conductive metals. Such a material can be deposited, for example, by electroplating, electroless plating, etc. In an embodiment, the electroplating process can be used to expose the conductive region of the seed layer within the opening of the photoresist. Once the molding material through-hole 142 is formed using the photoresist and seed layer, the photoresist can be removed using a suitable removal process. For example, a plasma ashing process can be used to remove the photoresist, thereby increasing the temperature of the photoresist until it undergoes thermal decomposition that allows for photoresist removal. In other embodiments, other suitable processes, such as wet stripping, can be utilized. The removal of the photoresist can expose the underlying portion of the seed layer.

[0173] For example, exposed portions of the seed layer (e.g., those not covered by the molding material perforations 142) can be removed using wet or dry etching processes. For instance, in a dry etching process, the molding material perforations 142 can be used as a mask to guide reactants to the seed layer. Alternatively, an etchant can be sprayed or otherwise brought into contact with the seed layer to remove exposed portions of the seed layer. After the exposed portions of the seed layer are removed (e.g., etched away), a portion of the first redistribution layer 102a can be exposed between the molding material perforations 142, thereby completing the process of forming the molding material perforations 142.

[0174] Figure 4C This is a vertical cross-sectional view of another intermediate structure 400c that can be used to form a semiconductor package structure 100 according to various embodiments. As shown, a first semiconductor die 104a and a second semiconductor die 104b can be positioned above a first redistribution layer 102a, ready to be attached to the first redistribution layer 102a. In this respect, the first semiconductor die 104a and the second semiconductor die 104b can be formed separately and can be positioned above the first redistribution layer 102a using a pick-and-place tool. Each of the first semiconductor die 104a and the second semiconductor die 104b may include a front-side electrical contact 106 and a back-side electrical contact 108, as referenced above. Figure 1 and 3A As described in 3D. The front electrical contact 106 may be configured with a solder material portion 406, which can be used to electrically couple the first semiconductor die 104a and the second semiconductor die 104b.

[0175] Figure 4D and 4E This is a vertical cross-sectional view of additional intermediate structures (400d, 400e) that can be used to form the semiconductor package structure 100 according to various embodiments. Figure 4D As shown, the first semiconductor die 104a and the second semiconductor die 104b can be attached to and electrically coupled to the first redistribution layer 102a. For example, a flip-chip bonding process can be performed to attach the first semiconductor die 104a and the second semiconductor die 104b to the first redistribution layer 102a.

[0176] In this respect, the pick-and-place tool can position the first semiconductor die 104a and the second semiconductor die 104b relative to the first redistribution layer 102a, such that the solder material portion 406 attached to the front electrical contact 106 (e.g., see...) Figure 4C The first semiconductor die 104a can contact the top-side electrical contact 110 of the first redistribution layer 102a. A reflow soldering operation can then be performed to melt the solder material portion 406, which can solidify upon cooling to form electrical and mechanical connections between the first semiconductor die 104a, the second semiconductor die 104b, and the first redistribution layer 102a. Afterwards, an underfill material 116 can be formed in the space between the semiconductor dies (104a, 104b) and the top surface of the first redistribution layer 102a, such as... Figure 4E As shown.

[0177] like Figure 4D and 4EAs shown, the first semiconductor die 104a and the second semiconductor die 104b can be placed in the region between the molding material perforations 142, so that the first semiconductor die 104a and the second semiconductor die 104b are effectively surrounded by the molding material perforations 142.

[0178] In some embodiments, one or both of the first semiconductor die 104a and the second semiconductor die 104b may be a logic device die, including logic circuitry formed therein. In other embodiments, one or both of the first semiconductor die 104a and the second semiconductor die 104b may be used in mobile applications and may include a power management integrated circuit (PMIC) die and a transceiver (TRX) chip. In other embodiments, one or more additional semiconductor dies (not shown) may be placed on a first redistribution layer 102a adjacent to each other. As described above, the first semiconductor die 104a and the second semiconductor die 104b may include a plurality of integrated circuits formed on the device substrate 8.

[0179] The device substrate 8 on which the integrated circuits 104a and 104b are formed may include bulk silicon, doped or undoped silicon, an active layer of a silicon-on-insulator (SOI) substrate, or another doped or undoped semiconductor substrate. For example, the SOI substrate may include a layer of semiconductor material, such as silicon, germanium, silicon-germanium, SOI, silicon-on-insulator (SGOI), or combinations thereof. Other substrates that may be used may include multilayer substrates, gradient substrates, or hybrid orientation substrates. The integrated circuit may include various active and passive devices, such as capacitors, resistors, inductors, etc., which can be used to achieve the desired structural and functional requirements of the design of the first semiconductor die 104a and the second semiconductor die 104b. The integrated circuit may be formed within or on the substrate using any suitable method.

[0180] In some embodiments, the top tip of the molding material through-hole 142 may be flush with the top surface of the back-side electrical contact 108. In other embodiments, the top tip of the molding material through-hole 142 may be higher than the top surface of the back-side electrical contact 108. Alternatively, the top tip of the molding material through-hole 142 may be lower than the top surface of the back-side electrical contact 108 but higher than the bottom surface of the back-side electrical contact 108.

[0181] Figure 4FThis is a vertical cross-sectional view of another intermediate structure 400f that can be used to form a semiconductor package structure 100 according to various embodiments. The intermediate structure 400f can be formed by a first molding material 140a formed over the first semiconductor die 104a, the second semiconductor die 104b, the molding material through-hole 142, and the first redistribution layer 102a. Figure 4E An intermediate structure 400e is formed. In this respect, the first molding material 140a can encapsulate the first semiconductor die 104a, the second semiconductor die 104b, and the molding material through-hole 142. In some embodiments, the first molding material 140a can fill the gap between the first semiconductor die 104a and the second semiconductor die 104b and can mechanically strengthen the intermediate structure 400f.

[0182] The first molding material 140a may include molding compound resins such as polyimide, PPS, PEEK, PES, heat-resistant crystalline resins, and combinations thereof. The encapsulation of the first semiconductor die 104a, the second semiconductor die 104b, and the through-hole 142 of the molding material can be achieved in a molded device ( Figure 4F (Not shown in the image) The first molding material 140a can be placed inside the molding cavity of the molding device or injected into the molding cavity through an injection port. Once the first molding material 140a has been placed in the molding cavity such that it can encapsulate the wafer 402, the first semiconductor die 104a, the second semiconductor die 104b, and the molding material through-hole 142, the first molding material 140a can then be cured to harden the first molding material 140a. Additionally, initiators and / or catalysts may be included within the first molding material 140a to better control the curing process. In some embodiments, the top surface of the first molding material 140a may be higher than the top of the molding material through-hole 142 and the top surfaces of the first semiconductor die 104a and the second semiconductor die 104b, such as... Figure 4F As shown.

[0183] Figure 4G This is a vertical cross-sectional view of another intermediate structure 400g, which can be used to form a semiconductor package structure 100 according to various embodiments. The intermediate structure 400g can be obtained by performing a thinning process to remove the top portion of the first molding material 140a. Figure 4F The intermediate structure 400f is formed. A thinning process can be performed on the first molding material 140a to expose the top of the molding material through-hole 142 and the top surface of the back electrical contact 108, such as... Figure 4G As shown.

[0184] The thinning process may include mechanical polishing or chemical mechanical planarization (CMP) processes, thereby using chemical etchants and abrasives to react and polish away a portion of the first molding material 140a to expose the top surface of the molding material through-hole 142 and the back-side electrical contacts 108. The resulting structure is as follows: Figure 4G As shown. The thinning process can also remove the top portion of the molding material perforation 142 and / or the top portion of the back-side electrical contact 108, so that the top of the molding material perforation 142, the top surface of the back-side electrical contact 108, and the top surface of the first molding material 140a are flush with each other, as shown. Figure 4G As shown. Although the CMP process described above can be used to perform a thinning process, various other removal processes can be used in other embodiments. For example, one or more chemical etching processes can be performed to thin the first molding material 140a, the first semiconductor die 104a, the second semiconductor die 104b, and the molding material through-hole 142. All such alternative thinning processes are within the scope of this disclosure.

[0185] Figure 4G The structure (including the first semiconductor die 104a, the second semiconductor die 104b, the molding material through-hole 142, and the first molding material 140a) can be referred to as an encapsulated semiconductor device 400g. Furthermore, the encapsulated semiconductor device 400g can be formed as one of a plurality of similar encapsulated semiconductor devices 400g on wafer 402 (e.g., see...). Figure 5A and Figure 5B Therefore, in each encapsulated semiconductor device 400g, a first semiconductor die 104a and a second semiconductor die 104b can be disposed in the die region, the molding material through-hole 142 can extend through the encapsulated semiconductor device 400g outside the die region, and the first molding material 140a can encapsulate the first semiconductor die 104a, the second semiconductor die 104b and the molding material through-hole 142.

[0186] Figure 4H This is a vertical cross-sectional view of another intermediate structure 400h, which can be used to form a semiconductor package structure 100 according to various embodiments. The intermediate structure 400h can be formed by creating a second redistribution layer 102b above the top side of the intermediate structure 400g (i.e., the semiconductor device encapsulation layer 400g). Figure 4GAn intermediate structure 400g is formed. The second redistribution layer 102b can be electrically connected to the first semiconductor die 104a, the second semiconductor die 104b, and the molding material through-hole 142. In some embodiments, the second redistribution layer 102b can be formed above the encapsulated semiconductor device 400g (including the first molding material 140a, the first semiconductor die 104a, and the second semiconductor die 104b) to connect the back-side electrical contacts 108 of the first semiconductor die 104a and the second semiconductor die 104b and the molding material through-hole 142 to the second redistribution layer 102b.

[0187] The second redistribution layer 102b can be formed by depositing and patterning a dielectric material layer 408 to form a patterned dielectric layer 408. A conductive material can then be formed over the patterned dielectric layer 408, for example, by electroplating. This process can be repeated several times to form the second redistribution layer 102b, which may include a plurality of electrical interconnect structures 401 formed within the dielectric material layer 408. The material of the electrical interconnect structures 401 may include metals or metal alloys, including aluminum, copper, tungsten, and / or alloys thereof. The dielectric material layer 408 may be formed of dielectric materials such as polymers, oxides, nitrides, carbides, carbon nitride, combinations thereof, and / or multiple layers thereof. The electrical interconnect structures 401 may be formed in the dielectric material layer 408 and may be electrically connected to the first semiconductor die 104a, the second semiconductor die 104b, and the molding material via 142. In some embodiments, the electrical interconnect structure 401 may further include a bump under-metal (UBM) layer (not shown) formed as part of the top-side electrical connection 110. Figure 4H As shown, the second redistribution layer 102b and the first redistribution layer 102a can be disposed on opposite sides of the encapsulated semiconductor device 400g. According to some embodiments, at least one of the first redistribution layer 102a and the second redistribution layer 102b includes features having at least one of a sub-micron linewidth or a sub-micron line spacing.

[0188] Figures 4I to 4L This is a vertical cross-sectional view of additional intermediate structures (400i to 400l) that can be used to form a semiconductor package structure 100 according to various embodiments. Intermediate structure 400i can be formed by attaching additional semiconductor dies (105a, 105b, 105c) to a second redistribution layer 102b. Figure 4H The intermediate structure is formed in 400h. Additional semiconductor dies (105a, 105b, 105c) can be attached to the second redistribution layer 102b by performing processes similar to those used to attach the first semiconductor die 104a and the second semiconductor die 104b to the first redistribution layer 102a, as referenced above. Figure 4C and 4D A more detailed description.

[0189] In this regard, a flip-chip process can be performed, in which pick-and-place tools position the additional semiconductor dies (105a, 105b, 105c) above the second redistribution layer 102b. A reflow soldering operation can then be performed to electrically and mechanically attach the additional semiconductor dies (105a, 105b, 105c) to the second redistribution layer. In a further processing step, an underfill material 116 can then be formed in the space between the additional semiconductor dies (105a, 105b, 105c) and the top surface of the second redistribution layer 102b, such as... Figure 4J As shown. Then you can use the above reference. Figure 4F and 4G The described technique involves forming a second molding material 140b above and around the additional semiconductor dies (105a, 105b, 105c), such as Figure 4K and 4L As shown.

[0190] Figure 4M and 4N This is a vertical cross-sectional view of additional intermediate structures (400m, 400n) that can be used to form a semiconductor package structure 100 according to various embodiments. The intermediate structure 400n can be formed by attaching a second wafer 402b (i.e., a carrier substrate) to the intermediate structure 400l using an adhesive layer 404 and by removing the first wafer 402a. Figure 4L An intermediate structure 400l is formed. As described above, the first wafer 402a can be removed by applying heat or ultraviolet radiation to deactivate the adhesive layer 404. Removing the first wafer 402a exposes the surface of the first redistribution layer 102a. Then, bottom-side electrical contacts 112 can be formed on the first redistribution layer 102a. Figure 4M The intermediate structure is formed at 400m. Figure 4N The intermediate structure 400n. Then, a solder material portion 406 can be formed above the bottom electrical contact 112. Then, a second wafer 402b can be formed by removing it from the intermediate structure 400n. Figure 1 The semiconductor packaging structure 100.

[0191] Figure 5A This is a top view of a wafer-level structure 500a, which can be used to form multiple semiconductor package structures 100 according to various embodiments. Figure 5A As shown, the wafer-level structure 500a may include a first redistribution layer 102a formed above the wafer 402a. The first redistribution layer 102a may include a first plurality of repeating units 502a spatially staggered from each other. In this respect, the first redistribution layer 102a may be arranged as a periodic array of the first plurality of repeating units 502a. Figure 5A As shown, each of the plurality of first repeating units 502a may have a rectangular shape and may have a uniform angular orientation.

[0192] As described above, one or more semiconductor dies (104a, 104b) can then be coupled to a first redistribution layer 102a located above each of the first plurality of repeating units 502a. Thus, each of the plurality of repeating units 502a can correspond to a corresponding semiconductor package structure 100 to be subsequently formed. In this regard, one or more semiconductor dies (104a, 104b) formed above each of the plurality of repeating units 502a can correspond to a first region (504a1, 504a2) that can be associated with one or more semiconductor dies (104a, 104b). In the absence of pick-and-place errors, each first region (504a1, 504a2) associated with one or more semiconductor dies (104a, 104b) can be spatially aligned with each of the first plurality of repeating units 502a of the first redistribution layer 102a. However, in practice, as feature sizes continue to decrease, pick-and-place errors may become unavoidable. Thus, each first region 504a may have a slight misalignment relative to a corresponding number of the first plurality of repeating units 502a. According to various embodiments, such pick and place errors can be measured, and the measured pick and place errors can be used to correct the placement of various features of the subsequent second redistribution layer 102b to be formed.

[0193] Figure 5B This is a top view of another wafer-level structure 500b, which can be used to form multiple semiconductor package structures according to various embodiments. Figure 5B The 500b wafer-level structure can be made from Figure 5A The wafer-level structure 500a is formed by coupling one or more semiconductor dies (104a, 104b) into place. Figure 5AThe first redistribution layer 102a is above each of the remaining first plurality of repeating units 502a. As described above, the placement of one or more semiconductor dies (104a, 104b) may include pick-and-place errors. Therefore, there may be some degree of misalignment between each first region (504a1, 504a2) associated with one or more semiconductor dies (104a, 104b) and the corresponding one of the first plurality of repeating units 502a. An exposure tool that can be used to generate the second redistribution layer 102b can measure the degree of misalignment between each first region (504a1, 504a2) and each corresponding repeating unit 502a, and can correct for the spatial features associated with the second redistribution layer 102b to be subsequently formed. Measurements can be made by capturing images of various alignment marks 120 formed on each of the one or more semiconductor dies (104a, 104b), as described below. Figure 5D and Figures 6A to 8F A more detailed description.

[0194] Modifications to the placement of features in the second redistribution layer 102b may include coarse adjustments and fine adjustments. Figure 5B An example of coarse adjustment is shown, wherein the overall pattern used to place the second redistribution layer 102b can be rotated relative to the pattern associated with the first redistribution layer 102a. For illustrative purposes, Figure 5B The rotation shown may be exaggerated. In reality, the overall rotation of the first redistribution layer 102a relative to the second redistribution layer 102b may only be a fraction of a degree. Coarse error correction can be determined by measuring the positions of two or more first regions (504a1, 504a2). Besides Figure 5B Compared to Figure 5A In addition to the rough alignment adjustments shown, you can also refer to the following: Figures 5C to 5F Make fine adjustments as described in more detail.

[0195] Figure 5C This is a top view illustrating another misplaced wafer-level structure 500c according to various embodiments, and Figure 5D yes Figure 5C An enlarged top view of a portion of the 500c wafer-level structure. (See image.) Figure 5C and 5DAs shown, each of the first regions (504a1, 504a2) may have placement errors, which may include rotation from one of the first regions 504a1 to the other of the first regions 504a2. To accurately measure the placement error, each of one or more semiconductor dies (104a, 104b) may include at least one alignment mark 120. Each alignment mark 120 may include fine features such that imaging the respective alignment marks 120 allows the exposure tool to accurately determine fine corrections for the placement of features in the second redistribution layer 102b, as described below. Figures 7A to 8F A more detailed description.

[0196] Figure 5E This is a top view of another wafer-level structure 500e, which can be used to form multiple semiconductor package structures 100 according to various embodiments, and Figure 5F yes Figure 5E An enlarged top view of a portion of the 500e wafer-level structure. (See image.) Figure 5E and Figure 5F As shown, the wafer-level structure 500e may include a second redistribution layer 102b formed on and electrically coupled to one or more semiconductor dies (104a, 104b). Figure 5E As shown, the second redistribution layer 102b may include a second plurality of repeating units 502b spatially offset from each other. Each of the second plurality of repeating units 502b may have a corresponding second region (504b1, 504b2) that may be spatially aligned with a corresponding first region (504a1, 504a2) associated with one or more semiconductor dies (104a, 104b). For example, in some embodiments, the second region (504b1, 504b2) may be aligned with the corresponding first region (504a1, 504a2) such that the coverage error is less than or equal to 0.5 micrometers. As described above, once the second redistribution layer 102b is formed (including coarse and fine placement corrections), one or more additional semiconductor dies (105a, 105b, 105c) may be attached to the second redistribution layer 102b.

[0197] Figures 6A to 6CTop views of various configurations (600a, 600b, 600c) according to various embodiments are shown, wherein each semiconductor die includes a back-side electrical contact 108 and alignment marks 120. In a first configuration 600a, a single semiconductor die 104a may be attached to a second redistribution layer 102b within each of a second plurality of repeating units 502b. Similarly, in a second configuration 600b, a first semiconductor die 104a and a second semiconductor die 104b may be attached to a second redistribution layer 102b within each of a second plurality of repeating units 502b. In a third configuration 600c, a first semiconductor die 104a, a second semiconductor die 104b, and a third semiconductor die 104c may be attached to a second redistribution layer 102b within each of a second plurality of repeating units 502b. As shown, each of the plurality of semiconductor dies (104a, 104b, 104c) may include a back-side electrical contact 108 and two or more alignment marks 120. Using two or more alignment marks 120 on each of the semiconductor dies (104a, 104b, 104c) in various configurations (600a, 600b, 600c) allows for the determination of the precise position and alignment data of each of the second plurality of repeating units 502b.

[0198] Figure 7A This is a vertical cross-sectional view of a semiconductor die 104a including back-side electrical contacts 108 and alignment marks 120 according to various embodiments, and Figure 7B yes Figure 7A A vertical cross-sectional view of a portion of the semiconductor die 104a shows details of the alignment marks 120. According to various embodiments, each alignment mark 120 may be a metal via structure 119 formed within the semiconductor substrate 8 of the semiconductor die 104a. For example, each alignment mark 120 may be formed as a copper via 119 or a silicon via 119. Reference can be made to the above in the context of forming conductive via structures 119. Figure 3B The processes described are similar to those used to form the alignment mark 120. However, with Figure 3D Unlike the via structure 118, the alignment mark 120 can be connected to the via structure 119 which is configured to be electrically floating (i.e., not electrically connected to the conductive interconnect structure 401). Furthermore, to improve the visibility of the alignment mark 120, each alignment mark 120 may include an alignment mark surface 702 that is recessed from the interface 704 by a recess distance 706, which is between 30 micrometers and 40 micrometers. Figure 7B As shown.

[0199] Figures 8A to 8FThis is a top view of exemplary alignment marks (120a, 120b, 120c, 120d, 120e, 120f) according to various embodiments, each exemplary alignment mark comprising a plurality of via structures 119. As shown, each alignment mark (120a, 120b, 120c, 120d, 120e, 120f) may include a plurality of via structures 119 formed in a given spatial configuration having a mirror-symmetric plane 802. Alternatively, various other embodiments may include alignment marks having via structures 119 (not shown) arranged asymmetrically. In various embodiments, exemplary alignment marks (120a, 120b, 120c, 120d, 120e, 120f) may be used individually on corresponding semiconductor dies (104a, 104b, 105a, 105b, 105c).

[0200] Alternatively, multiple sets of alignment markers (120a, 120b, 120c, 120d, 120e, 120f) can be used together. For example, alignment markers 120a and 120b can be formed as complementary pairs of alignment markers (120a, 120b) on one or more semiconductor dies (104a, 104b, 105a, 105b, 105c). Similarly, alignment markers 120c and 120d can be used together as complementary pairs of alignment markers (120c, 120d), just as alignment markers 120e and 120f can be used as complementary pairs of alignment markers (120e, 120f). Other various embodiments may include various different groups of alignment markers (120a, 120b, 120c, 120d, 120e, 120f), including groups of three or four alignment markers (120a, 120b, 120c, 120d, 120e, 120f).

[0201] Each alignment marker (120a, 120b, 120c, 120d, 120e, 120f) can have a relatively small spatial feature interval to allow for precise determination of fine alignment adjustments, as referenced above. Figures 5C to 5F Described. For example, Figure 8A and 8B The alignment markers (120a, 120b) may have given exemplary feature distances d1 = 50 μm, d2 = 15 μm, d3 = 9 μm, d4 = 9 μm, d5 = 55.5 μm, and d6 = 40.5. These values ​​of feature distances are provided as examples only, and various other sizes may be provided in other embodiments. In further exemplary embodiments, Figure 8C and Figure 8DThe alignment markers (120c, 120d) may have given exemplary feature distances d7 = 50 micrometers, d8 = 40.5 micrometers, d9 = 9 micrometers, and d10 = 9 micrometers. Similarly, these values ​​for feature distances are provided only as examples, and various other sizes may be provided in other embodiments.

[0202] include Figure 8E and Figure 8F The remaining embodiments of the alignment markers (120e, 120f) can have similar exemplary feature distances. As described above, each of the alignment markers (120a, 120b, 120c, 120d, 120e, 120f) can have a mirror symmetry plane 802. In other embodiments, alignment markers 120 can be provided with more or less symmetry. For example, alignment marker 120e may additionally have four-fold rotation symmetry about its midpoint. As described above, other embodiments of alignment markers 120 can have greater symmetry, reduced symmetry, or no specific symmetry.

[0203] Figure 9 This is a flowchart illustrating the operations of a method 900 for forming a wafer-level semiconductor structure (400h, 500e) according to various embodiments. In operation 902, method 900 may include forming a first redistribution layer 102a over wafer 402a, such that the first redistribution layer 102a includes a first plurality of repeating units 502a spatially offset from each other. In operation 904, method 900 may include attaching a first semiconductor die 104a and a second semiconductor die 104b to the first redistribution layer 102a over each of the first plurality of repeating units 502a, such that each of the first semiconductor die 104a and the second semiconductor die 104b is electrically coupled to the first redistribution layer 102a. In operation 906, method 900 may include measuring the spatial position and orientation of a first alignment mark 120 formed on the first semiconductor die 104a and the spatial position and orientation of a second alignment mark 120 formed on the second semiconductor die 104b.

[0204] In operation 908, method 900 may include determining the spatial location and orientation of a corresponding region 504a associated with the first semiconductor die 104a and the second semiconductor die 104b based on the spatial location and orientation of the first alignment mark 120 and the second alignment mark 120. In operation 910, method 900 may include forming a second redistribution layer 102b over and electrically attaching it to the first semiconductor die 104a and the second semiconductor die 104b by performing an additional operation. According to method 900, such an additional operation may include forming a second plurality of repeating units 502b that are spatially misaligned, such that each repeating unit may include a redistribution layer electrical connection 110.

[0205] In a further operation, method 900 may include spatially aligning each of the second plurality of repeating units 502b with the corresponding region 504a associated with the first semiconductor die 104a and the second semiconductor die 104b based on the spatial position and orientation of the corresponding region 504a associated with the first semiconductor die 104a and the second semiconductor die 104b. In a further operation, method 900 may include electrically connecting a redistribution layer electrical connection 110 to semiconductor die electrical connections 106 formed on the first semiconductor die 104a and the second semiconductor die 104b. When spatially aligning each of the second plurality of repeating units 502b with the corresponding region 504a associated with the first semiconductor die 104a and the second semiconductor die 104b, method 900 may further include controlling the spatial position and orientation of the second plurality of repeating units 502b such that the coverage error is less than or equal to 0.5 micrometers.

[0206] Method 900 may further include each of a first alignment mark 120 formed on a first semiconductor die 104a and a second alignment mark 120 formed on a second semiconductor die 104b to include a corresponding copper via 119 or a corresponding silicon via 119, each including an alignment mark surface 702 recessed from an interface 704 by a recess distance 706 between 30 and 40 micrometers. When spatially aligning each of the second plurality of repeating units 502b with a corresponding region 504a associated with the first semiconductor die 104a and the second semiconductor die 104b, method 900 may also perform a coarse alignment of the repeating units 502b of the second redistribution layer 102b (e.g., see...). Figure 5A and 5B ) and fine alignment (for example, see Figures 5C to 5F ).

[0207] By determining the position and orientation of at least two corresponding regions (504a1, 504a2) associated with the corresponding first semiconductor die 104a and second semiconductor die 104b, a coarse alignment operation can be performed to determine the position and coarse orientation of each of the subsequent plurality of repeating units 502b to be formed. A fine alignment operation can be performed to determine the precise orientation of each of the subsequent plurality of repeating units 502b to be formed based on the orientation of the first alignment mark 120 formed on the first semiconductor die 104a and the orientation of the second alignment mark 120 formed on the second semiconductor die 104b.

[0208] Referring to all the accompanying drawings and various embodiments of the present disclosure, a semiconductor package structure 100 is provided. The semiconductor package structure 100 may include a first redistribution layer 102a and a first semiconductor die 104a attached to the first redistribution layer 102a. The first semiconductor die 104a may include a first front-side electrical contact 106 and a first back-side electrical contact 108, such that the first front-side electrical contact 106 is electrically connected to the first redistribution layer 102a. The semiconductor package structure 100 may further include a second redistribution layer 102b formed over the first semiconductor die 104a, such that the second redistribution layer 102b is electrically connected to the first back-side electrical contact 108 of the first semiconductor die 104a. The semiconductor package structure 100 may further include a second semiconductor die 105a attached to the second redistribution layer 102b and vertically positioned over the first semiconductor die 104a. According to various embodiments, the first semiconductor die 104a may further include at least two alignment marks 120 spaced at least 50 micrometers apart.

[0209] According to various embodiments, a first region 504a associated with a first semiconductor die 104a can be aligned with a second region 504b associated with a second redistribution layer 102b, such that the coverage error is less than or equal to 0.5 micrometers. Furthermore, the first region 504a can correspond to a first spatial arrangement of a first back-side electrical contact 108 of the first semiconductor die 104a, and the second region 504b can correspond to a second spatial arrangement of a corresponding redistribution layer electrical connection 110. At least one of the first redistribution layer 102a and the second redistribution layer 102b includes features having at least one of a submicron linewidth or a submicron line spacing. At least two alignment marks 120 can be metal via structures 119 formed within the semiconductor substrate 8 of the first semiconductor die 104a.

[0210] In some embodiments, at least two alignment marks 120 may be formed as copper vias 119. According to various embodiments, the semiconductor substrate 8 may include silicon and at least two alignment marks 120 may be formed as silicon vias 119. In another embodiment, at least two alignment marks 120 may each have an alignment mark surface 702 that is recessed from the interface 704 by a recess distance 706 between 30 and 40 micrometers. Furthermore, in some embodiments, at least two alignment marks 120 may each include a shape having a mirror-symmetric plane 802. And in yet another embodiment, at least one of the at least two alignment marks 120 may also include fourfold rotational symmetry (e.g., see...). Figure 8E ).

[0211] According to some other embodiments, a wafer-level semiconductor structure (400h, 500e) is provided. The wafer-level semiconductor structure (400h, 500e) may include a first redistribution layer 102a formed over a wafer 402a, having a first plurality of repeating units 502a spatially offset from each other. The wafer-level semiconductor structure (400h, 500e) may also include a first semiconductor die 104a and a second semiconductor die 104b electrically coupled to the first redistribution layer 102a over each of the first plurality of repeating units 502a, and a second redistribution layer 102b formed over and electrically coupled to the first semiconductor die 104a and the second semiconductor die 104b. The second redistribution layer 102b may include a second plurality of repeating units 502b that are spatially misaligned with each other, and each of the second plurality of repeating units 502b may be spatially aligned with a corresponding region 504a associated with the first semiconductor die 104a and the second semiconductor die 104b, such that the coverage error is less than or equal to 0.5 micrometers.

[0212] Each of the first semiconductor die 104a and the second semiconductor die 104b may include at least one alignment mark 120. In some embodiments, the at least one alignment mark 120 may be a metal structure 119 formed within the semiconductor substrate 8 of each of the first semiconductor die 104a and the second semiconductor die 104b. For example, the at least one alignment mark 120 may be formed as a copper via 119 or a silicon via 119. In various embodiments, the at least one alignment mark 120 may include an alignment mark surface 702 that is recessed from the interface 704 by a recess distance 706 between 30 micrometers and 40 micrometers. Furthermore, in some embodiments, the at least one alignment mark 120 may include a shape having a mirror-symmetric plane 802. In still other embodiments, the wafer-level semiconductor structure (400i to 400n) may include a third semiconductor die 105a and a fourth semiconductor die 105b electrically coupled to a second redistribution layer 102b above each of the second plurality of repeating units 502b.

[0213] According to some other embodiments, a method for forming a wafer-level semiconductor structure is provided. This method includes: forming a first redistribution layer over a wafer, such that the first redistribution layer includes a first plurality of repeating units spatially offset from each other; attaching a first semiconductor die and a second semiconductor die to the first redistribution layer over each of the first plurality of repeating units, such that each of the first semiconductor die and the second semiconductor die is electrically coupled to the first redistribution layer; measuring the spatial position and orientation of a first alignment mark formed on the first semiconductor die and a second alignment mark formed on the second semiconductor die; determining the spatial position and orientation of corresponding regions associated with the first semiconductor die and the second semiconductor die based on the spatial position and orientation of the first alignment mark and the second alignment mark; and forming a second redistribution layer over the first semiconductor die and the second semiconductor die and electrically connected to the first semiconductor die.

[0214] The second semiconductor die is formed by performing the following operations: forming a second plurality of repeating units spatially offset from each other, each of the second plurality of repeating units including a redistribution layer electrical connection; spatially aligning each of the second plurality of repeating units with the corresponding regions associated with the first semiconductor die and the second semiconductor die based on the spatial position and orientation of the corresponding regions associated with the first semiconductor die and the second semiconductor die; and electrically connecting the redistribution layer to semiconductor die electrical connections formed on the first semiconductor die and the second semiconductor die.

[0215] In one embodiment, spatially aligning each of the second plurality of repeating units with the corresponding regions associated with the first semiconductor die and the second semiconductor die further includes controlling the spatial position and orientation of the second plurality of repeating units such that the coverage error is less than or equal to 0.5 micrometers. In one embodiment, the method further includes forming each of the first alignment marks on the first semiconductor die and forming the second alignment marks on the second semiconductor die to include a corresponding copper via or a corresponding silicon via, each including an alignment mark surface recessed from the interface by a distance between 30 and 40 micrometers. In one embodiment, spatially aligning each of the second plurality of repeating units with the corresponding regions associated with the first semiconductor die and the second semiconductor die further includes: performing a coarse alignment operation to determine the position and coarse orientation of each of the second plurality of repeating units to be subsequently formed by determining at least two corresponding regions associated with the respective first semiconductor die and the second semiconductor die; and performing a fine alignment operation to determine the precise orientation of each of the second plurality of repeating units to be subsequently formed based on the orientation of the first alignment mark formed on the first semiconductor die and the second alignment mark formed on the second semiconductor die.

[0216] The various embodiments disclosed herein can be advantageous by providing systems and methods for improving the placement accuracy of components or semiconductor packages 100. In this regard, the semiconductor package 100 can be formed by attaching semiconductor dies (104a, 104b) to a first redistribution layer 102a and forming a second redistribution layer 102b over the semiconductor dies (104a, 104b). Exemplary systems and methods may provide alignment marks (120a, 120b, 120c, 120d, 120e, 120f) with detailed features that allow for precise measurement of placement errors of the semiconductor dies (104a, 104b). Such measurements can then be used to adjust the features of the second redistribution layer 102b to correct for placement errors of the semiconductor dies (104a, 104b).

[0217] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor package structure, comprising: Comprising: a first redistribution layer; a first semiconductor die attached to the first redistribution layer, wherein the first semiconductor die includes first front-side electrical contacts and first back-side electrical contacts such that the first front-side electrical contacts are electrically connected to the first redistribution layer; a second redistribution layer formed over the first semiconductor die such that the second redistribution layer is electrically connected to the first back-side electrical contacts of the first semiconductor die; and a second semiconductor die attached to the second redistribution layer and vertically positioned over the first semiconductor die, wherein the first semiconductor die further includes at least two alignment marks that are at least 50 microns apart from each other. a first area associated with the first semiconductor die is aligned to a second area associated with the second redistribution layer such that a overlay error is less than or equal to 0.5 microns, the first area corresponds to a first spatial configuration of the first back-side electrical contacts of the first semiconductor die, and the second area corresponds to a second spatial configuration of the respective redistribution layer electrical connections.

2. The semiconductor package structure of claim 1, wherein, At least one of the first redistribution layer and the second redistribution layer includes features having at least one of sub-micron line width or sub-micron line spacing.

3. The semiconductor package structure of claim 1, wherein, The at least two alignment marks are metal structures formed within a semiconductor substrate of the first semiconductor die, each of the at least two alignment marks has an alignment mark surface that is recessed from an interface by a recess distance between 30 microns and 40 microns.

4. The semiconductor package structure of claim 1, wherein, Each of the at least two alignment marks includes a shape having a mirror-symmetry plane.

5. The semiconductor package structure of claim 1, wherein, At least one of the at least two alignment marks further includes a four-fold rotational symmetry.

6. The semiconductor package structure of claim 5, wherein, Comprising:

7. A wafer-level semiconductor structure, characterized by a first redistribution layer formed over a wafer, wherein the first redistribution layer includes a first plurality of repeating units that are spatially staggered from each other; a first semiconductor die and a second semiconductor die electrically coupled to the first redistribution layer over each of the first plurality of repeating units; and a second redistribution layer formed over the first semiconductor die and the second semiconductor die and electrically coupled to the first semiconductor die and the second semiconductor die, wherein the second redistribution layer includes a second plurality of repeating units that are spatially staggered from each other, wherein each of the second plurality of repeating units is spatially aligned to a respective area associated with the first semiconductor die and the second semiconductor die such that an overlay error is less than or equal to 0.5 microns. The first semiconductor die and the second semiconductor die each include at least one alignment mark that is a metal structure formed within a semiconductor substrate of each of the first semiconductor die and the second semiconductor die. The at least one alignment mark is formed as a copper via or a silicon through hole.

8. The wafer-level semiconductor structure of claim 7, wherein, Further comprising a third semiconductor die and a fourth semiconductor die electrically coupled to the second redistribution layer over each of the second plurality of repeating units.

9. The wafer-level semiconductor structure of claim 8, wherein, ​ 10. The wafer-level semiconductor structure of claim 7, wherein, ​

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