Display panel and display device

Abstract

The embodiment of the utility model discloses a display panel and a display device, an array substrate of the display panel comprises a first substrate, a signal line area and a gate drive circuit area, the signal line area and the gate drive circuit area are arranged on one side, facing an opposite substrate, of the first substrate and correspond to a peripheral area, and the gate drive circuit area is located between the signal line area and a display area; the orthographic projection of the frame sealing glue on the first substrate is at least partially overlapped with the orthographic projection of the signal line area on the first substrate, and is not overlapped with the orthographic projection of the gate driving circuit area on the first substrate; the display panel further comprises a first spacer layer arranged in the frame sealing glue and a second spacer layer arranged between the array substrate and the opposite substrate. The orthographic projection of the first spacer layer on the first substrate is at least partially overlapped with the orthographic projection of the signal line area on the first substrate, and the orthographic projection of the second spacer layer on the first substrate is at least partially overlapped with the orthographic projection of the gate drive circuit area on the first substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Utility Model Content

[0003] This disclosure provides a display panel and a display device, the specific solutions of which are as follows:

[0004] This disclosure provides a display panel having a display area and a peripheral area surrounding the display area. The display panel includes an array substrate and a counter substrate disposed opposite each other, and a sealing adhesive located in the peripheral area and disposed between the array substrate and the counter substrate. The array substrate includes a first substrate and a signal line area and a gate driving circuit area disposed on the side of the first substrate facing the counter substrate and corresponding to the peripheral area. The gate driving circuit area is located between the signal line area and the display area. The orthographic projection of the sealing adhesive on the first substrate at least partially overlaps with the orthographic projection of the signal line area on the first substrate, but does not overlap with the orthographic projection of the gate driving circuit area on the first substrate.

[0005] The display panel further includes: a first spacer layer disposed within the sealant, and a second spacer layer disposed between the array substrate and the opposing substrate; the orthographic projection of the first spacer layer on the first substrate at least partially overlaps with the orthographic projection of the signal line region on the first substrate, and the orthographic projection of the second spacer layer on the first substrate at least partially overlaps with the orthographic projection of the gate drive circuit region on the first substrate.

[0006] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the height of the first spacer layer along the thickness direction of the display panel is less than the maximum height of the sealing adhesive along the thickness direction of the display panel.

[0007] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the array substrate further includes a blank area disposed on the side of the signal line area away from the display area, wherein the orthographic projection of the first spacer layer on the first substrate overlaps with the orthographic projection of the blank area on the first substrate, and the orthographic projection of the sealing adhesive on the first substrate overlaps with the orthographic projection of the blank area on the first substrate.

[0008] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the sealing adhesive is a closed structure surrounding the display area, and the first spacer layer surrounds the display area.

[0009] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the first spacer layer and the second spacer layer are disposed on the side of the array substrate facing the opposing substrate.

[0010] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the first spacer layer is a closed structure surrounding the display area.

[0011] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the sealing adhesive covers at least a portion of the top surface of the first spacer layer on the side away from the first substrate, and covers the side surface of the first spacer layer on the side away from the display area.

[0012] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the width of the first spacer layer is smaller than the width of the sealing adhesive along the direction perpendicular to the thickness of the display panel.

[0013] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the orthographic projection shape of the second spacer layer on the array substrate is a planar structure.

[0014] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the first spacer layer and the second spacer layer are an integral structure.

[0015] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the minimum distance L1 between the inner edge of the sealing adhesive near the display area and the outer edge of the second spacer layer away from the display area satisfies the following formula:

[0016]

[0017] Wherein, L11 is the positional accuracy of the sealing adhesive, L12 is the single-sided width accuracy of the sealing adhesive, L13 is the single-sided width accuracy of the second spacer layer, and L14 is the positional accuracy of the second spacer layer.

[0018] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the gate driving circuit region includes an organic insulating layer via and a signal line overlap region, the second spacer layer includes at least one second spacer spaced apart from each other, and at least one surface of the organic insulating layer via and the signal line overlap region covers the second spacer spacer.

[0019] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the size of the second spacer is larger than the size of the organic insulating layer via, and the size of the second spacer is larger than the size of the signal line overlap area.

[0020] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the orthographic projection shape of the second spacer on the first substrate includes a circle or a square.

[0021] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the size L2 of the second spacer satisfies the following formula:

[0022]

[0023] Wherein, L21 is the size of the via in the organic insulating layer or the overlapping area of ​​the signal lines, L22 is the width accuracy of the second spacer, and L23 is the width accuracy of the via in the organic insulating layer or the overlapping area of ​​the signal lines.

[0024] In one possible implementation, the display panel provided in the embodiments of this disclosure further includes: a first alignment film located on the side of the second spacer layer facing the opposing substrate, wherein the distance between the second spacer layer and the adjacent boundary of the display area is greater than the width of the first alignment film covering the sidewall of the second spacer layer near the display area.

[0025] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the first spacer layer and the second spacer layer are disposed on the side of the opposing substrate facing the array substrate.

[0026] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the first spacer layer includes a plurality of first spacers spaced apart from each other, and the sealing adhesive contacts the array substrate or the opposing substrate through the gap between adjacent first spacers.

[0027] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the orthographic projection shape of the first spacer on the array substrate is circular, elliptical, square, strip-shaped, or mesh-like.

[0028] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the second spacer layer includes a plurality of second spacers spaced apart from each other.

[0029] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the display area includes a plurality of main spacers spaced apart from each other, the second spacers having the same shape and size as the main spacers, and the arrangement period of the plurality of second spacers being the same as the arrangement period of the plurality of main spacers.

[0030] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the array substrate further includes a common electrode lead area located between the gate driving circuit area and the display area, wherein the orthographic projection of the second spacer layer on the array substrate does not overlap with the orthographic projection of the common electrode lead area on the array substrate.

[0031] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the signal line area, the gate driving circuit area, the common electrode lead area, and the display area include a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a first conductive layer sequentially stacked between the first substrate and the second spacer layer. The array substrate further includes an organic insulating layer located between the second metal layer and the second insulating layer. The orthographic projection of the organic insulating layer on the first substrate does not overlap with the orthographic projection of the signal line area on the first substrate.

[0032] Accordingly, this disclosure also provides a display device, including the display panel provided in the embodiments of this disclosure. Attached Figure Description

[0033] Figure 1 This is a plan view of a display panel provided in an embodiment of the present disclosure;

[0034] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;

[0035] Figure 3 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0036] Figure 4 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0037] Figure 5A One of the orthographic projection shapes of the first spacer on the array substrate;

[0038] Figure 5B One of the orthographic projection shapes of the first spacer on the array substrate;

[0039] Figure 5C One of the orthographic projection shapes of the first spacer on the array substrate;

[0040] Figure 5D One of the orthographic projection shapes of the first spacer on the array substrate;

[0041] Figure 5E One of the orthographic projection shapes of the first spacer on the array substrate;

[0042] Figure 5F One of the orthographic projection shapes of the first spacer on the array substrate;

[0043] Figure 6 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0044] Figure 7 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "comprising" or "including," and similar terms as used in this disclosure, mean that an element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0047] As used in this disclosure, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0048] As used in this disclosure, "parallel," "perpendicular," and "equal" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein an acceptable deviation range for approximate parallelism may be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, wherein an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 10% of either one.

[0049] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0050] This disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, for clarity, the thickness of layers and the area of ​​regions are enlarged. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0051] In this disclosure, circles, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined, but can be approximate circles, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances may exist, and chamfers, curved edges, and other deformations may exist.

[0052] In the LCD panel industry, oxide technology, copper process technology, and BCE (back trench etch) device structures are widely used. Oxide panels, with their high mobility and low leakage current, are widely used in high refresh rate and low-frequency display applications. Copper process technology offers significant advantages in reducing metal resistance, which is crucial for high refresh rates and low power consumption. BCE devices can reduce the number of processes and shrink device size, thus offering advantages such as low cost and high resolution. However, moisture intrusion leading to via corrosion in the panel periphery, abnormal CLK (clock signal), and GOA (gate drive circuit) failure are common problems in oxide panels using BCE device structures and copper process technology, resulting in display defects and significant losses at the customer end.

[0053] To address the aforementioned problems, embodiments of this disclosure provide a display panel, such as... Figure 1 As shown, Figure 1 This is a plan view of a display panel provided in an embodiment of the present disclosure. The display panel has a display area AA and a peripheral area BB surrounding the display area AA. The display area AA generally includes multiple pixel units P arranged in an array, that is, the display area AA is used to display content; the peripheral area BB is located on the outer periphery of the display area AA, that is, the peripheral area BB is a non-display area that cannot display content.

[0054] like Figure 2 As shown, Figure 2 for Figure 1The diagram shows a cross-sectional view of the display panel in the peripheral area and part of the display area. The display panel includes an array substrate 1 and a counter substrate 2 disposed in a cell, and a sealing adhesive 3 located in the peripheral area BB and disposed between the array substrate 1 and the counter substrate 2. The sealing adhesive 3 is used to seal the array substrate 1 and the counter substrate 2 in the cell. A liquid crystal layer (not shown) is filled in the area between the array substrate 1 and the counter substrate 2 corresponding to the display area AA.

[0055] like Figure 2 As shown, the array substrate 1 includes a first substrate 11 and a signal line region 12 and a gate driving circuit region 13 (GOA region) disposed on the side of the first substrate 11 facing the opposing substrate 2 and corresponding to the peripheral region BB. The gate driving circuit region 13 is located between the signal line region 12 and the display region AA. The array substrate 1 also includes multiple gate lines and multiple data lines disposed on the side of the first substrate 11 facing the opposing substrate 2 and corresponding to the display region AA. The multiple gate lines and multiple data lines are insulated and intersected to define multiple pixel units P. The pixel unit P includes a thin film transistor and a pixel electrode. The gate lines are electrically connected to the gate of the thin film transistor, the data lines are electrically connected to the source of the thin film transistor, and the pixel electrode is electrically connected to the drain of the thin film transistor. The array substrate also has a common electrode corresponding to the pixel electrode.

[0056] like Figure 2 As shown, the gate drive circuit region 13 is located closer to the display area AA. This region contains the gate drive circuit, which sequentially provides scan signals to multiple gate lines during the driving phase. Upon receiving the scan signal, the gate lines turn on the thin-film transistors electrically connected to them, i.e., the source and drain of the thin-film transistors are turned on, providing signals from the data lines to the pixel electrodes. The signal line region 12 contains signal lines electrically connected to the gate drive circuit. These signal lines typically include the start signal line STV, the clock signal line CLK, and high / low level signal lines VGH / VGL. These signal lines generally use a copper process. CLK typically spans other signal lines and is electrically connected to the gate drive circuit. Therefore, the gate drive circuit region 13 includes a signal line overlap area. Furthermore, the gate drive circuit region 13 also includes organic insulating layer (PLN) vias to allow signal lines from different layers to overlap. Consequently, external moisture can easily penetrate, leading to corrosion of the overlap vias, abnormal CLK, and gate drive circuit failure.

[0057] like Figure 2 As shown, the orthographic projection of the sealant 3 on the first substrate 11 at least partially overlaps with the orthographic projection of the signal line area 12 on the first substrate 11, but does not overlap with the orthographic projection of the gate drive circuit area 12 on the first substrate 11. This is because, in order to reduce the bezel, the sealant 3 will cover the signal line area 12, and the gate drive circuit area 12 is generally provided with a planarization layer. If the sealant 3 covers the gate drive circuit area 1, it will result in a larger cell thickness of the display panel.

[0058] like Figure 2 As shown, the display panel further includes: a first spacer layer 4 disposed within the sealing adhesive 3, and a second spacer layer 5 disposed between the array substrate 1 and the opposing substrate 2; the orthographic projection of the first spacer layer 4 on the first substrate 11 at least partially overlaps with the orthographic projection of the signal line area 12 on the first substrate 11. In this embodiment, the orthographic projection of the first spacer layer 4 on the first substrate 11 completely covers the orthographic projection of the signal line area 12 on the first substrate 11. The orthographic projection of the second spacer layer 5 on the first substrate 11 at least partially overlaps with the orthographic projection of the gate drive circuit area 12 on the first substrate 11.

[0059] The display panel provided in this embodiment can replace the silicon balls in the sealant in related technologies by using a first spacer layer in the sealant to maintain cell thickness uniformity. Furthermore, a second spacer is provided in the gate drive circuit area. The first spacer layer in the sealant covering the signal line area and the second spacer layer covering the gate drive circuit area work together to prevent water vapor ions from contacting the signal lines (copper material) in the signal line area. This prevents water vapor ions from accelerating copper growth and causing short circuits at the CLK signal line crossings, thus improving CLK abnormality issues in the copper manufacturing process of the display panel. It also prevents water vapor from entering the gate drive circuit area, preventing device characteristic drift in the gate drive circuit and improving gate drive circuit failure issues.

[0060] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 As shown, the display area AA is generally provided with a main spacer (Main PS) and a sub spacer (Sub PS). The first spacer layer and the second spacer layer of this disclosure can be manufactured in one process with the main spacer and the sub spacer, and the material can be resin.

[0061] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 As shown, the height of the first spacer layer 4 along the thickness direction of the display panel is less than the maximum height of the sealant 3 along the thickness direction of the display panel. This ensures the sealing performance of the sealant while maintaining the thickness of the panel and blocking moisture.

[0062] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2As shown, the array substrate 1 also includes a blank area 14 disposed on the side of the signal line area 12 away from the display area AA. The orthographic projection of the first spacer layer 4 on the first substrate 11 overlaps with the orthographic projection of the blank area 14 on the first substrate 11, and the orthographic projection of the sealant 3 on the first substrate 11 overlaps with the orthographic projection of the blank area 14 on the first substrate 11. This improves the adhesion between the sealant 3 and the array substrate 1, and also enhances the ability of the first spacer layer 4 to block moisture.

[0063] In some embodiments, in the display panel provided in the present disclosure, such as 1 and Figure 2 As shown, the sealing adhesive 3 is a closed structure surrounding the display area AA, and the first spacer layer 4 is surrounding the display area AA. In this way, the first spacer layer 4 can block moisture from the outer perimeter of the display panel, further improving the ability to block moisture and enhancing the reliability of the display panel.

[0064] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 As shown, the first spacer layer 4 and the second spacer layer 3 can be disposed on the side of the array substrate 1 facing the opposing substrate 2. The first spacer layer 4 can be a closed structure surrounding the display area AA to further improve the ability to block moisture.

[0065] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 As shown, the sealant 3 covers at least a portion of the top surface of the first spacer layer 4 on the side away from the first substrate 11, and also covers the side surface of the first spacer layer 4 on the side away from the display area AA. Thus, the outer boundary of both the first spacer layer 4 and the outer boundary of the sealant 3 are located in the blank area 14, and the outer boundary of the first spacer layer 4 is located between the outer boundary of the sealant 3 and the outer boundary of the signal line area 12. While achieving the sealing performance of the sealant 4, the first spacer layer 4 can prevent external moisture from entering from above and around the signal line area 12, further improving its ability to block moisture.

[0066] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 As shown, along the cell thickness direction perpendicular to the display panel, the width W1 of the first spacer layer 4 is smaller than the width W2 of the sealant 3. This avoids the first spacer layer 4 occupying too much space, resulting in an excessively wide peripheral area. Furthermore, it allows the sealant 3 to adhere to the first spacer layer 4, improving its adhesion. Preferably, W1 / W2 ≈ 2 / 3, and W2 can be 800-1500 μm.

[0067] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2As shown, the orthographic projection shape of the second spacer layer 4 on the array substrate 1 can be a planar structure, and the first spacer layer 4 and the second spacer layer 5 can be an integral structure. In this way, the first spacer layer 4 and the second spacer layer 5 can be manufactured using a single patterning process, simplifying the manufacturing process and reducing costs.

[0068] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 As shown, the minimum distance L1 between the inner edge of the sealing adhesive 3 near the display area AA and the outer edge of the second spacer layer 5 away from the display area AA satisfies the following formula:

[0069]

[0070] Wherein, L11 is the positional accuracy of the sealing adhesive 3, L12 is the single-sided width accuracy of the sealing adhesive 3, L13 is the single-sided width accuracy of the second spacer layer 5, and L14 is the positional accuracy of the second spacer layer 5.

[0071] Specifically, since the gate drive circuit region 13 is generally provided with a planarization layer, the overall height of the film layer of the gate drive circuit region 13 is higher than that of the signal line region 12. This disclosure provides an L1 space between the sealing adhesive 3 and the second spacer layer 5 so that the sealing adhesive 3 will not climb over the second spacer layer 5, thus avoiding the case thickness being too thick.

[0072] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 As shown, the display panel also includes a first alignment film 6 located on the side of the second spacer layer 5 facing the opposing substrate 1. The distance d1 between the second spacer layer 5 and the adjacent boundary of the display area AA is greater than the width d2 of the first alignment film 6 covering the sidewall of the second spacer layer 5 near the display area AA (i.e., the width of the portion of the first alignment film 6 extending along the thickness direction of the display panel). This is because the material of the alignment film is generally PI. By setting d1 > d2, a certain amount of stacking space can be reserved for PI to prevent the PI stacking position from covering the display area AA and affecting the electric field at the edge of the display area AA.

[0073] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 As shown, the array substrate 1 also includes a common electrode line lead area 15 located between the gate driving circuit area 13 and the display area AA. A common electrode line (COM line) electrically connected to the common electrode is disposed within the common electrode line lead area 15. The orthographic projection of the second spacer layer 5 on the array substrate 1 does not overlap with the orthographic projection of the common electrode line lead area 15 on the array substrate 1. In this way, the common electrode line lead area 15 can serve as a PI stacking area, preventing the PI stacking location from covering the display area AA while reducing the width of the surrounding area.

[0074] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 As shown, the signal line area 12, gate drive circuit area 13, common electrode lead area 15, and display area AA include a first metal layer (e.g., gate metal layer), a first insulating layer (e.g., gate insulating layer), a second metal layer (e.g., source / drain metal layer), a second insulating layer (e.g., passivation layer), and a first conductive layer (e.g., common electrode layer) sequentially stacked between the first substrate 11 and the second spacer layer 5. The array substrate 1 also includes an organic insulating layer 7 located between the second metal layer and the second insulating layer. Since the sealing adhesive 3 generally covers the signal line area 12, in order to avoid the cell thickness being too high, the orthographic projection of the organic insulating layer 7 on the first substrate 11 does not overlap with the orthographic projection of the signal line area 12 on the first substrate 11.

[0075] In some embodiments, in the display panel provided in the present disclosure, such as Figure 2 As shown, the opposing substrate 2 can be a color filter substrate (CF) with a color filter and a black matrix BM, but it is not limited to this.

[0076] Specifically, such as Figure 2 As shown, the opposing substrate 2 includes: a second substrate 21, a black matrix BM and multiple filters (not shown) located on the side of the second substrate 21 facing the array substrate 1, and a second alignment film 8 located on the side of the black matrix BM and multiple filters facing the array substrate 1; the orthographic projection of the second alignment film 8 on the first substrate 11 does not overlap with the orthographic projection of the signal line area 12 on the first substrate 11, and the liquid crystal layer is located between the first alignment film 6 and the second alignment film 8. In the display area AA, the black matrix BM is disposed in the gap between adjacent pixel units. On the one hand, the black matrix BM is used to define multiple pixel units to avoid light crosstalk between adjacent pixel units. On the other hand, the black matrix BM is used to block metal signal lines, such as gate lines, data lines, etc., to prevent metal signal lines from reflecting and reduce the reflectivity of the display area; specifically, the black matrix BM includes multiple openings, and each filter is disposed in the corresponding opening. The multiple filters may include a red filter (e.g., a red color film), a green filter (e.g., a green color film), and a blue filter (e.g., a blue color film).

[0077] In some embodiments, in the display panel provided in the present disclosure, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure. Figure 3 and Figure 2 The difference lies in the structure of the second septum layer 5. Figure 3The second spacer layer 5 includes at least one second spacer 51 spaced apart from each other. At least one surface of the organic insulating layer 7 via and the signal line overlap area of ​​the gate drive circuit region 13 is covered by the second spacer 51. Since the organic insulating layer 7 via is prone to moisture entry, this embodiment uses the second spacer 51 to cover the organic insulating layer 7 via, preventing moisture from entering the organic insulating layer 7 via. In addition, the organic insulating layer 7 in the signal line overlap area is generally removed to prevent electrochemical corrosion from causing the inorganic insulating layer to break down and to avoid short traces between different layers. That is, only the inorganic insulating layer (e.g., passivation layer) is generally retained in the signal line overlap area. In this way, the signal line overlap area is also equivalent to having an organic insulating layer 7 via. Therefore, this embodiment can also use the second spacer 51 to cover the signal line overlap area to prevent moisture from entering the signal line overlap area.

[0078] In some embodiments, in the display panel provided in the present disclosure, such as Figure 3 As shown, the size of the second spacer 51 can be larger than the size of the via in the organic insulating layer 7, and the size of the second spacer 51 can be larger than the size of the signal line overlap area. In this way, the second spacer 51 can completely cover the via in the organic insulating layer 7 and the signal line overlap area, improving the ability to block moisture.

[0079] In some embodiments, in the display panel provided in the present disclosure, such as Figure 3 As shown, the shape of the via is generally square or circular. Therefore, the orthographic projection shape of the second spacer 51 on the first substrate 1 can be circular or square, but is not limited to this. It needs to be designed according to the shape of the overlap area between the via and the signal line in the organic insulating layer 7.

[0080] In some embodiments, in the display panel provided in the present disclosure, such as Figure 3 As shown, the dimension L2 of the second spacer 51 satisfies the following formula:

[0081]

[0082] Wherein, L21 is the size of the via or signal line overlap area of ​​the organic insulating layer 7, L22 is the width accuracy of the second spacer, and L23 is the width accuracy of the via or signal line overlap area of ​​the organic insulating layer 7.

[0083] With L2 > L21, the second spacer 51 can completely cover the via or signal line overlap area of ​​the organic insulating layer 7, improving the ability to block moisture.

[0084] It should be noted that the above dimensions can be defined according to the shape of the second spacer 51, the organic insulating layer 7, the via, and the overlapping area of ​​the signal line. The definition of the dimensions will be different depending on the shape of the via and the overlapping area. For example, when the shape of the via and the overlapping area is circular, the dimension can represent the diameter of the circle; when the shape of the via and the overlapping area is square, the dimension insulation represents the diagonal length of the square, and so on.

[0085] In some embodiments, in the display panel provided in the present disclosure, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure. Figure 4 and Figure 1 The difference lies in the different structures of the first septum layer 4 and the second septum layer 5. Figure 4 The first spacer layer 4 includes a plurality of first spacers 41 spaced apart from each other. The sealant 3 contacts the array substrate 1 through the gaps between adjacent first spacers 41. In this way, the plurality of first spacers 41 can extend the path of water vapor ions intruding through the sealant 3, and can increase the contact area between the sealant 3 and the array substrate 1, thereby increasing the adhesion of the sealant and improving the sealing performance.

[0086] In some embodiments, in the display panel provided in the present disclosure, such as Figure 4 As shown, the orthographic projection shape of the first spacer 41 on the array substrate 1 can be, but is not limited to, circular, elliptical, square, strip-shaped, or mesh-like. Specifically, as... Figure 5A and Figure 5B As shown, the orthographic projection shape of the first spacer 41 on the array substrate 1 can be circular; as Figure 5C As shown, the orthographic projection shape of the first spacer 41 on the array substrate 1 can be elliptical; as Figure 5D and Figure 5E As shown, the orthographic projection shape of the first spacer 41 on the array substrate 1 can be strip-shaped; such as Figure 5F As shown, the orthographic projection shape of the first spacer 41 on the array substrate 1 can be a mesh.

[0087] In some embodiments, in the display panel provided in the present disclosure, such as Figure 5A , Figure 5B and Figure 5D As shown, multiple first spacers 41 can be arranged in an array along the row and column directions of the display panel, and the number and arrangement density can be set as needed.

[0088] In some embodiments, in the display panel provided in the present disclosure, such as Figure 5CAs shown, multiple first spacers 41 can be arranged at a certain angle (e.g., 45°) to the row direction, and the number and arrangement density can be set as needed.

[0089] In some embodiments, in the display panel provided in the present disclosure, such as Figure 5F As shown, multiple first spacers 41 can be arranged in multiple rows, with the first spacers 41 in adjacent rows being staggered to form a triangular arrangement.

[0090] In some embodiments, in the display panel provided in the present disclosure, such as Figure 4 As shown, the second spacer layer 5 may include a plurality of second spacers 51 arranged at intervals. The plurality of second spacers 51 arranged at intervals can also extend the path of water vapor ions invading through the sealing adhesive 3, thus achieving a better effect in blocking water vapor.

[0091] In some embodiments, in the display panel provided in the present disclosure, such as Figure 4 As shown, the display area AA includes multiple main spacers (not shown) spaced apart from each other. The shape of the second spacer 51 can be the same as that of the main spacers, and the size of the second spacer 51 can be the same as that of the main spacers. Furthermore, the arrangement period of the multiple second spacers 51 can be the same as that of the multiple main spacers. This simplifies the manufacturing process and reduces costs by producing the second spacers 51 and the main spacers in a single patterning process.

[0092] In some embodiments, in the display panel provided in the present disclosure, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure. Figure 6 and Figure 4 The difference lies in the different positions of the first spacer layer 4 and the second spacer layer 5. Figure 6 The first spacer layer 4 and the second spacer layer 5 are disposed on the side of the opposing substrate 2 facing the array substrate 1, and the structures of the first spacer layer 4 and the second spacer layer 5 are both similar to those of the array substrate 1. Figure 4 Similarly, the second spacer layer 5 is located on the side of the black matrix BM facing the array substrate 1 in the signal line region 12, and the second spacer layer 5 is located between the black matrix BM and the second alignment film 8 in the gate drive circuit region 13. The sealant 3 contacts the opposing substrate 2 through the gap between adjacent first spacers 41.

[0093] It should be noted that other essential components of the display panel are all known to those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0094] Based on the same inventive concept, this disclosure also provides a display device, including the display panel described above. Since the principle by which this display device solves the problem is similar to that of the display panel described above, the implementation of the display device provided in this disclosure can refer to the implementation of the display panel described above, and repeated details will not be elaborated further.

[0095] In some embodiments, the display device provided in this disclosure further includes a backlight module located on the light-incident side of the display panel.

[0096] In some embodiments, the backlight module in the display device provided in this disclosure can be a direct-lit backlight module or an edge-lit backlight module. Optionally, an edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. A direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature light-emitting diodes (Mini LEDs, Micro LEDs, etc.).

[0097] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0098] In specific implementation, the display device provided in the embodiments of this disclosure is a liquid crystal display device. The liquid crystal display device also includes other necessary components and parts, such as a housing, a main circuit board, a power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here and should not be regarded as a limitation of this disclosure.

[0099] In specific implementation, the display device provided in the embodiments of this disclosure may be a full-screen display device or a flexible display device, etc., and is not limited thereto.

[0100] In specific implementation, the display device provided in the embodiments of this disclosure can be as follows: Figure 7 The image shows a full-screen mobile phone. Of course, the display device provided in this embodiment can also be any product or component with display function, such as a tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure. This display device includes, but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in this embodiment. In other words, the display device provided in this embodiment may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0101] This disclosure provides a display panel and display device in which a first spacer layer disposed in the sealant can replace the silicon balls disposed in the sealant in related technologies, thereby maintaining cell thickness uniformity. Furthermore, this disclosure also provides a second spacer in the gate drive circuit area. Thus, the first spacer layer disposed in the sealant and covering the signal line area, together with the second spacer layer covering the gate drive circuit area, can prevent water vapor ions from contacting the signal lines (copper material) in the signal line area, preventing water vapor ions from accelerating copper growth and causing short circuits at the CLK signal line crossing points, thus improving CLK abnormality problems in the copper manufacturing process of the display panel. It can also prevent water vapor from entering the gate drive circuit area, preventing device characteristic drift in the gate drive circuit and improving gate drive circuit failure problems.

[0102] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0103] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, The display panel has a display area and a peripheral area surrounding the display area, and comprises an array substrate and a counter substrate arranged in a cell, and a sealant arranged in the peripheral area and between the array substrate and the counter substrate. The array substrate comprises a first substrate, a signal line area and a gate drive circuit area arranged on a side of the first substrate facing the counter substrate and corresponding to the peripheral area, and the gate drive circuit area is located between the signal line area and the display area. A normal projection of the sealant on the first substrate at least partially overlaps a normal projection of the signal line area on the first substrate, and does not overlap a normal projection of the gate drive circuit area on the first substrate. The display panel further comprises a first spacer layer arranged in the sealant, and a second spacer layer arranged between the array substrate and the counter substrate. A normal projection of the first spacer layer on the first substrate at least partially overlaps a normal projection of the signal line area on the first substrate, and a normal projection of the second spacer layer on the first substrate at least partially overlaps a normal projection of the gate drive circuit area on the first substrate.

2. The display panel of claim 1, wherein, A height of the first spacer layer along a thickness direction of the display panel is less than a maximum height of the sealant along the thickness direction of the display panel.

3. The display panel of claim 2, wherein, The array substrate further comprises a blank area arranged on a side of the signal line area away from the display area, a normal projection of the first spacer layer on the first substrate partially overlaps a normal projection of the blank area on the first substrate, and a normal projection of the sealant on the first substrate partially overlaps a normal projection of the blank area on the first substrate.

4. The display panel of claim 3, wherein, The sealant is arranged in a closed structure surrounding the display area, and the first spacer layer is arranged in a closed structure surrounding the display area.

5. The display panel of claim 4, wherein, The first spacer layer and the second spacer layer are arranged on a side of the array substrate facing the counter substrate.

6. The display panel of claim 5, wherein, The first spacer layer is arranged in a closed structure surrounding the display area.

7. The display panel of claim 6, wherein, The sealant covers at least part of a top surface of the first spacer layer away from the first substrate, and covers a side surface of the first spacer layer away from the display area.

8. The display panel of claim 7, wherein, Along a thickness direction perpendicular to the display panel, a width of the first spacer layer is less than a width of the sealant.

9. The display panel of claim 8, wherein, A normal projection of the second spacer layer on the array substrate is in a planar structure.

10. The display panel of claim 9, wherein, The first spacer layer and the second spacer layer are in an integrated structure.

11. The display panel of claim 10, wherein, A minimum distance L1 between an inner side edge of the sealant close to the display area and an outer side edge of the second spacer layer away from the display area satisfies the following formula: ； wherein, L11 is a position accuracy of the sealant, L12 is a single-side width accuracy of the sealant, L13 is a single-side width accuracy of the second spacer layer, and L14 is a position accuracy of the second spacer layer.

12. The display panel of claim 8, wherein, The gate driving circuit region comprises an organic insulating layer via hole and a signal line overlap region, the second spacer layer comprises at least one second spacer arranged at intervals, and at least one surface of the organic insulating layer via hole and the signal line overlap region covers the second spacer.

13. The display panel of claim 12, wherein, The size of the second spacer is greater than the size of the organic insulating layer via hole, and the size of the second spacer is greater than the size of the signal line overlap region.

14. The display panel of claim 13, wherein, The shape of the orthographic projection of the second spacer on the first substrate comprises a circle or a square.

15. The display panel of claim 14, wherein, The size L2 of the second spacer satisfies the following formula: ； wherein L21 is the size of the organic insulating layer via hole or the signal line overlap region, L22 is the width accuracy of the second spacer, and L23 is the width accuracy of the organic insulating layer via hole or the signal line overlap region.

16. The display panel of any of claims 5-15, wherein, The display panel further comprises a first alignment film on the side of the second spacer layer facing the counter substrate, and the distance between the second spacer layer and the adjacent boundary of the display area is greater than the width of the first alignment film covering the side wall of the second spacer layer close to the display area.

17. The display panel of claim 4, wherein, The first spacer layer and the second spacer layer are arranged on the side of the counter substrate facing the array substrate.

18. The display panel of claim 5 or 17, wherein, The first spacer layer comprises a plurality of first spacers arranged at intervals, and the sealant contacts the array substrate or the counter substrate through the gap between adjacent first spacers.

19. The display panel of claim 18, wherein, The orthographic projection shape of the first spacer on the array substrate is a circle, an ellipse, a square, a strip, or a net.

20. The display panel of claim 19, wherein, The second spacer layer comprises a plurality of second spacers arranged at intervals.

21. The display panel of claim 20, wherein, The display area comprises a plurality of main spacers arranged at intervals, the shape and size of the second spacer are the same as the shape and size of the main spacer, and the arrangement period of the plurality of second spacers is the same as the arrangement period of the plurality of main spacers.

22. The display panel of any of claims 1-15, 17, 19-21, wherein, The array substrate further comprises a common electrode line lead region between the gate driving circuit region and the display area, and the orthographic projection of the second spacer layer on the array substrate does not overlap with the orthographic projection of the common electrode line lead region on the array substrate.

23. The display panel of claim 22, wherein, The signal line region, the gate driving circuit region, the common electrode line lead region, and the display area comprise a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a first conductive layer arranged in sequence between the first substrate and the second spacer layer, and the array substrate further comprises an organic insulating layer between the second metal layer and the second insulating layer, and the orthographic projection of the organic insulating layer on the first substrate does not overlap with the orthographic projection of the signal line region on the first substrate.

24. A display device comprising: The display panel comprises the display panel according to any one of claims 1-23. The display panel comprises the display panel according to any one of claims 1-23.

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