Heterogeneous intelligent interaction control terminal

Abstract

The utility model discloses a heterogeneous intelligent interaction control terminal which comprises a main processing module and a power management module. The main processing module adopts a heterogeneous computing architecture and comprises a general processing unit and three special processing units, namely a video coding and decoding engine, a graphic processing engine and an AI acceleration engine. The universal processing unit is connected with the special processing units through the independent on-chip bus, the special processing units directly exchange data through the shared bus, and the CPU transfer bottleneck is avoided. The power management module comprises four independent BUCK voltage reduction power supply branches which provide independent and adjustable power supplies for the processing units respectively. A video identification branch of the man-machine interaction module adopts a three-stage transient protection circuit composed of a TVS tube group, a current-limiting resistor and a protection inductor. According to the utility model, the multi-task parallel processing performance is optimized through a heterogeneous architecture, the industrial environment adaptability is improved through multi-stage protection, and the system is especially suitable for the fields of smart cities, electric power grids, industrial Internet of Things and the like.

Description

Technical Field

[0001] This utility model discloses a control terminal, especially a heterogeneous intelligent interactive control terminal. Background Technology

[0002] With the rapid development of Industry 4.0 and intelligent manufacturing, industrial control terminals, as key nodes connecting the physical and digital worlds, directly impact the operational efficiency and intelligence level of the entire industrial system. Especially in emerging application scenarios such as smart cities, industrial IoT, and smart power systems, traditional control terminals can no longer meet the complex demands for real-time performance, parallel processing capabilities, and multimodal interaction. Modern industrial scenarios require terminal devices to simultaneously handle multiple human-machine interaction methods such as video monitoring, voice control, and touch operation, and to complete complex data processing and decision-making tasks within millisecond response times. This demand for multi-task parallel processing is driving the development of control terminals towards higher performance and greater intelligence.

[0003] Currently, most intelligent control terminals on the market adopt general-purpose processor solutions based on x86 or ARM architecture. These terminals typically use a single CPU as the core processing unit, improving performance by increasing the clock speed and the number of cores. In terms of power supply design, most employ a centralized power supply architecture, using a single or dual-channel DC-DC converter to power the entire system. Human-machine interface protection usually employs simple RC filtering or single-stage TVS protection. Expansion functions are mainly implemented through general-purpose interfaces such as USB and serial ports, lacking dedicated industrial expansion bus designs. While some high-end products integrate GPUs or DSPs as coprocessors, these dedicated processing units still require task scheduling and data transfer through the CPU, essentially remaining a CPU-centric homogeneous architecture.

[0004] However, existing technical solutions reveal two key problems in practical applications: a data flow bottleneck in handling heterogeneous tasks, and in terms of electromagnetic compatibility in industrial settings, existing single-level protection designs cannot effectively cope with complex transient interference. Utility Model Content

[0005] The purpose of this utility model is to provide a heterogeneous intelligent interactive control terminal, in order to solve the above-mentioned problems existing in the prior art.

[0006] Technical solution: A heterogeneous intelligent interactive control terminal, comprising:

[0007] The main processing module includes a general-purpose processing unit and multiple dedicated processing units;

[0008] The dedicated processing unit includes a video encoding / decoding engine, a graphics processing engine, and an AI acceleration engine, which interact with each other via a shared bus.

[0009] The general-purpose processing unit is bidirectionally connected to the video encoding and decoding engine via the first internal bus, bidirectionally connected to the graphics processing engine via the second internal bus, and bidirectionally connected to the AI ​​acceleration engine via the third internal bus.

[0010] The power management module is electrically connected to the main processing module and provides independent power to the general-purpose processing unit and each dedicated processing unit.

[0011] According to one aspect of this application, the power management module includes:

[0012] Power management chip;

[0013] Four independent BUCK step-down power supply branches provide independent power to the general processing unit, video encoding and decoding engine, graphics processing engine and AI acceleration engine respectively;

[0014] The output of each BUCK step-down power supply branch is connected to the corresponding feedback pin of the power management chip through a feedback loop.

[0015] According to one aspect of this application, each BUCK step-down power supply branch includes:

[0016] An energy storage inductor connected to the switch output pin of a power management chip;

[0017] A filter capacitor bank connected to the output terminal of the energy storage inductor;

[0018] A resistor network is connected to the output terminal of the energy storage inductor to form a voltage divider feedback network. The voltage divider output terminal of the resistor network is connected to the corresponding feedback pin of the power management chip.

[0019] According to one aspect of this application, a human-computer interaction module is also included, the human-computer interaction module comprising:

[0020] The video recognition branch is connected to the video codec engine via the video data bus;

[0021] The touch control branch and the voice recognition branch are connected to the general processing unit via the peripheral bus.

[0022] According to one aspect of this application, the video recognition branch includes:

[0023] Video input interface;

[0024] The transient protection circuit is located between the video input interface and the video codec engine, and includes a parallel TVS diode group and a series protection inductor.

[0025] According to one aspect of this application, the transient protection circuit includes:

[0026] The first TVS diode and the second TVS diode are respectively connected to the data pins of the video input interface;

[0027] The first protection resistor and the second protection resistor are connected in series between the first TVS transistor, the second TVS transistor and the subsequent circuit, respectively.

[0028] The protection inductor has its first and second terminals connected in parallel with the first and second protection resistors, respectively.

[0029] According to one aspect of this application, an expansion bus module is also included, the expansion bus module comprising:

[0030] Bus interface connected to the general-purpose processing unit;

[0031] At least two standardized expansion slots support hot-swapping of functional modules.

[0032] According to one aspect of this application, the functional modules supported by the expansion slot include:

[0033] One or more combinations of local communication module, wireless communication module, RS-485 communication module, remote signaling pulse module and control output module.

[0034] According to one aspect of this application, a watchdog module is also included, wherein the reset output of the watchdog module is connected to the reset pin of the general-purpose processing unit, and the feed input of the watchdog module is connected to the GPIO pin of the general-purpose processing unit.

[0035] Beneficial effects include optimized multi-task parallel processing performance through heterogeneous architecture and improved adaptability to industrial environments through multi-level protection, making it particularly suitable for smart cities, power grids, industrial IoT and other fields. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the wireframe structure of this utility model.

[0037] Figure 2 This is a circuit diagram of the power management module of the present invention.

[0038] Figure 3 This is a circuit diagram of the second power management module using the new type.

[0039] Figure 4 This is a circuit diagram of the novel display touch module.

[0040] Figure 5 This is a partial circuit diagram of the video recognition module using this novel technology.

[0041] Figure 6 This is a wireframe diagram of the control module of this novel invention.

[0042] Figure 7 This is a schematic diagram of the topological structure of Embodiment 2 of this utility model.

[0043] Figure 8 This is a schematic diagram of the topological structure of Embodiment 3 of this utility model.

[0044] Figure 9 This is a schematic diagram of the topological structure of Embodiment 4 of this utility model.

[0045] Figure 10 This is a schematic diagram of the topological structure of Embodiment 5 of this utility model.

[0046] Figure 11 This is a schematic diagram of the topological structure of Embodiment Six of this utility model.

[0047] Figure 12 This is a schematic diagram of the topological structure of Embodiment 7 of this utility model.

[0048] Figure 13 This is a schematic diagram of the topological structure of Embodiment 8 of this utility model.

[0049] Figure 14 This is a schematic diagram of the topological structure of Embodiment 9 of this utility model.

[0050] Figure 15 This is a schematic diagram of the topological structure of Embodiment 10 of this utility model.

[0051] Figure 16 This is a schematic diagram of the topological structure of Embodiment Eleven of this utility model. Detailed Implementation

[0052] like Figures 1 to 16 The diagram illustrates the topology of various embodiments of this utility model.

[0053] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not intended to limit this utility model.

[0054] Example 1: This example provides a heterogeneous intelligent interactive control terminal, which is particularly suitable for complex control needs in fields such as industrial control, power electronics, and smart grids.

[0055] This terminal adopts a heterogeneous computing architecture, breaking through the limitations of traditional terminals that rely on a single processor architecture. The main processing module, as the core of the entire system, integrates a general-purpose processing unit and multiple dedicated processing units. The general-purpose processing unit uses a quad-core ARM architecture with a clock speed of up to 1.5GHz, responsible for the overall scheduling and control logic processing of the system. The dedicated processing units include a video encoding / decoding engine, a graphics processing engine, and an AI acceleration engine, each optimized for specific tasks.

[0056] In this embodiment, the general-purpose processing unit establishes bidirectional connections with each dedicated processing unit through three independent on-chip buses. The first on-chip bus adopts the AXI protocol, with a bandwidth of 128 bits, connects to the video codec engine, and supports 4K@30fps video processing capability; the second on-chip bus connects to the graphics processing engine, supporting OpenGL ES 3.2 graphics rendering; and the third on-chip bus connects to the AI ​​acceleration engine, providing 4 TOPS of AI computing power.

[0057] More importantly, the three dedicated processing units interact directly via a shared bus, avoiding the traditional model where data needs to be relayed through a general-purpose processing unit. For example, when the system performs intelligent video analysis, the raw video data decoded by the video codec engine can be directly transmitted to the AI ​​acceleration engine for target recognition via the shared bus. The recognition result is then transmitted to the graphics processing engine for visualization rendering. The entire process does not require the involvement of a general-purpose processing unit, significantly improving processing efficiency.

[0058] To support the efficient operation of the heterogeneous architecture, the power management module adopts a multi-path independent power supply scheme. The general-purpose processing unit operates at a core voltage of 1.2V, with a typical power consumption of 2W; the video encoding and decoding engine requires a power supply of 1.8V, with a peak power consumption of up to 3W; the graphics processing engine uses a power supply of 0.9V, with a power consumption range of 1-2.2W; and the AI ​​acceleration engine uses an ultra-low voltage power supply of 0.9V, keeping power consumption below 1.5W while ensuring performance. Through independent power supplies, each processing unit can dynamically adjust its operating state according to the actual load, achieving an optimal balance between performance and power consumption.

[0059] According to one aspect of this application, it can also be a star-shaped heterogeneous architecture.

[0060] All dedicated processing units are connected in a star topology around the general-purpose processing unit. In this architecture, the general-purpose processing unit acts as the central controller and is connected to the video encoding / decoding engine, graphics processing engine, and AI acceleration engine via independent point-to-point buses. There are no direct physical connection paths between the dedicated processing units.

[0061] In practice, the general-purpose processing unit integrates multiple bus interface controllers, each managing an independent bus channel. Taking video intelligent analysis applications as an example, when the system needs to perform AI recognition on input video and display the results, the data flow is as follows: First, the raw video data enters the video codec engine through the video interface. The decoded YUV format data is then transmitted to the buffer of the general-purpose processing unit via its connected bus. Next, the general-purpose processing unit forwards this data to the AI ​​acceleration engine for target recognition processing via another bus. After completing the calculation, the AI ​​acceleration engine returns the recognition result to the general-purpose processing unit. Finally, the general-purpose processing unit sends the recognition result and the raw image data together to the graphics processing engine for rendering output via a third bus. Throughout this process, each frame of image data needs to be transmitted at least six times on the bus, requiring the general-purpose processing unit to manage a large number of data transfer tasks. When the system processes 4K@30fps high-definition video, data transfer alone consumes approximately 40% of the general-purpose processing unit's processing capacity, severely limiting the overall system performance.

[0062] When the system needs to perform intelligent video analysis, the video data must first be read by the CPU from the video interface, then transmitted to the GPU for image processing. The processing result is returned to the CPU and then forwarded to the AI ​​accelerator for recognition. Finally, the recognition result must be sent to the display module by the CPU. Throughout this process, the CPU becomes the bottleneck for data exchange, which not only increases processing latency but also causes a large amount of bus bandwidth occupation and power waste. Secondly, video signal lines in industrial environments are often subjected to complex electromagnetic interference caused by lightning strikes, motor start-stop, etc. This interference is characterized by fast rise time (nanosecond level), high energy (kilovolt level), and wide spectrum (from DC to GHz). Simple TVS protection can often only clamp the voltage but cannot effectively suppress high-frequency components and limit transient current, so residual interference may still damage sensitive circuits in subsequent stages.

[0063] According to one aspect of this application, it can also be a ring-shaped heterogeneous architecture.

[0064] The ring-based heterogeneous architecture connects all processing units in series via a ring bus, forming a closed loop. In this topology, the general-purpose processing unit, video codec engine, graphics processing engine, and AI acceleration engine are sequentially connected to the ring bus. Each processing unit is equipped with a ring bus interface, which can inject data into the loop or extract data from the loop.

[0065] Ring buses typically employ token rings or time-slot-based access mechanisms. Taking token rings as an example, a special control token circulates within the ring, and only the processing unit that acquires the token can send data. Data packets flow in a fixed direction within the ring, with each node checking the destination address of the packet; if it's addressed to itself, it accepts it; otherwise, it forwards it to the next node. For instance, when a video codec engine needs to send data to an AI acceleration engine, if the two are adjacent in the ring, the data only needs to travel one hop; however, if they are separated by other processing units, the data needs to be forwarded through multiple nodes. This forwarding mechanism introduces unpredictable transmission delays; in the worst case, data may need to travel through a large portion of the ring to reach its destination. Furthermore, the bandwidth of the ring bus is shared by all nodes, easily leading to congestion when multiple processing units simultaneously have high data transmission demands. More seriously, if any node or connection in the ring fails, the entire communication system will be paralyzed, which is unacceptable for high-reliability applications such as industrial control.

[0066] According to one aspect of this application, it can also be a cross-switch matrix architecture.

[0067] The crossbar switch matrix architecture uses a central switching matrix to achieve arbitrary interconnection between all processing units. At the core of this architecture is a 4×4 crossbar switch array. A general-purpose processing unit and three dedicated processing units are connected to the input and output ports of the switching matrix, respectively. By configuring the internal connections of the switching matrix, a direct communication channel can be established between any two processing units.

[0068] The crossbar switch matrix internally consists of numerous 2-to-1 multiplexers, forming a fully connected switching network. When a connection needs to be established, the central arbiter configures the appropriate multiplexer according to the requests of each processing unit, forming the required connection path. The biggest advantage of this architecture is that it can simultaneously support parallel communication between multiple pairs of processing units. For example, while the video codec engine transmits data to the AI ​​acceleration engine, the general-purpose processing unit can also send control commands to the graphics processing engine, and the two communication processes do not interfere with each other. However, implementing a 4×4 high-speed crossbar switch matrix requires 16 cross points, each requiring complex multiplexing and buffering circuitry. When the bus width is 128 bits and the operating frequency is 500MHz, the number of transistors in the entire switching matrix exceeds one million, and the power consumption can reach several watts. More importantly, as the number of processing units increases, the complexity of the switching matrix increases quadratically, making this solution unacceptable in terms of both cost and power consumption.

[0069] According to one aspect of this application, it can also be a layered heterogeneous architecture.

[0070] The layered heterogeneous architecture divides the system into two layers: a control plane and a data plane. General-purpose processing units reside in the control plane, responsible for system scheduling and management; dedicated processing units reside in the data plane, responsible for high-speed data processing. The two planes are connected through different bus systems: the control plane uses a low-speed but reliable control bus, while the data plane uses a high-speed data bus.

[0071] In its implementation, the control bus employs the traditional AHB or APB protocol, operating at a lower frequency but supporting complex transaction processing. The data bus uses a specially optimized streaming protocol, supporting high-bandwidth batch data transmission. The general-purpose processing unit (GPU) sends task descriptors, including data source address, target address, and processing parameters, to each dedicated processing unit via the control bus. Upon receiving a task, the dedicated processing unit autonomously reads, processes, and writes data back via the data bus, without the involvement of the general-purpose processing unit. This design achieves complete separation of control and data flows, significantly reducing the burden on the general-purpose processing unit. However, maintaining two independent bus systems increases the complexity of design and verification. More importantly, synchronization between the control plane and data plane becomes a new challenge, especially when handling hybrid tasks requiring frequent interaction; the communication overhead across planes may negate the performance advantages of layering.

[0072] According to one aspect of this application, it can also be a partially interconnected heterogeneous architecture.

[0073] Partially interconnected heterogeneous architecture is a compromise that selectively adds direct connections between some dedicated processing units while maintaining the basic star topology. A typical design establishes dedicated channels between processing unit pairs that interact most frequently with data, such as adding a high-speed data channel between the video codec engine and the AI ​​acceleration engine, because the data traffic between these two units is the largest in most video intelligent analytics applications.

[0074] This architecture is relatively simple to implement, requiring only the addition of a small number of point-to-point connections to a star topology. These new connections can utilize specially optimized protocols, such as simplified handshake mechanisms and flow control, to achieve higher transmission efficiency. In practical applications, when performing video AI analysis, decoded image data can be directly transmitted from the video codec engine to the AI ​​acceleration engine, avoiding the need for intermediaries in general processing units. Tests show that this optimization alone can reduce video processing latency by approximately 30%. However, the limitations of this architecture are also apparent: First, the design phase requires accurate prediction of the system's data flow patterns; incorrect predictions result in limited performance improvements. Second, the system's scalability is limited; adding new processing units may necessitate a redesign of the interconnect structure. Finally, for applications with highly variable data flow patterns, fixed interconnect components may not be fully effective.

[0075] The heterogeneous architecture, combining an independent on-chip bus with a shared bus between dedicated processing units, integrates the advantages of various solutions while avoiding their main drawbacks. This architecture retains the independent control capabilities of general-purpose processing units over each dedicated processing unit, while enabling efficient data exchange between dedicated processing units through a shared bus. It is suitable for the complex and ever-changing application requirements of modern smart terminals, maximizing data processing performance while ensuring system flexibility. Real-world test data shows that in typical 4K video AI analysis applications, compared to traditional star topologies, this solution reduces data transmission latency by 60% and bus bandwidth usage by 70%, fully validating the advanced nature and practicality of this architecture design.

[0076] Example 2: This example details the specific implementation of the BUCK step-down power supply branch in the power management module.

[0077] The core of the power management module is the U500 power management chip, which integrates four independent BUCK controllers with a programmable switching frequency ranging from 500kHz to 2MHz. In this embodiment, it is set to 1MHz to balance efficiency and size. The input voltage range is 4.5V-18V, covering the 5V and 12V power supply standards commonly found in industrial environments.

[0078] The first BUCK circuit supplies power to the general-purpose processing unit. Its circuit composition and operation are as follows:

[0079] The energy storage inductor L500 is a 2.2μH molded inductor with low DCR (20mΩ) and a saturation current of 5A. When the SW1 pin of the power management chip U500 outputs a high level, the input voltage is applied to the inductor L500 through the internal upper MOSFET, storing energy and causing the current to rise linearly. At this time, the filter capacitor bank (C504, C505, C506, C507) supplies power to the load using the stored energy.

[0080] When SW1 switches to a low level, inductor L500 freewheels through the internal synchronous rectifier MOSFET, releasing the stored energy to the load and the filter capacitor bank. Specifically, C504 and C505 use 22μF / 6.3V ceramic capacitors for high-frequency filtering; C506 and C507 use 100μF / 6.3V tantalum capacitors for large-capacity energy storage and low-frequency filtering. This parallel design of ceramic and tantalum capacitors fully utilizes the advantages of both types, achieving ripple suppression across the entire frequency band from kHz to MHz.

[0081] The feedback network consists of a voltage divider circuit composed of resistors R500 (10kΩ) and R502 (5.6kΩ), which proportionally reduces the output voltage before sending it to the FB1 pin. When the output voltage is too high, the FB1 voltage rises, and the controller decreases the duty cycle; conversely, it increases the duty cycle, thereby achieving an accurate output of 1.2V ± 2%.

[0082] When the general-purpose processing unit suddenly enters a high-load state (such as when multiple algorithms are started simultaneously), the current may increase instantaneously to over 3A. At this time, the power management chip U500 detects the overcurrent state through its built-in current detection circuit and immediately enters hiccup mode, periodically attempting to restart, thus avoiding system crashes that may be caused by traditional protection methods.

[0083] Example 3: This example focuses on the transient protection design of the video recognition branch in the human-computer interaction module.

[0084] In industrial environments, video signal lines are often exposed to strong electromagnetic interference. Lightning strikes, electrostatic discharge (ESD), and motor start-up and shutdown can all generate transient high voltages on the signal lines. The protection circuit in this embodiment can withstand Level 4 ESD impacts (contact discharge ±8kV, air discharge ±15kV) according to the IEC61000-4-2 standard.

[0085] The X700 uses a standard HDMI interface for video input, supporting high-definition video input. A 100pF protection capacitor C705 is connected to the power pin to provide high-frequency noise filtering.

[0086] The core protection is achieved using a TVS diode array. The first TVS diode, D701, and the second TVS diode, D702, are 5V bidirectional TVS diodes with a breakdown voltage of 6V and a clamping voltage of 8.5V (under an 8 / 20μs standard lightning strike waveform). During normal operation, when the video signal level is within the range of 0-3.3V, the TVS diodes exhibit a high impedance state (leakage current less than 1μA), having no impact on signal transmission.

[0087] When electrostatic discharge occurs, assume an +8kV ESD pulse is applied to the video data pin. Upon pulse arrival, the TVS diode D701 transitions from a high-resistance state to a low-resistance state in less than 1ns, clamping the voltage at 8.5V. Simultaneously, the series-connected protection resistor R710 (100Ω) limits the transient current, forming a voltage divider network with the TVS diode, further reducing the residual voltage reaching subsequent circuits.

[0088] The protection inductor L700 (10μH) employs a common-mode choke structure, with its first and second terminals connected in parallel with the first protection resistor R710 and the second protection resistor R711, respectively. This connection method allows differential signals to pass smoothly while effectively suppressing common-mode interference (such as ESD). The inductive impedance of the inductor slows down the rise rate of transient current, buying time for the TVS diode to respond and achieving multi-level protection.

[0089] Traditional video interface protection typically uses only a single TVS diode, offering limited protection. This embodiment employs a combination of TVS diode arrays, current-limiting resistors, and common-mode inductors to form a three-level protection network, reducing the residual voltage to below 3V, far below the withstand voltage of the video codec engine (5V), ensuring reliable system operation in harsh electromagnetic environments.

[0090] Example 4 illustrates the specific implementation of the extended bus module and demonstrates the flexible expansion capability of the terminal.

[0091] The expansion bus module is implemented through the External Memory Interface (EMIF) of the general-purpose processing unit, employing a 16-bit parallel bus with an operating frequency of up to 100MHz. The bus interface integrates address decoding logic, supporting addressing of up to eight expansion slots.

[0092] Each standardized expansion slot uses a 96-pin high-density connector, defining a uniform mechanical size (100mm × 80mm) and electrical interface. The slot provides three power supplies: +5V (2A), +3.3V (1A), and +12V (500mA) to meet the power supply requirements of different functional modules.

[0093] The expansion slot supports hot-swapping. The slot connector uses an unequal-length pin design, with the power pin being the longest and making contact first; the ground pin is next; and the signal pin is the shortest and making contact last. This design ensures that power and ground connections are established first during insertion, avoiding inrush current on the signal pins.

[0094] Meanwhile, each slot is equipped with a dedicated hot-swap controller that integrates soft-start circuitry and current limiting functionality. When a module insertion is detected, the controller slowly increases the supply voltage at a rate of 100μs / V to prevent instantaneous high current surges from impacting the system.

[0095] In smart grid applications, an RS-485 communication module (for connecting smart meters), a wireless communication module (supporting 4G / 5G backhaul), and a control output module (driving relays) can be inserted simultaneously. Each module works independently without interfering with the others, exchanging data with the main processor via a bus, achieving flexible "plug-and-play" configuration.

[0096] Example 5: This example details the implementation of the watchdog module in ensuring system reliability.

[0097] The watchdog module uses an independent hardware timer, with its clock source derived from a separate 32.768kHz crystal oscillator, completely isolated from the main processor's clock. This design ensures that the watchdog will continue to function normally even if the main processor's clock system fails.

[0098] The watchdog timer's overflow time can be configured via a register, ranging from 1ms to 65s with an accuracy of ±1%. In this embodiment, with a timeout of 1s, the general-purpose processing unit needs to send a rising edge pulse to the watchdog input via the GPIO pin every 500ms.

[0099] When the system is running normally, the general processing unit periodically performs watchdog feeding operations in the main loop, and the watchdog timer is constantly being cleared and restarted.

[0100] If the general-purpose processing unit enters an infinite loop or the program crashes due to electromagnetic interference and is unable to perform the watchdog timer operation, the watchdog timer will overflow after 1 second. Upon overflow, the reset output terminal outputs a low-level pulse lasting 100ms, forcing the general-purpose processing unit to reset and restart.

[0101] Furthermore, the watchdog module also features a window watchdog function. It not only monitors for watchdog timeouts but also for excessively fast watchdog times (less than 300ms), which typically indicates abnormally accelerated program execution. This dual protection mechanism significantly improves system reliability.

[0102] Traditional software watchdogs rely on operating system timer interrupts, which may fail during deep system crashes. The hardware watchdog in this embodiment is completely independent of the main processor, reliably triggering a reset even under the most severe system failures, providing robust protection for applications with high reliability requirements, such as industrial control.

[0103] As can be seen from the above embodiments, the heterogeneous intelligent interactive control terminal of this utility model achieves a balance of high performance, high reliability, and high flexibility through heterogeneous computing architecture, independent multi-channel power supply design, multi-level transient protection, flexible modular expansion, and hardware watchdog protection. It is particularly suitable for applications with extremely high reliability requirements, such as industrial control, power electronics, and smart grids. Compared with traditional solutions, processing performance is improved by 3-5 times, power consumption is reduced by 40%, and anti-interference capability reaches industrial level 4 standard.

[0104] Example 6: This example details the specific implementation of the touch control branch and the voice recognition branch in the human-computer interaction module. These two branches, together with the video recognition branch, constitute a complete multimodal human-computer interaction system.

[0105] The touch control branch connects to the general-purpose processing unit via a peripheral bus, employing capacitive touch technology for precise touch positioning. The X5700 touch interface is a standard I2C interface, supporting multi-touch detection. Considering the complex electromagnetic environment of industrial sites, the touch control branch integrates comprehensive ESD protection measures. TVS diodes F5700, F5701, F5702, and F5703 are connected to various pins of the X5700. These TVS diodes are 5V bidirectional TVS diodes with a response time of less than 1ns and can withstand ESD impact level 4 of the IEC61000-4-2 standard. The specific connection relationship is as follows: pin 7 of the X5700 is connected to TVS diode F5700, pin 6 is connected to TVS diode F5701, pin 5 is connected to TVS diode F5702, and pin 2 is connected to TVS diode F5703. The other end of each TVS diode is grounded, forming a discharge path to ground. The filtering circuit consists of resistor R5703 and capacitor C5707. R5703 is a 1kΩ resistor, and C5707 is a 100nF capacitor. These two are connected to pin 3 of the X5700 to form an RC low-pass filter with a cutoff frequency of approximately 1.6kHz, effectively filtering out high-frequency interference. When the touchscreen is touched, the capacitance change signal is transmitted to the general-purpose processing unit via the I2C bus. The processing unit calculates the touch position coordinates using a dedicated touch algorithm. The entire response time is less than 10ms, supporting a touch sampling rate of 300 times per second, fully meeting the operational requirements of industrial HMIs.

[0106] The voice recognition branch is designed with full consideration of the noise environment in industrial settings, employing a differential input and multi-stage filtering scheme. The core pickup device is the electret microphone MIC1, with a sensitivity of -42dB and a frequency response range of 20Hz-20kHz. The microphone is powered by resistor R726, a 2.2kΩ resistor, which provides approximately 2V bias voltage from the 3.3V power supply. Capacitor C720 is a 10μF electrolytic capacitor used for power supply decoupling, filtering out power supply ripple. The microphone's output signal enters the protection circuit through resistor R732, a 100Ω current-limiting resistor. A 3.3V bidirectional TVS diode, D706, provides ESD protection. The differential processing circuit for the voice signal is particularly crucial. The positive output of the microphone passes through a high-pass filter composed of resistor R727 and capacitor C713, with a cutoff frequency set at 80Hz to filter out low-frequency noise. The negative output passes through a high-pass filter with the same parameters, composed of resistor R728 and capacitor C714. Capacitor C717 is connected across the differential signals, forming a band-pass filter for differential mode together with R727 and R728, effectively suppressing common-mode noise. The filtered signal is AC-coupled through capacitors C707 and C708, and after removing the DC bias, it is sent to the audio ADC interface of the general-purpose processing unit. The signal-to-noise ratio of the entire voice recognition branch reaches over 65dB, and it can still accurately recognize voice commands in an industrial noise environment of 85dB, with a recognition rate exceeding 95%.

[0107] Example 7: This example details the specific implementation of various functional modules supported by the extended bus, demonstrating the powerful functional expansion capabilities of the terminal.

[0108] The local communication module is primarily used for wired communication with field devices, integrating CAN bus and MODBUS interfaces. The module connects to an expansion slot using a standard 96-pin interface and integrates an STM32F103 microcontroller as a communication coprocessor with a 72MHz clock speed, responsible for protocol conversion and data buffering. The CAN bus interface uses a TJA1050 transceiver, supporting a communication rate of 1Mbps and exhibiting good anti-interference capabilities. The MODBUS interface uses a MAX485 chip for RS485 level conversion, supporting connections of up to 32 nodes. The module has 2KB of built-in dual-port RAM for data exchange with the main processor, avoiding frequent interruptions to the main processor during communication. In practical applications, this module can simultaneously manage up to 16 CAN devices and 32 MODBUS devices, and is widely used in industrial automation control systems.

[0109] The wireless communication module adopts a modular design, supporting dual-mode communication of 4G / 5G and WiFi 6. The 4G / 5G communication utilizes the Quectel RM500Q module, supporting the 5G NR Sub-6GHz band with a downlink speed of up to 2.1Gbps. The WiFi 6 portion uses the MediaTek MT7915 chip, supporting the 802.11ax protocol with a maximum speed of 1.2Gbps. The two wireless communication modes can automatically switch, ensuring reliable data transmission. The module integrates a complete RF front-end, including a power amplifier, a low-noise amplifier, and an antenna switch. To meet the electromagnetic compatibility requirements of industrial environments, the module employs a metal shielding design and adds ferrite beads and TVS diodes for protection at the power and signal interfaces. This wireless communication module is particularly suitable for remote data acquisition and control in smart grids, enabling real-time monitoring and remote operation and maintenance of power equipment.

[0110] RS-485 communication modules are one of the most commonly used communication methods in industrial settings. This embodiment supports multi-channel isolated RS-485 communication. The module provides four independent RS-485 interfaces, each using an ADM2587E isolated transceiver with an isolation voltage of 2.5kV, effectively preventing ground potential differences and common-mode interference. Each RS-485 channel supports 256 nodes, with a communication distance of up to 1200 meters. The module's internal FPGA implements hardware-level protocol processing, supporting MODBUS RTU, MODBUS ASCII, and custom protocols, significantly reducing the burden on the main processor. Particularly noteworthy is the module's integrated automatic transmit / receive control circuit, enabling half-duplex communication direction switching without software intervention, improving communication real-time performance and reliability.

[0111] The remote signaling pulse module is specifically designed for acquiring switch signals in power systems, providing 16 opto-isolated digital input channels. Each channel is isolated using a TLP281 optocoupler, supporting an input voltage range of 12V to 220V to adapt to different field signal levels. The input terminals integrate anti-jitter circuitry, with programmable anti-jitter time settings from 1ms to 100ms, effectively filtering out switch contact jitter. The module's internal CPLD implements hardware-level pulse counting and time stamping functions, achieving a time accuracy of 1μs, meeting the stringent requirements of power systems for Sequence of Events (SOE). In smart substation applications, this module can accurately record the timing of circuit breaker and disconnector actions, providing reliable data for fault analysis.

[0112] The control output module provides 8 relay outputs and 8 transistor outputs to meet various control requirements. The relay outputs use Hongfa HF115 miniature relays with contact capacities of 2A / 30VDC or 5A / 250V and a mechanical life exceeding 10 million cycles. Each relay is equipped with a freewheeling diode and TVS diode protection to prevent damage from back EMF when an inductive load is disconnected. The transistor outputs use a ULN2803 Darlington transistor array, each capable of driving a 500mA load. They feature built-in freewheeling diodes, making them particularly suitable for driving low-power loads such as solenoid valves and indicator lights. An internal watchdog circuit monitors the output status; upon detecting an anomaly (such as a short circuit or overcurrent), it immediately disconnects the output and reports to the main processor, ensuring system safety.

[0113] Each functional module connects to the main system via an expansion bus, following a unified communication protocol. Upon insertion, each module undergoes identification; the main processor reads the module's ID register and automatically loads the corresponding driver. Data transmission utilizes DMA, achieving a maximum transfer rate of 100MB / s, meeting the demands of high-speed data acquisition. Module configuration parameters are stored in on-chip EEPROM, ensuring they are retained even during power outages, achieving true plug-and-play functionality. This modular design allows users to flexibly configure system functions according to specific application requirements, significantly improving product adaptability and cost-effectiveness.

[0114] Example 8: A heterogeneous intelligent interactive control terminal, comprising:

[0115] The main processing module is connected to the module via a power supply module and is based on a domestically developed high-performance processing platform.

[0116] The storage module is connected to the main processing module via communication.

[0117] The power management module is used to supply power to the various peripherals of the main processing module.

[0118] The human-computer interaction module is connected to the main processing module for communication.

[0119] The control module is connected to the main processing module via communication.

[0120] The expansion module is connected to the main processing module via an expansion bus.

[0121] The main processing module includes a storage module, a watchdog module, and is connected to the power supply module. It is also connected to the human-machine interface module, the control module, the communication module, and the expansion bus module.

[0122] The main processing module is a high-performance, low-power quad-core application processor designed for smart hardware and industrial applications. It also provides a variety of powerful embedded hardware engines to optimize performance for high-end applications, including video encoding / decoding, graphics processing, and AI acceleration.

[0123] The watchdog module is a mechanism used to monitor the operating status of the system. It is mainly used to ensure that the system can automatically recover when a failure occurs, thus ensuring stability and reliability.

[0124] The power management module is connected to the main processing module via communication.

[0125] The power management module includes the power management chip U500.

[0126] The power management chip includes a 4-channel BUCK circuit.

[0127] The BUCK1 circuit includes inductor L500, capacitors C504, C505, C506, and C507, and resistors R500 and R502. One end of inductor L500 is connected to SW1 of the power management chip, and the other end is connected to capacitors C507, C506, R500, C504, and C505. The other ends of capacitors C504, C506, and C507 are grounded. Capacitor C505 is connected to the other end of resistor R500, which is then connected to resistor R502. The other end of resistor R502 is connected to FB1 of the power management chip.

[0128] The BUCK2 circuit includes inductor L502, capacitors C525, C519, C520, and C521, and resistor R503. One end of inductor L502 is connected to SW2 of the power management chip, and the other end is connected to capacitors C521, C520, R503, C519, and C525. The other ends of capacitors C525, C520, and C521 are grounded. The other ends of capacitors C519 and R503 are connected to FB2 of the power management chip.

[0129] The BUCK3 circuit includes inductor L503, capacitors C522, C523, and C524, and resistors R504 and R505. One end of inductor L503 is connected to SW3 of the power management chip, and the other end is connected to capacitors C522, C523, and C524. The other ends of capacitors C522, C523, and C524 are grounded. One end of resistor R504 is connected to VBUCK3 of the power management chip, and the other end is connected to resistor R505 and then to FB3 of the power management chip. The other end of R505 is connected to ground.

[0130] The BUCK4 circuit includes inductor L501, capacitors C508, C509, C510, C511, and resistor R501. One end of inductor L501 is connected to SW4 of the power management chip, and the other end is connected to capacitors C508, C509, R501, C510, and C511. The other ends of capacitors C508, C509, and C511 are grounded. The other ends of capacitor C510 and resistor R501 are connected to FB4 of the power management chip.

[0131] The human-computer interaction module includes a display touch module, a voice recognition module, and a video recognition module. The human-computer interaction module includes X5702, resistors R5716, R5717, R5718, R5617, R5618, R5634, and R5635, capacitors C5608, C5609, C5612, and C5603, and transistors Q5600 and Q56001. One end of resistor R5716 is connected to power supply VCC3V3, and the other end is connected to VDDIN of X5702. One end of resistor R5717 is grounded, and the other end is connected to GND of X5702. One end of resistor R5718 is grounded, and the other end is connected to GND of X5702. One end of capacitor C5608 is connected to GND, and the other end is connected to VDD3V3 and then connected to capacitor C5609. The two ends of capacitor C5609 are connected to the two ends of resistor R5618. One end of resistor R5618 is connected to one end of transistor Q5600. The other end of 5618 is connected to the other end of transistor Q5600 and to resistor R5635. The three terminals of transistor Q5600 are connected to capacitors C5612 and C5603. The other ends of capacitors C5612 and C5603 are connected to ground. The other end of resistor R5635 is connected to the two terminals of transistor Q5601. The two terminals of transistor Q5601 are connected to resistors R5634 and R5617. The other end of resistor R5634 is grounded, and the other end of resistor R5617 is connected to the main processing module.

[0132] The touch module includes an X5700, TVS diodes F5700, F5701, F5702, and F5703, a resistor R5703, and a capacitor C5707. Resistor R5703 and capacitor C5707 are connected to pin 3 of the X5700. Pin 7 of the X5700 is connected to TVS diode F5700, pin 6 of the X5700 is connected to TVS diode F5701, pin 5 of the X5700 is connected to TVS diode F5702, and pin 2 of the X5700 is connected to TVS diode F5703.

[0133] The voice recognition module includes resistors R726, R732, R727, and R728; capacitors C707, C708, C713, C714, C717, and C720; a microphone (MIC1); and a TVS diode (D706). One end of resistor R726 is connected to capacitors C720 and R732. The other end of resistor R732 is connected to one end of the TVS diode (D706) and microphone (MIC1). One end of microphone (MIC1) is connected to resistor R727. The other end of resistor R727 is connected to capacitor C713. The other end of capacitor C713 is connected to capacitor C707. The other end of microphone (MIC1) is connected to resistor R728. The other end of resistor R728 is connected to capacitor C714. The other end of capacitor C714 is connected to capacitor C708. One end of capacitor C717 is connected to one end of resistor R727, and the other end of capacitor C717 is connected to one end of resistor R728.

[0134] The video recognition module includes X700, capacitor C705, TVS diodes D701 and D702, inductor L700, resistors R710 and R711. One pin of X700 is connected to capacitor C705. Pin 2 of X700 is connected to TVS diode D702, then to one end of resistor R711. One end of resistor R711 is connected to one end of inductor L700, and the other end of resistor R711 is connected to the other end of inductor L700. Pin 3 of X700 is connected to TVS diode D701, then to one end of resistor R710. One end of resistor R710 is connected to one end of inductor L700, and the other end of resistor R710 is connected to the other end of inductor L700.

[0135] The control module connects to the main processing module via a universal communication interface. The control functions are implemented through the communication bus of the terminal's main processing module, and the communication data must conform to relevant protocols. This significantly reduces the probability of malfunctions caused by interference, thus ensuring the safety and reliability of the terminal's control functions.

[0136] Expansion bus module. The expansion bus module supports various functional interface modules, including but not limited to local communication modules, loop status inspection modules, wireless remote communication modules, wireless private network communication modules, RS-485 modules, remote signaling pulse modules, and control modules. Functional modules can be combined according to actual needs.

[0137] In the technical solution of this application, the general-purpose processing unit is connected to the video encoding / decoding engine, graphics processing engine, and AI acceleration engine via independent on-chip buses. More importantly, the three dedicated processing units achieve direct data interaction through a shared bus. This architecture allows the data stream for video intelligent analysis to be directly transmitted from the video encoding / decoding engine to the AI ​​acceleration engine via the shared bus, and the recognition results are then directly transmitted to the graphics processing engine for rendering. The entire process does not require the general-purpose processing unit to participate in data transfer. The general-purpose processing unit is only responsible for task scheduling and issuing control commands, truly achieving the separation of control flow and data flow. At the same time, the power management module provides an independent power supply branch for each processing unit. Each unit can independently adjust its working state according to the actual load, avoiding the limitation that all modules must operate at the same voltage and frequency under the traditional centralized power supply method, further improving system efficiency. Actual tests show that in typical video intelligent analysis applications, data processing latency is reduced by more than 60%, system bus bandwidth usage is reduced by 70%, and the performance potential of each dedicated processing unit is fully released.

[0138] Regarding the three-stage transient protection circuit: The first stage of protection consists of TVS diodes D701 and D702, using 5V bidirectional TVS diodes to clamp transient high voltage to below 8.5V within nanoseconds. However, TVS clamping alone is insufficient; the high-frequency components and large currents of transient interference can still cause damage. Therefore, the second stage of protection introduces series current-limiting resistors R710 and R711. Each 100Ω resistor not only limits the amplitude of the transient current but, more importantly, forms a voltage divider network with the dynamic resistance of the TVS diodes, further reducing residual voltage. The third stage of protection is characterized by the special connection method of the protection inductor L700. This inductor adopts a common-mode choke structure, with its two ends connected in parallel with two protection resistors, forming high impedance to common-mode interference and low impedance to differential signals. When common-mode interference such as lightning strikes occurs, the inductor's high inductive reactance (reaching several thousand ohms in the MHz band) effectively prevents the propagation of high-frequency interference; while normal differential video signals can pass through smoothly. The synergistic effect of this three-level protection will control the residual interference voltage that ultimately reaches the video codec engine to below 3V, which is far lower than the chip's 5V withstand voltage value, and can work reliably even in the harsh electromagnetic environment of IEC61000-4-2 standard level 4 (±15kV).

[0139] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and all such equivalent transformations fall within the protection scope of the present invention.

Claims

1. A heterogeneous intelligent interactive control terminal, characterized in that, The application relates to a multi-core processor, which comprises the following parts: a main processing module comprising a general processing unit and a plurality of special processing units; the special processing units comprise a video codec engine, a graphics processing engine and an AI acceleration engine, and the three units realize mutual data interaction through a shared bus; the general processing unit is bidirectionally connected with the video codec engine through a first on-chip bus, bidirectionally connected with the graphics processing engine through a second on-chip bus and bidirectionally connected with the AI acceleration engine through a third on-chip bus; a power management module is electrically connected with the main processing module and provides independent power supply for the general processing unit and the special processing units.

2. The heterogeneous intelligent interactive control terminal according to claim 1, characterized in that, The power management module comprises: a power management chip; four independent BUCK voltage reduction power supply branches which provide independent power supply for the general processing unit, the video codec engine, the graphics processing engine and the AI acceleration engine respectively; the output ends of the BUCK voltage reduction power supply branches are connected to corresponding feedback pins of the power management chip through feedback loops.

3. The heterogeneous intelligent interactive control terminal according to claim 2, characterized in that, Each BUCK voltage reduction power supply branch comprises: a storage inductance connected to a switch output pin of the power management chip; a filter capacitor group connected to the output end of the storage inductance; a resistance network connected to the output end of the storage inductance and forming a voltage division feedback network, and the voltage division output end of the resistance network is connected to a corresponding feedback pin of the power management chip.

4. The heterogeneous intelligent interactive control terminal according to claim 1, characterized in that, The application further comprises a human-computer interaction module, which comprises: a video recognition branch connected to the video codec engine through a video data bus; a touch branch and a voice recognition branch connected to the general processing unit through peripheral buses respectively.

5. The heterogeneous intelligent interactive control terminal according to claim 4, characterized in that, The video recognition branch comprises: a video input interface; a transient protection circuit arranged between the video input interface and the video codec engine, which comprises a TVS tube group in parallel and a protection inductance in series.

6. The heterogeneous intelligent interactive control terminal according to claim 5, characterized in that, The transient protection circuit comprises: a first TVS tube and a second TVS tube connected to data pins of the video input interface respectively; a first protection resistor and a second protection resistor connected in series between the first TVS tube and the second TVS tube and a subsequent circuit; a protection inductance, the first end and the second end of which are connected in parallel with the first protection resistor and the second protection resistor respectively.

7. The heterogeneous intelligent interactive control terminal according to claim 1, characterized in that, The application further comprises an expansion bus module, which comprises: a bus interface connected to the general processing unit; at least two standardized expansion slots supporting hot plug of functional modules.

8. The heterogeneous intelligent interactive control terminal according to claim 7, characterized in that, The functional modules supported by the expansion slots comprise: one or more combinations of a local communication module, a wireless communication module, an RS-485 communication module, a remote signaling pulse module and a control output module.

9. The heterogeneous intelligent interactive control terminal according to claim 1, characterized in that, The application further comprises a watchdog module, and a reset output end of the watchdog module is connected to a reset pin of the general processing unit, and a dog feeding input end of the watchdog module is connected to a GPIO pin of the general processing unit.

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