Display panel

Abstract

The utility model provides a display panel which comprises a first sub-pixel and a second sub-pixel which are different in color, a source electrode of a driving transistor in a pixel circuit is electrically connected to a corresponding first voltage line, a drain electrode of the driving transistor is electrically connected to a light-emitting element, the amplitudes of voltages transmitted by two first voltage lines corresponding to the first sub-pixel and the second sub-pixel are different, and the amplitudes of voltages transmitted by two second voltage lines corresponding to the first sub-pixel and the second sub-pixel are different. And the power consumption of the display panel is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to display technical field, concretely relates to a display panel. BACKGROUND

[0002] With the development of OLED (Organic Light Emitting Diode) technology, the market demand for low power consumption of OLED panel is increasing.

[0003] However, in order to meet the brightness and chroma requirements of the display picture, the amplitude of the power signal of the pixel circuit is generally set to be large, which leads to the increase of the power consumption of the OLED panel. SUMMARY

[0004] The embodiment of the utility model provides a display panel to improve the technical problem of the increase of the power consumption of the existing OLED panel.

[0005] The embodiment of the utility model provides a display panel, including multiple subpixels, multiple the subpixels include different color first subpixel, second subpixel, the subpixel includes light emitting element and corresponding pixel circuit, the pixel circuit includes:

[0006] Drive transistor, one of the source, drain of drive transistor is electrically connected to corresponding first voltage line, the other of the source, drain of drive transistor is electrically connected to the light emitting element;

[0007] Wherein, the amplitude of the voltage that the first voltage line corresponding to the first subpixel transmits is different from the amplitude of the voltage that the first voltage line corresponding to the second subpixel transmits.

[0008] In some embodiments, multiple the subpixels still include third subpixel, the color of the third subpixel is different from the color of the first subpixel, the color of the second subpixel;

[0009] Wherein, the amplitude of the voltage that the first voltage line corresponding to the first subpixel transmits and the amplitude of the voltage that the first voltage line corresponding to the third subpixel transmits are same, and both are different from the amplitude of the voltage that the first voltage line corresponding to the second subpixel transmits.

[0010] In some embodiments, the color of the first subpixel is red, the color of the second subpixel is blue, and the color of the third subpixel is green.

[0011] In some embodiments, the amplitude of the voltage transmitted by the first voltage line corresponding to the first sub-pixel and the amplitude of the voltage transmitted by the first voltage line corresponding to the third sub-pixel are both greater than or equal to 2.6V and less than or equal to 3.0V.

[0012] The voltage amplitude transmitted by the first voltage line corresponding to the second sub-pixel is greater than or equal to 2.3V and less than or equal to 2.7V.

[0013] In some embodiments, the first voltage line corresponding to the first sub-pixel and the first voltage line corresponding to the third sub-pixel are located on the same layer, and the two are located on different layers from the first voltage line corresponding to the second sub-pixel.

[0014] In some embodiments, a plurality of sub-pixel arrays are arranged such that a plurality of sub-pixels in the same row include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a second sub-pixel arranged in sequence;

[0015] In one group of sub-pixels, multiple sub-pixels in the same column include alternating first sub-pixels and third sub-pixels; in another group of sub-pixels, multiple sub-pixels in the same column are all second sub-pixels.

[0016] Among them, multiple first voltage lines corresponding to multiple first sub-pixels and multiple third sub-pixels located in the same column are electrically connected, and multiple first voltage lines corresponding to multiple second sub-pixels located in the same column are electrically connected.

[0017] In some embodiments, a plurality of the sub-pixel arrays are arranged such that the plurality of sub-pixels in the same row include a first sub-pixel, a third sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence;

[0018] In one group of sub-pixels, multiple sub-pixels in the same column include alternating first sub-pixels and second sub-pixels; in another group of sub-pixels, multiple sub-pixels in the same column are all the third sub-pixels.

[0019] Among them, multiple third sub-pixels located in the same column and multiple first sub-pixels in an adjacent column are electrically connected to each other, and multiple first voltage lines corresponding to multiple second sub-pixels located in the same column are electrically connected.

[0020] In some embodiments, the plurality of sub-pixels further includes a third sub-pixel, the color of which is different from the color of the first sub-pixel and the color of the second sub-pixel;

[0021] The voltage amplitude transmitted by the first voltage line corresponding to the first sub-pixel, the voltage amplitude transmitted by the first voltage line corresponding to the second sub-pixel, and the voltage amplitude transmitted by the first voltage line corresponding to the third sub-pixel are all different.

[0022] In some embodiments, the first voltage line corresponding to the first sub-pixel, the first voltage line corresponding to the second sub-pixel, and the first voltage line corresponding to the third sub-pixel are located in three different layers.

[0023] In some embodiments, the display panel includes peripheral traces located on at least one side of the plurality of sub-pixels, the peripheral traces including:

[0024] The first peripheral trace is electrically connected to the multiple first voltage lines corresponding to the multiple first sub-pixels;

[0025] The second peripheral trace is electrically connected to the first voltage lines corresponding to the multiple second sub-pixels.

[0026] In some embodiments, the pixel circuit further includes:

[0027] A switching transistor, wherein one of its source and drain is electrically connected to the corresponding first voltage line, and the other of its source and drain is electrically connected to one of the source and drain of the driving transistor.

[0028] This invention provides a display panel including multiple sub-pixels, each sub-pixel including a first sub-pixel and a second sub-pixel of different colors. Each sub-pixel includes a light-emitting element and a corresponding pixel circuit. The pixel circuit includes a driving transistor, one of the source and drain of the driving transistor being electrically connected to a corresponding first voltage line, and the other of the source and drain of the driving transistor being electrically connected to the light-emitting element. The amplitude of the voltage transmitted by the first voltage line corresponding to the first sub-pixel is different from the amplitude of the voltage transmitted by the first voltage line corresponding to the second sub-pixel, thus avoiding the problem of high power consumption in the display panel caused by using the same amplitude first voltage signal for sub-pixels of different colors. Attached Figure Description

[0029] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for explaining some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0030] Figure 1 This is a schematic diagram of the display device provided for an embodiment of the present invention.

[0031] Figure 2 and Figure 3 Two circuit diagrams of pixel circuits provided for embodiments of this utility model.

[0032] Figure 4 Provided for embodiments of this utility model Figure 3 The timing diagram corresponding to the pixel circuit.

[0033] Figures 5 to 7 A layout diagram of sub-pixels and lines in a display panel provided for an embodiment of this utility model. Detailed Implementation

[0034] The technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0035] In this invention, the terms "first" and "second" are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to such processes, methods, products, or devices.

[0036] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the present invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0037] The embodiments of this utility model provide a display panel, which includes, but is not limited to, the following embodiments and combinations thereof.

[0038] In some embodiments, such as Figures 1 to 3As shown, the display panel 100 includes a plurality of sub-pixels P, each sub-pixel P including a first sub-pixel R and a second sub-pixel B of different colors. Each sub-pixel P includes a light-emitting element D and a corresponding pixel circuit 10. The pixel circuit 10 includes a driving transistor T1, one of the source and drain of the driving transistor T1 (taking the source as an example) being electrically connected to a corresponding first voltage line (for transmitting a first voltage signal VDD), and the other of the source and drain of the driving transistor T1 (taking the drain as an example) being electrically connected to the light-emitting element D. The amplitude of the voltage transmitted by the first voltage line corresponding to the first sub-pixel R (i.e., the corresponding first voltage signal VDD, referred to as the first sub-voltage signal RVDD) is different from the amplitude of the voltage transmitted by the first voltage line corresponding to the second sub-pixel B (i.e., the corresponding first voltage signal VDD, referred to as the second sub-voltage signal BVDD).

[0039] In this embodiment, the specific colors of the first sub-pixel R and the second sub-pixel B are not limited, as long as the colors of the two are different.

[0040] Among them, such as Figure 1 As shown, the display panel 100 can be used to construct a display device 200. The display device 200 may further include a gate driver 300, a timing controller 401, and a source driver 402. The gate driver 300 may be a gate driving circuit located on the substrate of the display panel 100 or a chip disposed independently of the display panel 100. Figure 1 (The former is used as an example only). For ease of description, Figure 1 The following example illustrates the arrangement of multiple sub-pixel arrays P in the display panel 100, for instance, they can be arranged in N rows and M columns (N and M are both positive integers).

[0041] Specifically, the display panel 100 may also include multiple gate lines (GL1 to GLN) electrically connected to the gate driver 300 and multiple data lines (DL1 to DLM) electrically connected to the source driver. Gate driver 300 generates multiple gate signals Gate corresponding to multiple rows of sub-pixels P. Each gate line (one of GL1 to GLN) is electrically connected to a corresponding row of sub-pixels P to transmit the corresponding gate signal Gate to the corresponding row of sub-pixels P. Each gate signal Gate includes a gate pulse for controlling the corresponding row of sub-pixels P to turn on. The multiple gate pulses are arranged sequentially on the time axis, so that the corresponding multiple rows of sub-pixels P turn on sequentially. Each data line (one of DL1 to DLM) is electrically connected to a corresponding column of sub-pixels P to transmit a corresponding data signal Data generated by source driver 402 to it. Each data signal Data includes multiple data voltages corresponding to the multiple sub-pixels P in that column. The multiple data signals Data corresponding to the multiple columns of sub-pixels P are configured to transmit the multiple data voltages corresponding to the multiple sub-pixels P in that row to the multiple sub-pixels P respectively through the multiple data lines (DL1 to DLM) when each row of sub-pixels P is turned on.

[0042] The display device 200 also includes a power manager 500, which supplies power to the gate driver 300, the source driver 402, the timing controller 401, and the display panel 100. The timing controller 401 generates timing signals and transmits them to the gate driver 300 and the source driver 402, and generates image signals and transmits them to the source driver 402. The gate driver 300 then generates the aforementioned plurality of gate signals (Gate), and the source driver 402 generates the aforementioned plurality of data signals (Data), thereby driving the plurality of sub-pixels P to emit light. The plurality of first voltage signals VDD acting on the plurality of pixel circuits 10 can be provided by the power manager 500.

[0043] In the pixel circuit 10, since the source of the driving transistor T1 receives the corresponding first voltage signal VDD and the drain of the driving transistor T1 is electrically connected to the light-emitting element D, the magnitude of the first voltage signal VDD will affect the gate-source voltage of the driving transistor T1, thereby affecting the magnitude of the driving current Id generated by the driving transistor T1 flowing through the light-emitting element D, and thus affecting the light-emitting brightness of the corresponding light-emitting element D.

[0044] Understandably, this embodiment takes into account the differences in material properties between the first sub-pixel R and the second sub-pixel B, which have different colors, resulting in differences in their luminous efficiency under the same conditions. Without intervention, this could lead to problems such as color shift and inaccurate brightness in the displayed image. Therefore, the amplitudes of the two first voltage signals VDD (e.g., the first sub-voltage signal RVDD and the second sub-voltage signal BVDD) received by the pixel circuit 10 corresponding to the two are set differently. This allows the two first voltage signals VDD to be set according to the properties of the corresponding light-emitting element D. As a result, each first voltage signal VDD has an appropriate value, which not only meets the luminous requirements of the light-emitting elements D with different colors, but also avoids the problem of high power consumption of the display device 200 (including the power consumption of the light-emitting element D and the power consumption of the power manager 500) caused by uniformly setting all the first voltage signals VDD to a large value (greater than the first voltage signal VDD corresponding to some light-emitting elements D).

[0045] In some embodiments, such as Figure 1 and Figure 3 As shown, the pixel circuit 10 further includes a switching transistor (e.g., a first switching transistor T5), one of the source and drain of the switching transistor (taking the source as an example) is electrically connected to the corresponding first voltage line (for transmitting the first voltage signal VDD), and the other of the source and drain of the switching transistor (taking the drain as an example) is electrically connected to one of the source and drain of the driving transistor T1 (taking the source as an example). That is, by setting a switching transistor connected in series between the first voltage line and the driving transistor T1, it is possible to control whether a current path is formed between the first voltage line and the driving transistor T1, thereby improving the flexibility and reliability of the pixel circuit 10.

[0046] To better illustrate how the magnitude of the first voltage signal VDD affects the magnitude of the driving current Id generated by the driving transistor T1 and flowing through the light-emitting element D, we will use... Figure 2 and Figure 3 Taking the example that all transistors in the two pixel circuits 10 shown are P-type transistors, the working principle of the pixel circuit 10 will be explained.

[0047] Combination Figure 1 and Figure 2 As shown, the gate signal Gate includes the first gate signal Scan. When the gate pulse corresponding to the first gate signal Scan arrives, the data writing transistor T2 is turned on, and the data voltage corresponding to the data signal Data is written to the gate of the driving transistor T1. The storage capacitor Cst maintains the gate-source voltage of the driving transistor T1 at VDD-Data, and the corresponding driving current Id is k×(VDD-Data-Vth). 2k is a coefficient related to the material and size of the driving transistor T1, and Vth is the threshold voltage of the driving transistor T1.

[0048] Combination Figure 1 , Figure 3 and Figure 4 As shown, taking the nth row sub-pixel P as an example, the gate signal Gate of the nth level mentioned above includes the first gate signal Scan[n] of the nth level and the second gate signal EM[n] of the nth level. The pixel circuit 10 can include the following working stages:

[0049] During the reset phase t1, the first gate signal Scan[n-1] of the [n-1]th stage is the corresponding effective potential, the reset transistor T4 is turned on, and the reset signal VI is transmitted to the gate of the driving transistor T1 to reset it;

[0050] During the compensation phase t2, the first gate signal Scan[n] of the nth stage is the corresponding effective potential. The data writing transistor T2 and the compensation transistor T3 are turned on. The data voltage corresponding to the data signal Data is written to the source of the driving transistor T1 to turn on the driving transistor T1. The data signal Data is transmitted to the gate of the driving transistor T1 through the turned-on driving transistor T1 and compensation transistor T3. The potential of the gate of the driving transistor T1 gradually rises until the gate-source voltage of the driving transistor T1 is Data+Vth, at which point the driving transistor T1 is turned off.

[0051] During the light-emitting stage t3, the second gate signal EM[n] of the nth stage is the corresponding effective potential. Both the first switching transistor T5 and the second switching transistor T6 are turned on. The first voltage signal VDD is transmitted to the source of the driving transistor T1, and the second voltage signal VSS is transmitted to the cathode of the light-emitting element D. The gate-source voltage of the driving transistor T1 is data + Vth - VDD. The storage capacitor Cst maintains the gate-source voltage of the driving transistor T1. Since a current path is formed, the driving transistor T1 generates a value of k × (data - VDD). 2 The driving current Id.

[0052] Therefore, for any pixel circuit 10, such as 2T1C, 6T1C, or other architectures, the first voltage signal VDD transmitted by the first voltage line electrically connected to the source of the driving transistor T1 may affect the magnitude of the driving current Id generated by the driving transistor T1 and flowing through the light-emitting element D. Therefore, this embodiment sets the amplitude of the first voltage signal VDD corresponding to sub-pixels P of different colors differently. While meeting the brightness requirements of sub-pixels P of different colors, it can also avoid the problem of excessive power consumption of the light-emitting element D and the power manager 500 caused by the first voltage signal VDD being set uniformly.

[0053] In some embodiments, such as Figure 1 , Figure 5 and Figure 6 As shown, the display panel 100 includes peripheral traces located on at least one side of the plurality of sub-pixels P. The peripheral traces include: a first peripheral trace L1, electrically connected to the plurality of first voltage lines corresponding to the plurality of first sub-pixels R; and a second peripheral trace L2, electrically connected to the plurality of first voltage lines corresponding to the plurality of second sub-pixels B.

[0054] Furthermore, in order to improve the driving force of the first voltage signal VDD, or in order to reduce the brightness difference between the sub-pixels P on the left and right sides of the display panel 100, the first peripheral trace L1 and the second peripheral trace L2 can both be configured to include portions distributed on the left and right sides of the multiple sub-pixels P, and electrically connected through the portion located between the two sides, and electrically connected to the power manager 500 through the connection line.

[0055] Understandably, by setting up peripheral traces that are electrically connected to the power manager 500 and surround multiple sub-pixels P, the first voltage line corresponding to each sub-pixel P can be electrically connected to the corresponding first peripheral trace L1 or second peripheral trace L2 through the corresponding connecting line, which facilitates wiring within the display panel 100.

[0056] In some embodiments, such as Figure 1 , Figures 6 to 7 As shown, the plurality of sub-pixels P further includes a third sub-pixel G, the color of which is different from the color of the first sub-pixel R and the color of the second sub-pixel B; wherein, the amplitude of the voltage transmitted by the first voltage line corresponding to the first sub-pixel R (i.e., the first sub-voltage signal RVDD) and the amplitude of the voltage transmitted by the first voltage line corresponding to the third sub-pixel G (i.e., the corresponding first voltage signal VDD, referred to as the third sub-voltage signal GVDD) are the same, and both are different from the amplitude of the voltage transmitted by the first voltage line corresponding to the second sub-pixel B (i.e., the second sub-voltage signal BVDD).

[0057] Similarly, in this embodiment, the specific colors of the first sub-pixel R, the second sub-pixel B, and the third sub-pixel G are not limited, as long as the colors of the three are different.

[0058] It should be noted that when multiple sub-pixels P include first sub-pixels R, second sub-pixels B, and third sub-pixels G of different colors, this embodiment will, based on the differential setting of the amplitude of the first sub-voltage signal RVDD corresponding to the first sub-pixel R and the amplitude of the second sub-voltage signal BVDD corresponding to the second sub-pixel B to reduce the power consumption of the display device 200, set the amplitude of the first sub-voltage signal RVDD and the amplitude of the third sub-voltage signal GVDD corresponding to the first sub-pixel R and the third sub-pixel G of different colors to be the same. This allows the power manager 500 to generate only two first voltage signals VDD with different amplitudes. That is, the first sub-pixel R and the third sub-pixel G are both powered by the same first voltage signal VDD. This can reduce the number of output pins of the power manager 500 and the types of traces transmitting different first voltage signals VDD within the display panel 100, thereby reducing the wiring difficulty of the display panel 100.

[0059] Specifically, the difference in material properties of the light-emitting elements D corresponding to the first sub-pixel R and the third sub-pixel G, which have different colors, can be considered to decrease. Therefore, even if they are subjected to the same first voltage signal VDD, they can still meet their respective light-emitting requirements. Specifically, the color of the first sub-pixel R is red, the color of the second sub-pixel B is blue, and the color of the third sub-pixel G is green.

[0060] In some embodiments, such as Figure 1 , Figures 6 to 7 As shown, the amplitude of the voltage transmitted by the first voltage line corresponding to the first sub-pixel R (i.e., the first sub-voltage signal RVDD) and the amplitude of the voltage transmitted by the first voltage line corresponding to the third sub-pixel G (i.e., the third sub-voltage signal GVDD) are both greater than or equal to 2.3V and less than or equal to 2.7V; the amplitude of the voltage transmitted by the first voltage line corresponding to the second sub-pixel B (i.e., the second sub-voltage signal BVDD) is greater than or equal to 2.6V and less than or equal to 3.0V.

[0061] Understandably, in the light-emitting element D of an OLED, the red light-emitting material (corresponding to the first sub-pixel R) and the green light-emitting material (the third sub-pixel G) can use phosphorescent materials to achieve a luminous efficiency close to 100%, while the blue light-emitting material (corresponding to the second sub-pixel B) still uses fluorescent materials, with a lower efficiency of only 25%. Therefore, in this embodiment, by setting the amplitudes of the first sub-voltage signal RVDD and the third sub-voltage signal GVDD corresponding to the first sub-pixel R and the third sub-pixel G, which have similar and relatively high luminous efficiencies, to a smaller and the same value, and setting the amplitude of the second sub-voltage signal BVDD corresponding to the second sub-pixel B, which has a lower luminous efficiency, to a larger value, the luminous requirements of the three colors of sub-pixels are met, which not only reduces the power consumption of the display device 200, but also reduces the number of output pins of the power manager 500 and the wiring difficulty of the display panel 100.

[0062] In some embodiments, such as Figure 1 , Figures 6 to 7 As shown, the first voltage line corresponding to the first sub-pixel R and the first voltage line corresponding to the third sub-pixel G are located on the same layer, and the two are located on different layers from the first voltage line corresponding to the second sub-pixel B.

[0063] As discussed above, the amplitude of the first sub-voltage signal RVDD transmitted by the first voltage line corresponding to the first sub-pixel R is the same as the amplitude of the third sub-voltage signal GVDD transmitted by the first voltage line corresponding to the third sub-pixel G. That is, the first voltage line corresponding to the first sub-pixel R and the first voltage line corresponding to the third sub-pixel G are used to transmit the same first voltage signal VDD. The signals transmitted by the two first voltage lines will not interfere with each other. Therefore, the two (and their corresponding peripheral traces) can be set on the same layer to reduce the number of film layers in the display panel 100. At the same time, since the second sub-voltage signal BVDD transmitted by the first voltage line corresponding to the second sub-pixel B is different from the previous two, the first voltage line corresponding to the second sub-pixel B (and its corresponding peripheral traces) can be set on another layer to reduce the interference between the second sub-voltage signal BVDD and the previous two.

[0064] For example Figure 6 and Figure 7 In the first sub-pixel R, the first voltage line corresponding to the first sub-pixel R and the first voltage line corresponding to the third sub-pixel G are electrically connected to the first peripheral trace L1, which is set on the same layer as both of them. The first voltage line corresponding to the second sub-pixel B is electrically connected to the second peripheral trace L2, which is set on the same layer as it.

[0065] In some embodiments, such as Figure 6As shown, multiple sub-pixel P arrays are arranged in a row. The multiple sub-pixels P in the same row include a first sub-pixel R, a second sub-pixel B, a third sub-pixel G, and a second sub-pixel B arranged in sequence. In some columns of sub-pixels P, multiple sub-pixels P in the same column include alternating first sub-pixels R and third sub-pixels G. In other columns of sub-pixels P, multiple sub-pixels P in the same column are all second sub-pixels B. The multiple first voltage lines corresponding to the multiple first sub-pixels R and the multiple third sub-pixels G in the same column are electrically connected, and the multiple first voltage lines corresponding to the multiple second sub-pixels B in the same column are electrically connected.

[0066] Specifically, in this embodiment, multiple sub-pixel P arrays are arranged, and the first sub-pixel R and the third sub-pixel G corresponding to the same first voltage signal VDD are set in the same column. Furthermore, the two are arranged alternately to make their numbers close. At the same time, the second sub-pixel B is set in the same column so that the number of the second sub-pixel B can be approximately twice the number of each of the first sub-pixel R and the third sub-pixel G, so that the second sub-pixel B occupies a larger proportion in the display panel 100, in order to compensate for the brightness loss of the corresponding color caused by the luminous efficiency of the second sub-pixel B.

[0067] And, as Figure 6 As shown, since the first sub-pixel R and the third sub-pixel G are arranged in the same column, multiple first voltage lines corresponding to multiple first sub-pixels R and multiple first voltage lines corresponding to multiple third sub-pixels G on one side can be electrically connected through vertically extending traces. Similarly, multiple first voltage lines corresponding to multiple second sub-pixels B on one side can be electrically connected through another vertically extending trace. Therefore, the arrangement of the above-mentioned sub-pixels P is beneficial to simplifying the trace layout within the display panel 100.

[0068] In some embodiments, such as Figure 7 As shown, multiple sub-pixel P arrays are arranged in a row. The multiple sub-pixels P in the same row include a first sub-pixel R, a third sub-pixel G, a second sub-pixel B, and another third sub-pixel G arranged in sequence. In some columns of sub-pixels P, multiple sub-pixels P in the same column include alternating first sub-pixels R and second sub-pixels B. In other columns of sub-pixels P, multiple sub-pixels P in the same column are all third sub-pixels G. The multiple first voltage lines corresponding to the multiple third sub-pixels G in the same column and the multiple first sub-pixels R in at least one adjacent column are electrically connected. The multiple first voltage lines corresponding to the multiple second sub-pixels B in the same column are also electrically connected.

[0069] Specifically, in this embodiment, multiple sub-pixel P arrays are arranged, and a column of sub-pixels P formed by alternating first sub-pixels R and second sub-pixels B is set between two adjacent columns of third sub-pixels G. At the same time, the column of sub-pixels P formed by alternating first sub-pixels R and second sub-pixels B and the column of third sub-pixels G are alternately arranged in the row direction. The color of the third sub-pixel G in the same column can be shared by the column of sub-pixels P formed by alternating first sub-pixels R and second sub-pixels B in the two adjacent columns. Correspondingly, the color of the column of sub-pixels P formed by alternating first sub-pixels R and second sub-pixels B can be shared by the third sub-pixels G in the two adjacent columns.

[0070] Among them, such as Figure 7 As shown, although the first sub-pixel R and the second sub-pixel B are arranged in the same column, the amplitudes of their corresponding first voltage signals VDD are different. Furthermore, the amplitude of the second sub-voltage signal BVDD corresponding to the second sub-pixel B is different from the amplitudes of the first sub-voltage signal RVDD corresponding to the first sub-pixel R and the third sub-voltage signal GVDD corresponding to the third sub-pixel G. Therefore, multiple first voltage lines corresponding to multiple second sub-pixels B in a column of sub-pixels P on one side can be electrically connected through a vertically extending trace. Similarly, multiple first voltage lines corresponding to a column of third sub-pixels G on one side can be electrically connected through another vertically extending trace. At the same time, this vertically extending trace can also be electrically connected to multiple first sub-pixels R in a column of sub-pixels P on the other side.

[0071] In some embodiments, such as Figure 1 and Figure 5 As shown, the plurality of sub-pixels P further includes a third sub-pixel G, the color of which is different from the color of the first sub-pixel R and the color of the second sub-pixel B; wherein, the amplitude of the voltage transmitted by the first voltage line corresponding to the first sub-pixel R, the amplitude of the voltage transmitted by the first voltage line corresponding to the second sub-pixel B, and the amplitude of the voltage transmitted by the first voltage line corresponding to the third sub-pixel G are all different.

[0072] Compare with the above text about Figure 6 As discussed earlier, in this embodiment, for the first sub-pixel R, the second sub-pixel B, and the third sub-pixel G with different colors, the first sub-voltage signal RVDD, the second sub-voltage signal BVDD, and the third sub-voltage signal GVDD corresponding to the three are set differently. Specifically, the amplitudes of the three sub-voltage signals are different, thereby satisfying the brightness requirements of different colored sub-pixels P and further improving the accuracy of the display image of the display panel 100. The colors of the first sub-pixel R, the second sub-pixel B, and the third sub-pixel G can be red, blue, and green, respectively.

[0073] Furthermore, in comparison with the above discussion, the amplitude of the second sub-voltage signal BVDD corresponding to the second sub-pixel B in this embodiment can also be between 2.6V and 3.0V. The amplitudes of the first sub-voltage signal RVDD corresponding to the first sub-pixel R and the third sub-voltage signal GVDD corresponding to the third sub-pixel G can be selected as two different values ​​between 2.3V and 2.7V. Of course, the ranges of their amplitudes can also be non-overlapping.

[0074] In some embodiments, such as Figure 1 and Figure 5 As shown, the first voltage line corresponding to the first sub-pixel R, the first voltage line corresponding to the second sub-pixel B, and the first voltage line corresponding to the third sub-pixel G are located in three different layers.

[0075] Understandably, in this embodiment, since the amplitudes of the first sub-voltage signal RVDD, the second sub-voltage signal BVDD, and the third sub-voltage signal GVDD acting on the first sub-pixel R, the second sub-pixel B, and the third sub-pixel G are different, they need to be electrically connected to three different output pins in the power manager 500 through the first peripheral trace L1, the second peripheral trace L2, and the third peripheral trace L3, respectively, to obtain three first voltage signals VDD with different amplitudes. Similarly, in order to reduce interference between different signals, the first voltage line and the corresponding first peripheral trace L1 corresponding to the first sub-pixel R can be set in one film layer, the first voltage line and the corresponding second peripheral trace L2 corresponding to the second sub-pixel B can be set in another film layer, and the first voltage line and the corresponding third peripheral trace L3 corresponding to the third sub-pixel G can be set in yet another film layer.

[0076] In other embodiments, regardless of whether the number of peripheral wiring types is 2 or greater, such as Figures 5 to 7 As shown, multiple sub-pixels P corresponding to the same first voltage signal VDD can be arranged in the same column, and multiple first voltage lines in the same column can be electrically connected to a corresponding vertically extending trace. Furthermore, traces located on the upper or lower side of the display panel 100 and extending horizontally can be electrically connected to multiple vertically extending traces corresponding to the same first voltage signal VDD through multiple nodes. Of course, in Figure 7 In the process, since the amplitudes of the first sub-voltage signal RVDD corresponding to the first sub-pixel R and the third sub-voltage signal GVDD corresponding to the third sub-pixel G are the same, multiple first sub-pixels R in at least one column adjacent to a column of third sub-pixels G can also be connected to the vertically extending trace corresponding to the column of third sub-pixels G through a line with a shorter horizontal length.

[0077] Or, different from Figures 5 to 7In the wiring method shown, among multiple sub-pixels P in the same row, multiple first voltage lines corresponding to multiple sub-pixels P that correspond to the same first voltage signal VDD can be electrically connected to the same horizontally extending trace. Furthermore, each peripheral trace can be electrically connected to multiple horizontally extending traces corresponding to the same first voltage signal VDD through multiple nodes.

[0078] In the two embodiments described above, by setting a vertically extending trace between each two adjacent columns of sub-pixels P and setting a number of horizontal traces on the upper or lower side of the display panel 100 that are the same as the number of peripheral traces, or by setting a horizontally extending trace between each two adjacent rows of sub-pixels P, an electrical connection with the peripheral traces is achieved, so that multiple vertically extending traces or multiple horizontally extending traces can be arranged regularly within the display area of ​​the display panel 100, thereby reducing the risk of uneven display of the display panel 100.

[0079] In other embodiments, multiple sub-pixels P based on the same column correspond to the same first voltage signal VDD, but unlike... Figures 5 to 7 The wiring method shown involves multiple sub-pixels P in a certain column being electrically connected to a corresponding vertically extending trace in the same column. For multiple sub-pixels P in the remaining columns, multiple sub-pixels P in the same row corresponding to the same first voltage signal are electrically connected to a corresponding horizontally extending trace. Therefore, the display area of ​​the display panel 100 can have a similar number of vertically extending traces and horizontally extending traces, making the uniformity of the display image in both the horizontal and vertical directions nearly consistent, further improving the uniformity of the display image.

[0080] It should be noted that the transistors used in all embodiments of this invention can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Since the source and drain of the transistors used here are symmetrical, they are interchangeable. In the embodiments of this invention, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source, and the other is called the drain. Furthermore, the transistors used in the embodiments of this invention can include both P-type and N-type transistors. The P-type transistor conducts when the gate is low and is cut off when the gate is high, while the N-type transistor conducts when the gate is high and is cut off when the gate is low.

[0081] The display panel provided in the embodiments of this utility model has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this utility model. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this utility model. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A display panel, characterized by, The display panel comprises a plurality of sub-pixels, the plurality of sub-pixels comprising first sub-pixels and second sub-pixels of different colors, the sub-pixels comprising light-emitting elements and corresponding pixel circuits, the pixel circuits comprising: a driving transistor, one of a source and a drain of the driving transistor being electrically connected to a corresponding first voltage line, the other of the source and the drain of the driving transistor being electrically connected to the light-emitting element; wherein the first sub-pixels correspond to different voltage amplitudes transmitted by the first voltage line.

2. The display panel of claim 1, wherein, The plurality of sub-pixels further comprises third sub-pixels, the colors of the third sub-pixels being different from the colors of the first sub-pixels and the colors of the second sub-pixels; wherein the first sub-pixels correspond to the same voltage amplitude transmitted by the first voltage line as the third sub-pixels, and both are different from the voltage amplitude transmitted by the first voltage line corresponding to the second sub-pixels.

3. The display panel of claim 2, wherein, The color of the first sub-pixels is red, the color of the second sub-pixels is blue, and the color of the third sub-pixels is green.

4. The display panel of claim 3, wherein, The voltage amplitudes transmitted by the first voltage line corresponding to the first sub-pixels and the third sub-pixels are both greater than or equal to 2.6V and less than or equal to 3.0V; The voltage amplitude transmitted by the first voltage line corresponding to the second sub-pixels is greater than or equal to 2.3V and less than or equal to 2.7V.

5. The display panel of claim 2, wherein, The first voltage line corresponding to the first sub-pixels and the first voltage line corresponding to the third sub-pixels are located on the same layer, and both are different from the first voltage line corresponding to the second sub-pixels.

6. The display panel of claim 2, wherein, The plurality of sub-pixels are arranged in an array, the plurality of sub-pixels in the same row comprising the first sub-pixels, the second sub-pixels, the third sub-pixels, and the second sub-pixels arranged in sequence; The plurality of sub-pixels in the same column in some columns comprise the first sub-pixels and the third sub-pixels arranged alternately, and the plurality of sub-pixels in the same column in the other columns are all the second sub-pixels; wherein the plurality of first sub-pixels and the plurality of third sub-pixels in the same column are electrically connected to a plurality of first voltage lines corresponding to the plurality of first sub-pixels and the plurality of third sub-pixels, and the plurality of second sub-pixels in the same column are electrically connected to a plurality of first voltage lines corresponding to the plurality of second sub-pixels.

7. The display panel of claim 2, wherein, The plurality of sub-pixels are arranged in an array, the plurality of sub-pixels in the same row comprising the first sub-pixels, the third sub-pixels, the second sub-pixels, and the third sub-pixels arranged in sequence; The plurality of sub-pixels in the same column in some columns comprise the first sub-pixels and the second sub-pixels arranged alternately, and the plurality of sub-pixels in the same column in the other columns are all the third sub-pixels; wherein the plurality of third sub-pixels in the same column and the plurality of first sub-pixels in at least one adjacent column are electrically connected to a plurality of first voltage lines corresponding to the plurality of third sub-pixels and the plurality of first sub-pixels, and the plurality of second sub-pixels in the same column are electrically connected to a plurality of first voltage lines corresponding to the plurality of second sub-pixels.

8. The display panel of claim 1, wherein, The plurality of sub-pixels further include a third sub-pixel, a color of the third sub-pixel being different from the color of the first sub-pixel and the color of the second sub-pixel; The first sub-pixel corresponds to the first voltage line, the second sub-pixel corresponds to the first voltage line, and the third sub-pixel corresponds to the first voltage line.

9. The display panel of claim 8, wherein, The first sub-pixel corresponds to the first voltage line, the second sub-pixel corresponds to the first voltage line, and the third sub-pixel corresponds to the first voltage line.

10. The display panel of claim 1, wherein, The display panel includes a peripheral trace located on at least one side of the plurality of sub-pixels, and the peripheral trace includes: A first peripheral trace electrically connected to a plurality of first voltage lines corresponding to a plurality of first sub-pixels; A second peripheral trace electrically connected to a plurality of first voltage lines corresponding to a plurality of second sub-pixels.

11. The display panel of any of claims 1 to 10, wherein, The pixel circuit further includes: A switch transistor, one of a source and a drain of the switch transistor being electrically connected to the corresponding first voltage line, and the other of the source and the drain of the switch transistor being electrically connected to one of a source and a drain of the driving transistor.

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