Memory particle power supply discharging circuit and memory circuit
By setting a first resistor and a first switch in the power discharge circuit of the memory chip, and using a control circuit to control their conduction or shutdown, the problem of the power-down timing of the memory chip not meeting the specifications is solved, achieving fast power-down and reduced power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2026-03-10
AI Technical Summary
Existing technologies do not meet the specifications for power-down timing of memory chips, and have problems such as excessive power consumption or incomplete charge discharge.
By setting a first resistor and a first switch in the power discharge circuit of the memory chip, and using a control circuit to control the switch to turn on or off, rapid discharge can be achieved.
It achieves rapid power-down of the memory chip power supply, meets power-down timing requirements, and reduces power consumption during normal system operation.
Smart Images
Figure CN223986425U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of power electronics, especially to a memory grain power supply discharging circuit and storage circuit. BACKGROUND
[0002] In the storage circuit, often include a plurality of memory grains for storing and transmitting data, need through a plurality of power supply provides a plurality of power supply voltage to the memory grain power supply. When the system needs to power down, the power down sequence of a plurality of power supply voltage needs to be controlled, if the power down sequence does not meet the power down timing, it may lead to data loss, system instability and even security problems.
[0003] However, the voltage of the power supply end of some memory grains drops relatively slowly, which will lead to difficulty in meeting the power down timing specified in the protocol specification. In the prior art, for the power supply end with slow power down, a resistor is usually connected in parallel with the power supply end, so that the charge stored in the memory grain provides a discharge loop, and the voltage drop speed of the power supply end is improved.
[0004] However, this method has a serious problem. If the resistance value of the resistor in the parallel branch is too small, it will lead to high energy consumption of the system during normal operation. If the resistance value of the resistor is too large, it will not achieve rapid discharge of the charge. UTILITY MODEL CONTENTS
[0005] Therefore, the utility model embodiment provides a memory grain power supply discharging circuit and storage circuit. The control circuit can control the conduction or turn-off of the first switch, so the resistance value of the first resistor can be set smaller, thereby realizing rapid discharge of the power supply end of the memory grain and reducing the energy consumption of the system during normal operation.
[0006] In a first aspect, the utility model embodiment provides a memory grain power supply discharging circuit, which comprises:
[0007] A discharging branch comprising a first resistor and a first switch, which are connected in series between a ground end and a first power supply end of the memory grain;
[0008] A control circuit configured to control the conduction or turn-off of the first switch according to the controlled state of the memory grain, thereby discharging the first power supply end of the memory grain.
[0009] In a second aspect, the utility model embodiment provides a storage circuit, which comprises:
[0010] At least one memory grain;
[0011] at least one power supply circuit connected to the at least one memory cell through the first power supply terminal, the power supply circuit being configured to supply power to the memory cell;
[0012] at least one memory cell power supply discharge circuit according to the first aspect, the memory cell power supply discharge circuit being configured to control a discharge state of the power supply circuit.
[0013] The technical scheme of the embodiment of the utility model discloses a discharge branch and control circuit are arranged in the memory cell power supply discharge circuit, wherein, discharge includes first resistance and first switch, the first resistance and first switch are connected between ground terminal and the first power supply terminal of memory cell, and control circuit is configured as the first switch is turned on or turned off according to the controlled state of memory cell, thereby discharging the first power supply terminal of memory cell. Therefore, the control circuit can control the first switch to be turned on or turned off, so the resistance of the first resistance can be set smaller, and then the first power supply terminal of the memory cell is discharged quickly, and the energy consumption when the system is working normally is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0014] The above and other objects, features and advantages of the present application will become more apparent from the following description of the preferred embodiments of the present application taken with reference to the accompanying drawings, in which:
[0015] Figure 1 is the schematic diagram of the memory cell power supply discharge of prior art;
[0016] Figure 2 is the schematic diagram of the memory circuit of the embodiment of the utility model;
[0017] Figure 3 is the circuit diagram of the memory cell power supply discharge circuit of one embodiment of the utility model;
[0018] Figure 4 is the circuit diagram of the memory cell power supply discharge circuit of another embodiment of the utility model. DETAILED DESCRIPTION
[0019] The present application is described below based on embodiments, but the present application is not limited to these embodiments only. In the following detailed description of the present application, some specific details are described in detail. The present application can also be understood without the description of these details by those skilled in the art. In order to avoid confusion of the essence of the present application, well-known methods, processes, procedures, elements and circuits are not described in detail.
[0020] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only and the drawings are not necessarily drawn to scale.
[0021] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.
[0022] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".
[0023] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0024] In current memory technology, memory chips are the main component of memory modules; specifically, they are the tiny particles on the memory module responsible for storing and transmitting data. Current storage systems typically contain multiple memory chips, each responsible for storing and transmitting data. Multiple power supplies are required to provide multiple voltage levels to maintain normal operation. When the system powers down, these power supplies must meet a pre-set power-down sequence to maintain the stability of the storage system.
[0025] However, some memory chips exhibit a slow voltage drop at their power supply terminals during power-down, violating established power-down timing requirements. To address this issue, current technology tends to connect a resistor in parallel at the power supply terminal to create a charge discharge path and accelerate the voltage drop process. At this point, choosing the appropriate resistor value becomes a tricky problem: a resistance value that is too small will increase power consumption during normal system operation, while a resistance value that is too large will not effectively accelerate charge discharge, thus failing to achieve rapid power-down.
[0026] For example, LPDDR4X (Low Power Double Data Rate 4X) is a type of memory chip mainly used in mobile devices such as smartphones, tablets, and laptops. In the Jedec association specification, the power-down timing of LPDDR4X chips has the following requirements: when any power supply voltage drops to the minimum allowable voltage value and all power supplies are just below 300mV, VDD2 must be greater than VDDQ-200mV. Therefore, the power-down speed of power supply VDDQ must be relatively fast, otherwise the association specification for power-down timing cannot be met.
[0027] Therefore, how to reduce system energy consumption and improve charge discharge efficiency while ensuring that the system can power down according to the power-down sequence is a current problem.
[0028] Figure 1 This is a schematic diagram of power discharge for existing memory chips, such as... Figure 1 As shown, for the power supply VDDQ which powers down slowly, a small resistor R is connected in parallel with the memory chip to provide a discharge circuit for the charge stored in the memory chip. This allows the charge stored in the memory chip to be quickly discharged to ground through this parallel branch when the system is powered off.
[0029] However, in the above parallel resistor scheme, the resistance value of resistor R usually cannot be too small. If the resistance value of R is too small, it will lead to a large discharge current, which will generate power consumption in this parallel branch during normal system operation, resulting in a significant increase in system power consumption, and in severe cases, it may even affect the normal operation of the system. However, if the discharge current is to be kept small, the power-down speed of VDDQ cannot meet the power-down timing requirements.
[0030] To address the aforementioned problems with existing technical solutions, this utility model provides a memory chip power discharge circuit. By setting a first switch and a first resistor in the discharge branch, wherein the resistance value of the first resistor is very small, and the first switch is controlled by the control circuit to turn on or off to discharge the power supply terminal of the memory chip, the discharge branch is turned on only when the system is powered off. This allows the value of the first resistor to be set to be relatively small, thereby enabling rapid power-off of the power supply VDDQ during system power-off.
[0031] Figure 2 This is a schematic diagram of the storage circuit according to an embodiment of the present invention, as shown below. Figure 2 As shown, the storage circuit includes a memory chip 1, a power supply circuit 2, and a memory chip power discharge circuit 3. It should be noted that... Figure 2The diagram only shows one memory chip 1, one power supply circuit 2, and one memory chip power discharge circuit 3. However, in a storage circuit, there can be multiple memory chips 1. Furthermore, a power supply circuit 2 and a memory chip power discharge circuit 3 need to be provided for each memory chip 1; that is, a corresponding number of power supply circuits 2 and memory chip power discharge circuits 3 need to be provided. This embodiment of the invention does not limit the specific number of memory chips. Additionally, one power supply circuit 2 can also supply power to multiple memory chips. This embodiment of the invention uses the example of one power supply circuit 2 corresponding to only one memory chip for illustration.
[0032] Memory chip 1 is the core component of a memory module. It performs temporary data exchange and storage functions within the computer system, storing and retrieving data during computer program execution. Specifically, a memory chip consists of many tiny transistors, which, together with capacitors, form a storage unit. Each storage unit can store one binary bit, either 0 or 1. When data needs to be stored, the memory controller chip selects the corresponding storage unit based on the instruction's address information. Then, depending on whether the data to be stored is 0 or 1, it controls the charging or discharging state of the capacitors. Data storage is achieved through the charging and discharging state of the capacitors.
[0033] The power supply circuit 2 is connected to the memory chip 1 via a first power supply terminal, and is used to supply power to the memory chip 1. The first power supply terminal is the power supply terminal of the memory chip 1. Specifically, the power supply circuit 2 employs power management technology to adapt to the power consumption changes and power stability requirements that may occur during the operation of the memory chip, ensuring the normal operation of the memory chip under various complex operating conditions. Specifically, the power management technology includes functions such as voltage regulation, current limiting, overcurrent protection, and short-circuit protection. In this embodiment of the invention, the power supply circuit 2 also optimizes the power response speed to ensure that the required energy support can be quickly provided when the memory chip performs high-speed data read and write operations, reducing power supply delay.
[0034] The memory chip power discharge circuit 3 is connected to the power supply circuit 2 and is used to control the discharge state of the power supply circuit. Specifically, the memory chip power discharge circuit 3 determines whether to change the operating state of the power supply circuit based on the controlled state of the memory chip 1, thereby discharging the first power supply terminal of the memory chip. Specifically, when the controlled state is the normal operating state, the memory chip power discharge circuit 3 enables the first power supply terminal of the memory chip to operate normally; when the system is in a power-off state, it enables the first power supply terminal of the memory chip 1 to discharge. Since the discharge only occurs when the system is in a power-off state, the resistance in the discharge branch can be set relatively small, thereby achieving rapid discharge of the first power supply terminal of the memory chip.
[0035] This embodiment of the invention establishes a discharge branch and a control circuit within the power discharge circuit of the memory chip. The discharge branch includes a first resistor and a first switch, connected in series between a ground terminal and a first power supply terminal of the memory chip. The control circuit is configured to control the first switch to turn on or off based on the controlled state of the memory chip, thereby discharging the first power supply terminal of the memory chip. Thus, the control circuit can control the on / off state of the first switch, allowing the resistance value of the first resistor to be set relatively small, thereby achieving rapid discharge of the first power supply terminal of the memory chip and reducing power consumption during normal system operation.
[0036] Figure 3 This is a circuit diagram of the power discharge circuit for the memory chip according to an embodiment of this utility model, as shown below. Figure 3 As shown, the memory chip power discharge circuit 3 includes a discharge branch 31 and a control circuit 32.
[0037] The discharge branch 31 includes a first resistor R1 and a first switch Q1, which are connected in series between the ground terminal and the first power supply terminal of the memory chip 1. The resistance value of the first resistor R1 is set to be relatively small. The first switch Q1 is controlled by the control circuit 32 to change its operating state, so as to enable the discharge branch 31 to conduct discharge when discharge is needed, and to disconnect the discharge branch 31 when discharge is not needed.
[0038] The control circuit 32 is configured to generate a control signal based on the control state of the memory chip 1 to control the discharge state of the first power supply terminal of the memory chip 1. Specifically, when the controlled state is the normal operating state, the control signal generated by the control circuit 32 is used to control the first switch Q1 to turn off, so that the first power supply terminal of the memory chip 1 does not discharge. When the controlled state is the power-off state, the control signal generated by the control circuit 32 is used to control the first switch Q1 to turn on, and the first power supply terminal of the memory chip 1 discharges. Thus, there is no leakage current in the discharge branch 31 during normal operation, so no energy consumption is generated. However, during power-off, the first power supply terminal of the memory chip can form a discharge path through the first resistor R1 with a small resistance and the turned-on first switch Q1, thereby achieving rapid discharge.
[0039] The control circuit 32 specifically includes a state detection circuit 321 and a control signal generation circuit 322. The state detection circuit 321 is configured to output a state signal based on the controlled state. In this embodiment, the controlled state includes a normal operating state and a power-off state. The state detection circuit 321 detects the controlled state and outputs a corresponding state signal to control the control signal generation circuit 322. The control signal generation circuit 322 is configured to output a switch control signal based on the state signal. The switch control signal is used to control the on / off state of the first switch Q1. In some embodiments, the state detection circuit 321 is implemented using a control chip. The working principle of the control chip is based on the electronic characteristics of semiconductor materials and micro-integrated circuit design. It collects system state information through an interface, and the collected electrical signals are sent to the analog-to-digital converter of the control chip for digitization. The digitized signals are then sent to a processor for calculation and analysis to determine the current state of the system. The processor processes the digitized signals according to a preset algorithm and threshold to determine the controlled state. The state detection circuit 321 is also connected to a second power supply terminal VCC to obtain power. The second power supply terminal is used to supply power to the power discharge circuit of the memory chip. This embodiment of the invention does not limit the specific type of the second power supply terminal. In some embodiments, the state detection circuit 321 is configured to output a high-level state signal in response to the controlled state being in normal operation, and to output a low-level state signal in response to the system being in a power-down state.
[0040] It should be noted that the first and second power supply terminals are implemented using different power sources. The first power supply terminal supplies power to the memory chips, specifically by converting the motherboard voltage through a power supply circuit. The voltage provided by the first power supply terminal is determined based on the type of memory chip. The second power supply terminal, on the other hand, supplies power to the control circuit and status detection circuit in the power discharge circuit of the memory chips. This can be achieved through a separate external power supply, such as an external 3.3V or 5V power supply.
[0041] The control signal generation circuit 322 includes a second resistor R2, a third resistor R3, a fourth resistor R4, and a second switch Q2. Specifically, the second resistor R2 and the third resistor R3 are connected in series between the second power supply terminal and the ground terminal, with the second resistor R2 connected to the second power supply terminal and the third resistor R3 connected to the ground terminal. The common terminal a1 of the second resistor R2 and the third resistor R3 is connected to the state detection circuit 321 to receive the state signal output by the state detection circuit 321. The fourth resistor R4 and the second switch Q2 are connected in series between the second power supply terminal and the ground terminal, with the fourth resistor R4 connected to the second power supply terminal and the second switch Q2 connected to the ground terminal. The control terminal of the second switch Q2 is connected to the common terminal a1 of the second resistor R2 and the third resistor R3.
[0042] In some embodiments, both the first switch Q1 and the second switch Q2 are implemented using NMOS transistors (N-channel Metal-Oxide-Semiconductor Field-Effect Transistors). In this case, the source of the second switch Q2 is connected to ground, the gate is connected to the common terminal of the second resistor R2 and the third resistor R3, and the drain is connected to the fourth resistor R4. The source of the first switch Q1 is connected to ground, the gate is connected to the common terminal of the fourth resistor R4 and the second switch Q2, and the drain is connected to the first resistor R1.
[0043] In some embodiments, the memory chip power discharge circuit further includes an energy storage capacitor C, which is connected between the control terminal and the ground terminal of the first switch Q1. In this embodiment, the energy storage capacitor C is specifically used to store the charge in the energy storage capacitor C when the first power supply terminal of the memory chip 1 is discharged during the first switch Q1 is turned on, so as to prevent the charge from being discharged too quickly and thus causing damage to the circuit components.
[0044] In this embodiment, both the first switch Q1 and the second switch Q2 are NMOS transistors. The following will combine... Figure 3 The circuit shown illustrates the operating state of the entire memory chip power discharge circuit.
[0045] When the system is working normally, the state detection circuit outputs a high level. At this time, the gate voltage of the second switch Q2 is high. According to the operating characteristics of the NMOS transistor, the second switch Q2 is in the on state. Therefore, the common terminal a2 of the fourth resistor R4 and the second switch Q2 is low, resulting in a low gate voltage of the first switch Q1 and the first switch being turned off. At this time, the discharge branch 31 is open, and the first power supply terminal of the memory chip 1 does not discharge.
[0046] When the system powers down, the state detection circuit 321 outputs a low level. At this time, the gate voltage of the second switch Q2 is low. According to the operating characteristics of the NMOS transistor, the second switch Q2 is in the off state. Therefore, the common terminal a2 of the fourth resistor R4 and the second switch Q2 is high, resulting in a high gate voltage of the first switch Q1, which then conducts. At this time, the discharge branch 31 forms a circuit, and the first power supply terminal of the memory chip 1 begins to discharge. Since the first resistor R1 is set very small, the first power supply terminal of the memory chip can discharge quickly through the discharge branch 31, thus meeting the timing requirements for system power-down.
[0047] It should be noted that in this embodiment of the present invention, both the first switch Q1 and the second switch Q2 can be set as PMOS transistors to achieve the same effect, and this embodiment of the present invention will not be described in detail here.
[0048] The technical solution of this utility model embodiment involves setting a discharge branch and a control circuit in the power discharge circuit of the memory chip. The discharge includes a first resistor and a first switch, which are connected in series between the ground terminal and the first power supply terminal of the memory chip. The control circuit is configured to control the first switch to be turned on or off according to the controlled state of the memory chip, thereby discharging the first power supply terminal of the memory chip. Thus, the control circuit can control the on or off of the first switch, allowing the resistance value of the first resistor to be set relatively small, thereby achieving rapid discharge of the first power supply terminal of the memory chip and reducing energy consumption during normal system operation.
[0049] Figure 4 This is a circuit diagram of the power discharge circuit for the memory chip according to another embodiment of the present invention. Figure 4 The memory chip power discharge circuit shown is... Figure 3 Similarly, only the second switch Q2 is replaced with a PMOS transistor, and the position of the fourth resistor R4 is adjusted accordingly. This embodiment of the invention will not elaborate on other components in the circuit.
[0050] Let's go to... Figure 4 The diagram illustrates the operating state of the memory chip power discharge circuit. Specifically, when the system is operating normally, the state detection circuit outputs a high level. At this time, the gate voltage of the second switch Q2 is high. According to the operating characteristics of the PMOS transistor, the second switch Q2 is in the off state. Meanwhile, the gate of the first switch Q1 is connected to ground, and the gate voltage of the first switch Q1 is low, meaning the first switch Q1 is off. At this time, the discharge branch 31 is open, and the first power supply terminal of the memory chip 1 does not discharge.
[0051] When the system is powered down, the state detection circuit outputs a low level. At this time, the gate voltage of the second switch Q2 is low, and the second switch Q2 is in the on state. At this time, the gate of the first switch Q1 is connected to the second power supply terminal VCC, and the gate voltage of the first switch Q1 is high, and the first switch Q1 is on. At this time, the discharge branch 31 is formed, and the first power supply terminal of the memory chip 1 begins to discharge.
[0052] It should be noted that the first switch Q1 can also be set as a PMOS transistor and the second switch Q2 can be set as an NMOS transistor. In this case, the working principle of the memory chip power discharge circuit 3 is similar to that when the first switch Q1 is an NMOS transistor and the second switch Q2 is a PMOS transistor. This embodiment of the present invention will not be described again.
[0053] The technical solution of this utility model embodiment involves setting a discharge branch and a control circuit in the power discharge circuit of the memory chip. The discharge includes a first resistor and a first switch, which are connected in series between the ground terminal and the first power supply terminal of the memory chip. The control circuit is configured to control the first switch to be turned on or off according to the controlled state of the memory chip, thereby discharging the first power supply terminal of the memory chip. Thus, the control circuit can control the on or off of the first switch, allowing the resistance value of the first resistor to be set relatively small, thereby achieving rapid discharge of the first power supply terminal of the memory chip and reducing energy consumption during normal system operation.
[0054] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A power discharge circuit for memory chips, characterized in that, The memory cell power discharge circuit comprises: a discharge branch comprising a first resistor and a first switch, the first resistor and the first switch being connected in series between a ground terminal and a first power supply terminal of the memory cell; a control circuit configured to control the first switch to be turned on or turned off according to a controlled state of the memory cell, so as to discharge the first power supply terminal of the memory cell.
2. The memory cell power discharge circuit of claim 1, wherein, The control circuit comprises: a state detection circuit configured to output a state signal according to the controlled state; a control signal generation circuit configured to output a switch control signal according to the state signal, the switch control signal being used to control the first switch to be turned on or turned off.
3. The memory cell power discharge circuit of claim 2, wherein, The state detection circuit is configured to output the state signal as a high level in response to the controlled state being a normal working state, and output the state signal as a low level in response to the controlled state being a power-off state.
4. The memory cell power discharge circuit of claim 3, wherein, The control signal generation circuit comprises: a second resistor; a third resistor connected in series with the second resistor between a second power supply terminal and the ground terminal, a common terminal of the second resistor and the third resistor being connected to the state detection circuit; a fourth resistor; a second switch connected in series with the fourth resistor between the second power supply terminal and the ground terminal.
5. The memory cell power discharge circuit of claim 4, wherein, A control terminal of the second switch is connected to the common terminal of the second resistor and the third resistor.
6. The memory cell power discharge circuit of claim 5, wherein, A control terminal of the first switch is connected to a common terminal of the fourth resistor and the second switch.
7. The memory cell power discharge circuit of claim 6, wherein, The first switch and the second switch are both N-type metal oxide semiconductor field effect transistors; wherein a source of the first switch is connected to the ground terminal, a gate of the first switch is connected to the common terminal of the fourth resistor and the second switch, and a drain of the first switch is connected to the first resistor; a source of the second switch is connected to the ground terminal, a gate of the second switch is connected to the common terminal of the second resistor and the third resistor, and a drain of the second switch is connected to the fourth resistor.
8. The memory cell power discharge circuit of claim 6, wherein, The first switch is an N-type metal oxide semiconductor field effect transistor, and the second switch is a P-type metal oxide semiconductor field effect transistor; wherein a source of the first switch is connected to the ground terminal, a gate of the first switch is connected to the common terminal of the fourth resistor and the second switch, and a drain of the first switch is connected to the first resistor; a source of the second switch is connected to the second power supply terminal, a gate of the second switch is connected to the common terminal of the second resistor and the third resistor, and a drain of the second switch is connected to the fourth resistor.
9. The memory cell power discharge circuit of claim 1, wherein, The memory cell power discharge circuit further comprises: a storage capacitor connected between a control terminal of the first switch and the ground terminal.
10. A storage circuit, characterized by comprising: The memory circuit comprises: at least one memory cell; at least one power supply circuit connected to the at least one memory cell through a first power supply terminal, the power supply circuit being used to supply power to the memory cell; at least one memory cell power discharge circuit according to any one of claims 1-9, the memory cell power discharge circuit being used to control a discharge state of the power supply circuit.