Pulse distributor circuit

By designing a pulse distributor circuit and combining piezoelectric conversion, optical isolation acquisition, and driving circuits, the shortcomings of existing pulse distributors with high speed, high resolution, high isolation, and multi-level output are solved, realizing fast, accurate signal distribution and stable transmission, which is suitable for various industrial automation equipment.

CN223987084UActive Publication Date: 2026-03-10TIANJIN C E ELECTRICAL AUTOMATION CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-12-12
Publication Date
2026-03-10

AI Technical Summary

Technical Problem

Existing technologies lack high-speed, high-resolution, high-isolation, and multi-level output pulse distributors, making it difficult to meet the high-precision control requirements of industrial automation equipment, especially in angle and angular velocity measurements where their application is not widespread.

Method used

A pulse distributor circuit was designed, including a piezoelectric conversion circuit, a threshold voltage conditioning circuit, an optical isolation acquisition circuit, a comparator circuit, and a driver circuit. High isolation and high resolution of the signal are achieved through an optocoupler, and differential signals are output using a comparator and a differential driver chip, making it suitable for devices of different voltage levels.

Benefits of technology

It achieves fast, accurate signal distribution and stable transmission, and is suitable for equipment of different voltage levels. It is applicable to industries such as steel, port machinery, and hoisting machinery, providing high-speed and precise signal distribution functions.

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Abstract

The utility model discloses a pulse distributor circuit, which comprises a piezoelectric conversion circuit, a threshold voltage conditioning circuit, an optical isolation acquisition circuit, a comparison circuit and a driving circuit, and can divide three paths of signal output (six paths of differential signals) of an incremental encoder into two parts to be output to different devices. The device is suitable for incremental encoders of different voltage levels, and high isolation of signals and a power supply is realized by receiving output signals of the encoders through the photoelectric coupler; accurate, reliable and fine comparison voltage is realized through a threshold voltage conditioning circuit, and the voltage is compared with an encoder output signal acquired by an optocoupler at a high speed and is output to a driving circuit through a comparator; the driving circuit outputs a differential pulse signal with certain driving capability, and finally provides the differential signal to different devices.
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Description

Technical Field

[0001] This utility model belongs to the field of electronic circuit technology, and specifically relates to a pulse distributor circuit. Background Technology

[0002] Currently, industrial automation is increasing, demanding ever-higher precision in control. Incremental encoders are crucial for this precision control, as they generate more pulses per revolution, resulting in higher resolution (up to 5400 pulses or more). Furthermore, automated control systems are often interconnected and located at considerable distances. Incremental encoders also offer advantages in cost-effectiveness and ease of use for angle and angular velocity measurements, making them suitable for a wide range of applications. This technological context necessitates a high-speed, high-resolution, high-isolation, multi-level output pulse distributor for use with control equipment. Utility Model Content

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a pulse distributor circuit for photoelectric isolation of three input signals and splitting them into two for transmission to two devices. The input signals can be clock signals, control signals, pulse signals, etc. The pulse distributor can quickly and accurately distribute the signals to the receiving ports of the two devices, thereby enabling the same set of signals to be sent to synchronous pulse signals that require different voltage levels. It also amplifies the input signals to ensure stable and reliable signal transmission.

[0004] This utility model is achieved through the following technical solution:

[0005] A pulse distributor circuit includes a piezoelectric conversion circuit, a threshold voltage conditioning circuit, an optical isolation acquisition circuit, a comparator circuit, and a drive circuit. The piezoelectric conversion circuit provides power; the threshold voltage conditioning circuit provides a comparator threshold voltage; the optical isolation acquisition circuit connects to an encoder signal; the input of the comparator circuit is connected to the output of both the optical isolation acquisition circuit and the threshold voltage conditioning circuit, comparing the encoder signal acquired by the optical isolation acquisition circuit with the threshold voltage provided by the threshold voltage conditioning circuit, and outputting a corresponding pulse square wave; the drive circuit is connected to the output of the comparator circuit, converting the pulse square wave output by the comparator circuit into a differential signal and providing a certain drive current to output a square wave signal.

[0006] In the above technical solution, the voltage conversion circuit includes multiple LDO chips.

[0007] In the above technical solution, the threshold voltage conditioning circuit includes: potentiometers R10 to R15, wherein the center taps of potentiometers R10 to R12 are connected together and then connected to the anode of diode array chip D4 and one end of ceramic capacitor C7, and the cathode of diode array chip D4 and the other end of ceramic capacitor C7 are grounded to M; the center taps of potentiometers R13 to R15 are connected together and then connected to the anode of diode array chip D6 and one end of ceramic capacitor C8, and the cathode of diode array chip D6 and the other end of ceramic capacitor C8 are grounded to GND; the center tap REF1 of potentiometers R10 to R12 is connected to comparator CP1 of the comparator circuit, and the center tap REF2 of potentiometers R13 to R15 is connected to comparator CP2 of the comparator circuit.

[0008] In the above technical solution, the optical isolation acquisition circuit includes: optocouplers OC1 to OC12; the encoder input signal A+ is connected to pin 1 of optocoupler OC1; pin 2 of optocoupler OC1 is connected to pin 1 of optocoupler OC2; pin 2 of optocoupler OC2 is connected to encoder input signal A-; encoder input signal A- is connected to pin 1 of optocoupler OC3; pin 2 of optocoupler OC3 is connected to pin 1 of optocoupler OC4; pin 2 of optocoupler OC4 is connected to encoder input signal A+; encoder input signal B+ is connected to pin 1 of optocoupler OC5; pin 2 of optocoupler OC5 is connected to pin 1 of optocoupler OC6; pin 2 of optocoupler OC6 is connected to encoder input signal B+. -; Encoder input signal B- is connected to pin 1 of optocoupler OC7; pin 2 of optocoupler OC7 is connected to pin 1 of optocoupler OC8; pin 2 of optocoupler OC8 is connected to encoder input signal B+; encoder input signal Z+ is connected to pin 1 of optocoupler OC9; pin 2 of optocoupler OC9 is connected to pin 1 of optocoupler OC10; pin 2 of optocoupler OC10 is connected to encoder input signal Z-; encoder input signal Z- is connected to pin 1 of optocoupler OC11; pin 2 of optocoupler OC11 is connected to pin 1 of optocoupler OC12; pin 2 of optocoupler OC12 is connected to encoder input signal Z+; the output pins of optocouplers OC1 to OC12 are all connected to the comparator circuit.

[0009] In the above technical solution, pin 4 of optocouplers OC1, OC3, OC5, OC7, OC9 and OC11 of the optical isolation acquisition circuit is connected to power supply 1P5; pin 4 of optocouplers OC2, OC4, OC6, OC8, OC10 and OC12 is connected to power supply 2P5.

[0010] In the above technical solution, pin 3 of optocoupler OC1 is connected to pin 7 of comparator CP1 in the comparator circuit; pin 3 of optocoupler OC2 is connected to pin 7 of comparator CP2 in the comparator circuit; pin 3 of optocoupler OC3 is connected to pin 6 of comparator CP1 in the comparator circuit; pin 3 of optocoupler OC4 is connected to pin 6 of comparator CP2; pin 3 of optocoupler OC5 is connected to pin 5 of comparator CP1; pin 3 of optocoupler OC6 is connected to pin 5 of comparator CP2; pin 3 of optocoupler OC7 is connected to pin 4 of comparator CP1; pin 3 of optocoupler OC8 is connected to pin 4 of comparator CP2; pin 3 of optocoupler OC9 is connected to pin 9 of comparator CP1; pin 3 of optocoupler OC10 is connected to pin 9 of comparator CP2; pin 3 of optocoupler OC11 is connected to pin 8 of comparator CP1; and pin 3 of optocoupler OC12 is connected to pin 8 of comparator CP2.

[0011] In the above technical solution, the comparison circuit includes comparator CP1 and comparator CP2.

[0012] In the above technical solution, resistor R16 is connected to pins 1 and 7 of comparator CP1. Pin 1 of comparator CP1 is connected to pull-up resistor R23 and serves as output terminal S1 connected to the drive circuit. Resistor R17 is connected to pins 2 and 5 of comparator CP1. Pin 2 of comparator CP1 is connected to pull-up resistor R22 and serves as output terminal S2 connected to the drive circuit. Resistor R19 is connected to pins 9 and 14 of comparator CP1. Pin 14 of comparator CP1 is connected to pull-up resistor R20 and then to pin 11 of comparator CP1. One end of resistor R18 is connected to REF1 of the threshold voltage conditioning circuit, and the other end is connected to pin 13 of comparator CP1. Pin 13 of comparator CP1 is connected to pull-up resistor R21 and serves as output terminal S3 connected to the drive circuit. To the drive circuit; resistor R24 ​​is connected to pins 1 and 7 of comparator CP2, pin 1 of comparator CP2 is connected to pull-up resistor R31 and serves as output terminal S4 connected to the drive circuit; resistor R25 is connected to pins 2 and 5 of comparator CP2, pin 2 of comparator CP2 is connected to pull-up resistor R30 and serves as output terminal S5 connected to the drive circuit; resistor R27 is connected to pins 9 and 14 of comparator CP2, pin 14 of comparator CP2 is connected to pull-up resistor R28 and connected to pin 11 of CP2; one end of resistor R26 is connected to REF2 of the threshold voltage conditioning circuit, and the other end is connected to pin 13 of comparator CP2, pin 13 of comparator CP2 is connected to pull-up resistor R29 and serves as output terminal S6 connected to the drive circuit.

[0013] In the above technical solution, the driving circuit includes: differential driving chip U1 and differential driving chip U2.

[0014] In the above technical solution, pin 1 of the differential driver chip U1 is connected to the output terminal S1 from the comparator circuit, pin 7 of the differential driver chip U1 is connected to the output terminal S2 from the comparator circuit, pin 9 of the differential driver chip U1 is connected to the output terminal S3 from the comparator circuit, and pin 15 of the differential driver chip U1 is grounded to M; pins 2 and 3, pins 6 and 5, and pins 10 and 11 of the differential driver chip U1 serve as three sets of differential signal outputs of the pulse distributor circuit; pin 1 of the differential driver chip U2 is connected to the output terminal S4 from the comparator circuit, pin 7 of the differential driver chip U2 is connected to the output terminal S5 from the comparator circuit, pin 9 of the differential driver chip U2 is connected to the output terminal S6 from the comparator circuit, and pin 15 of the differential driver chip U2 is grounded to GND; pins 2 and 3, pins 6 and 5, and pins 10 and 11 of the differential driver chip U2 serve as three sets of differential signal outputs of the pulse distributor circuit.

[0015] The advantages and beneficial effects of this utility model are as follows:

[0016] This invention relates to a pulse distribution circuit suitable for incremental encoders powered by 5-30V, with a pulse frequency ≥800KHz and an isolation voltage level of 2000VAC. It can split the three signal outputs (six differential signals) of an incremental encoder into two, outputting them to different devices. Applicable to incremental encoders of different voltage levels, it receives the encoder's output signal through an optocoupler, achieving high isolation between the signal and power supply. A threshold voltage conditioning circuit provides a precise and reliable comparison voltage, which is compared with the encoder's output signal acquired at high speed by the optocoupler. The comparison signal is then output to the drive circuit. The drive circuit outputs a differential pulse signal with a certain driving capability, and finally, this differential signal is provided to different devices. This pulse distribution circuit can be applied to various speed measurement fields, such as steel, port machinery, hoisting machinery, pressure machinery, glass machinery, printing machinery, textile machinery, woodworking machinery, and packaging machinery, providing high-speed and precise signal distribution capabilities. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of the voltage conversion circuit of the pulse distributor circuit of this utility model.

[0018] Figure 2 This is a circuit diagram of the threshold voltage conditioning circuit of the pulse distributor circuit of this utility model.

[0019] Figure 3 This is a circuit diagram of the optical isolation acquisition circuit of the pulse distributor circuit of this utility model.

[0020] Figure 4 This is a circuit diagram of the comparison circuit of the pulse distributor circuit of this utility model.

[0021] Figure 5This is a circuit diagram of the drive circuit of the pulse distributor circuit of this utility model.

[0022] Figure 6 This is an overall structural diagram of the pulse distributor circuit of this utility model.

[0023] For those skilled in the art, other related figures can be obtained from the above figures without any creative effort. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solution of the present invention will be further described below with reference to specific embodiments.

[0025] This embodiment provides a pulse distributor circuit for splitting the three square wave pulses (single-ended output A, B, Z) or (differential output A+, A-, B+, B-, Z+, Z-) output by an incremental encoder into two sets of six in-phase, different voltage level pulse square waves, which are then sent to speed measuring devices of different voltage levels. See appendix. Figure 6 The pulse distributor circuit includes a piezoelectric conversion circuit 1, a threshold voltage conditioning circuit 2, an optical isolation acquisition circuit 3, a comparator circuit 4, and a drive circuit 5. The piezoelectric conversion circuit 1 provides power; the threshold voltage conditioning circuit 2 provides the comparator threshold voltage; the optical isolation acquisition circuit 3 acquires (connects to) the encoder signal and also provides opto-isolation; the input of the comparator circuit 4 is connected to the output of the optical isolation acquisition circuit 3 and the output of the threshold voltage conditioning circuit 2, comparing the encoder signal acquired by the optical isolation acquisition circuit 3 with the threshold voltage provided by the threshold voltage conditioning circuit 2, and outputting a corresponding pulse square wave; the drive circuit 5 is connected to the output of the comparator circuit 4, converting the pulse square wave output by the comparator circuit 4 into a differential signal and providing a certain drive current to output a square wave signal.

[0026] The following is in conjunction with the appendix Figure 1 - Appendix Figure 5 This section provides a detailed description of the structure and connections of each circuit.

[0027] like Figure 1 As shown, the voltage conversion circuit includes LDO chip P1, LDO chip P2 and LDO chip P3.

[0028] Pin 1 of LDO chip P1 is connected to the cathode of diode D1, the positive terminal of electrolytic capacitor C1, and one end of ceramic capacitor C11; the negative terminal of electrolytic capacitor C1 and the other end of ceramic capacitor C11 are grounded to GND1; Pin 2 of LDO chip P1 is connected to the positive terminal of electrolytic capacitor C2, one end of ceramic capacitor C12, and one end of resistor R1; the negative terminal of electrolytic capacitor C2 and the other end of ceramic capacitor C12 are grounded to GND1; the other end of resistor R1 is connected in series with LED DS1 and then grounded to GND1; Pin 3 of LDO chip P1 is grounded to GND1.

[0029] Pin 1 of LDO chip P2 is connected to the cathode of diode D2, the positive terminal of electrolytic capacitor C3, and one end of ceramic capacitor C9; the negative terminal of electrolytic capacitor C3 and the other end of ceramic capacitor C9 are grounded to M; pin 2 of LDO chip P2 is connected to the positive terminal of electrolytic capacitor C4, one end of ceramic capacitor C13, and one end of resistor R2; the negative terminal of electrolytic capacitor C4 and the other end of ceramic capacitor C13 are grounded to M; the other end of resistor R2 is connected in series with LED DS2 and then grounded to M; pin 3 of LDO chip P2 is grounded to M.

[0030] Pin 1 of LDO chip P3 is connected to the cathode of diode D3, the positive terminal of electrolytic capacitor C5, and one end of ceramic capacitor C10; the negative terminal of electrolytic capacitor C5 and the other end of ceramic capacitor C10 are grounded to GND; pin 2 of LDO chip P3 is connected to the positive terminal of electrolytic capacitor C6, one end of ceramic capacitor C14, and one end of resistor R3; the negative terminal of electrolytic capacitor C6 and the other end of ceramic capacitor C14 are grounded to GND; the other end of resistor R3 is connected in series with LED DS3 and then grounded to GND; pin 3 of LDO chip P3 is grounded to GND.

[0031] like Figure 2 As shown, the threshold voltage conditioning circuit includes: six potentiometers: potentiometers R10 to R15, wherein the center taps of potentiometers R10 to R12 are connected together to the anode of diode array chip D4 and one end of ceramic capacitor C7, and the cathode of diode array chip D4 and the other end of ceramic capacitor C7 are grounded to M; the center taps of potentiometers R13 to R15 are connected together to the anode of diode array chip D6 and one end of ceramic capacitor C8, and the cathode of diode array chip D6 and the other end of ceramic capacitor C8 are grounded to GND; the center tap REF1 of potentiometers R10 to R12 is connected to pin 10 of comparator CP1; the center tap REF2 of potentiometers R13 to R15 is connected to pin 10 of comparator CP2.

[0032] like Figure 3As shown, the optical isolation acquisition circuit includes: 12 optocouplers: optocouplers OC1 to OC12; the encoder input signal A+ is connected to pin 1 of optocoupler OC1 via series resistor R4; pin 2 of optocoupler OC1 is connected to pin 1 of optocoupler OC2; pin 2 of optocoupler OC2 is connected to encoder input signal A-; encoder input signal A- is connected to pin 1 of optocoupler OC3 via series resistor R5; pin 2 of optocoupler OC3 is connected to pin 1 of optocoupler OC4; pin 2 of optocoupler OC4 is connected to encoder input signal A+; encoder input signal B+ is connected to pin 1 of optocoupler OC5 via series resistor R6; pin 2 of optocoupler OC5... Connect pin 1 of optocoupler OC6; connect pin 2 of optocoupler OC6 to encoder input signal B-; connect encoder input signal B- in series with resistor R7 to pin 1 of optocoupler OC7; connect pin 2 of optocoupler OC7 to pin 1 of optocoupler OC8; connect pin 2 of optocoupler OC8 to encoder input signal B+; connect encoder input signal Z+ in series with resistor R8 to pin 1 of optocoupler OC9; connect pin 2 of optocoupler OC9 to pin 1 of optocoupler OC10; connect pin 2 of optocoupler OC10 to encoder input signal Z-; connect encoder input signal Z- in series with resistor R9 to pin 1 of optocoupler OC11; connect pin 2 of optocoupler OC11 to... Pin 1 of OC12; pin 2 of optocoupler OC12 is connected to the encoder input signal Z+; pin 4 of optocouplers OC1, OC3, OC5, OC7, OC9, and OC11 is connected to power supply 1P5; pin 4 of optocouplers OC2, OC4, OC6, OC8, OC10, and OC12 is connected to power supply 2P5; pin 3 (+A1) of optocoupler OC1 is connected to pin 7 of comparator CP1; pin 3 (+A2) of optocoupler OC2 is connected to pin 7 of comparator CP2; pin 3 (-A1) of optocoupler OC3 is connected to comparator CP1. Pin 6 of OC4; pin 3-A2 of optocoupler OC4 is connected to pin 6 of comparator CP2; pin 3+B1 of optocoupler OC5 is connected to pin 5 of comparator CP1; pin 3+B2 of optocoupler OC6 is connected to pin 5 of comparator CP2; pin 3-B1 of optocoupler OC7 is connected to pin 4 of comparator CP1; pin 3-B2 of optocoupler OC8 is connected to pin 4 of comparator CP2; pin 3+Z1 of optocoupler OC9 is connected to pin 9 of comparator CP1; pin 3+Z2 of optocoupler OC10 is connected to pin 9 of comparator CP2; pin 3-Z1 of optocoupler OC11 is connected to pin 8 of comparator CP1; pin 3-Z2 of optocoupler OC12 is connected to pin 8 of comparator CP2.

[0033] like Figure 4As shown, the comparison circuit includes: comparator CP1 and comparator CP2; resistor R16 is connected to pins 1 and 7 of comparator CP1; pin 1 of comparator CP1 is connected to pull-up resistor R23 and serves as output terminal S1 connected to the drive circuit; resistor R17 is connected to pins 2 and 5 of comparator CP1; pin 2 of comparator CP1 is connected to pull-up resistor R22 and serves as output terminal S2 connected to the drive circuit; resistor R19 is connected to pins 9 and 14 of comparator CP1; pin 14 of comparator CP1 is connected to pull-up resistor R20 and then to pin 11 of comparator CP1; one end of resistor R18 is connected to REF1 of the threshold voltage conditioning circuit, and the other end is connected to pin 13 of comparator CP1; pin 13 of comparator CP1 is connected to pull-up resistor R21. The resistor R24 ​​is connected to pins 1 and 7 of comparator CP2. Pin 1 of comparator CP2 is connected to pull-up resistor R31 and is connected to the drive circuit as output S4. The resistor R25 is connected to pins 2 and 5 of comparator CP2. Pin 2 of comparator CP2 is connected to pull-up resistor R30 and is connected to the drive circuit as output S5. The resistor R27 is connected to pins 9 and 14 of comparator CP2. Pin 14 of comparator CP2 is connected to pull-up resistor R28 and then to pin 11 of CP2. One end of resistor R26 is connected to REF2 of the threshold voltage conditioning circuit, and the other end is connected to pin 13 of comparator CP2. Pin 13 of comparator CP2 is connected to pull-up resistor R29 and is connected to the drive circuit as output S6.

[0034] like Figure 5 As shown, the driving circuit includes: differential driving chip U1 and differential driving chip U2.

[0035] Pin 1 of the differential driver chip U1 is connected to the output terminal S1 from the comparator circuit, pin 7 of the differential driver chip U1 is connected to the output terminal S2 from the comparator circuit, pin 9 of the differential driver chip U1 is connected to the output terminal S3 from the comparator circuit, and pin 15 of the differential driver chip U1 is grounded to M. Pins 2 and 3, pins 6 and 5, and pins 10 and 11 of the differential driver chip U1 serve as the three sets of differential signal outputs 0A+1 and 0A-1, OB+1 and OB-1, and OZ+1 and OZ-1 of the pulse distributor circuit.

[0036] Pin 1 of the differential driver chip U2 is connected to the output terminal S4 from the comparator circuit, pin 7 of the differential driver chip U2 is connected to the output terminal S5 from the comparator circuit, pin 9 of the differential driver chip U2 is connected to the output terminal S6 from the comparator circuit, and pin 15 of the differential driver chip U2 is grounded to GND; pins 2 and 3, pins 6 and 5, and pins 10 and 11 of the differential driver chip U2 serve as the three sets of differential signal outputs 0A+2 and 0A-2, OB+2 and OB-2, and OZ+2 and OZ-2 of the pulse distributor circuit.

[0037] The present invention has been described above by way of example. It should be noted that, without departing from the core of the present invention, any simple modifications, alterations or other equivalent substitutions that can be made by those skilled in the art without creative effort fall within the protection scope of the present invention.

Claims

1. A pulse distributor circuit, characterized by: The voltage conversion circuit is used for providing power supply; the light isolation acquisition circuit is used for connecting the encoder signal; the input end of the comparison circuit is connected with the output end of the light isolation acquisition circuit and the output end of the threshold voltage conditioning circuit; and the output end of the comparison circuit is connected with the driving circuit.

2. The pulse distributor circuit of claim 1, wherein: The voltage conversion circuit comprises a plurality of LDO chips.

3. The pulse distributor circuit of claim 1, wherein: The comparison circuit comprises a comparator CP1 and a comparator CP2.

4. The pulse distributor circuit of claim 3, wherein: The threshold voltage conditioning circuit comprises potentiometers R10-R15, wherein the middle taps of the potentiometers R10-R12 are connected together and then connected to the anode of a diode array chip D4 and one end of a ceramic capacitor C7, the cathode of the diode array chip D4 and the other end of the ceramic capacitor C7 are grounded M; the middle taps of the potentiometers R13-R15 are connected together and then connected to the anode of a diode array chip D6 and one end of a ceramic capacitor C8, the cathode of the diode array chip D6 and the other end of the ceramic capacitor C8 are grounded GND; the middle tap REF1 of the potentiometers R10-R12 is connected to the comparator CP1 of the comparison circuit, and the middle tap REF2 of the potentiometers R13-R15 is connected to the comparator CP2 of the comparison circuit.

5. The pulse distributor circuit of claim 3, wherein: The light isolation acquisition circuit comprises optocouplers OC1-OC12, wherein the 1 pin of the optocoupler OC1 is connected to the encoder input signal A+; the 2 pin of the optocoupler OC1 is connected to the 1 pin of the optocoupler OC2; the 2 pin of the optocoupler OC2 is connected to the encoder input signal A-; the 1 pin of the optocoupler OC3 is connected to the encoder input signal A-; the 2 pin of the optocoupler OC3 is connected to the 1 pin of the optocoupler OC4; the 2 pin of the optocoupler OC4 is connected to the encoder input signal A+; the 1 pin of the optocoupler OC5 is connected to the encoder input signal B+; the 2 pin of the optocoupler OC5 is connected to the 1 pin of the optocoupler OC6; the 2 pin of the optocoupler OC6 is connected to the encoder input signal B-; the 1 pin of the optocoupler OC7 is connected to the encoder input signal B-; the 2 pin of the optocoupler OC7 is connected to the 1 pin of the optocoupler OC8; the 2 pin of the optocoupler OC8 is connected to the encoder input signal B+; the 1 pin of the optocoupler OC9 is connected to the encoder input signal Z+; the 2 pin of the optocoupler OC9 is connected to the 1 pin of the optocoupler OC10; the 2 pin of the optocoupler OC10 is connected to the encoder input signal Z-; the 1 pin of the optocoupler OC11 is connected to the encoder input signal Z-; the 2 pin of the optocoupler OC11 is connected to the 1 pin of the optocoupler OC12; the 2 pin of the optocoupler OC12 is connected to the encoder input signal Z+; and the output pins of the optocouplers OC1-OC12 are connected to the comparison circuit.

6. The pulse distributor circuit of claim 5, wherein: The 4-pin connection power supply 1P5 of the photoelectric coupler OC1, the photoelectric coupler OC3, the photoelectric coupler OC5, the photoelectric coupler OC7, the photoelectric coupler OC9 and the photoelectric coupler OC11 of the light separation acquisition circuit; the 4-pin connection power supply 2P5 of the photoelectric coupler OC2, the photoelectric coupler OC4, the photoelectric coupler OC6, the photoelectric coupler OC8, the photoelectric coupler OC10 and the photoelectric coupler OC12.

7. The pulse distributor circuit of claim 5, wherein: The 7-pin of the comparator CP1 of the comparison circuit connected to the 3-pin of the photoelectric coupler OC1; the 7-pin of the comparator CP2 of the comparison circuit connected to the 3-pin of the photoelectric coupler OC2; the 6-pin of the comparator CP1 of the comparison circuit connected to the 3-pin of the photoelectric coupler OC3; the 6-pin of the comparator CP2 connected to the 3-pin of the photoelectric coupler OC4; the 5-pin of the comparator CP1 connected to the 3-pin of the photoelectric coupler OC5; the 5-pin of the comparator CP2 connected to the 3-pin of the photoelectric coupler OC6; the 4-pin of the comparator CP1 connected to the 3-pin of the photoelectric coupler OC7; the 4-pin of the comparator CP2 connected to the 3-pin of the photoelectric coupler OC8; the 9-pin of the comparator CP1 connected to the 3-pin of the photoelectric coupler OC9; the 9-pin of the comparator CP2 connected to the 3-pin of the photoelectric coupler OC10; the 8-pin of the comparator CP1 connected to the 3-pin of the photoelectric coupler OC11; the 8-pin of the comparator CP2 connected to the 3-pin of the photoelectric coupler OC12.

8. The pulse distributor circuit of claim 4, wherein: The 1-pin and the 7-pin of the comparator CP1 connected to the resistance R16, the 1-pin of the comparator CP1 connected to the pull-up resistance R23 and connected to the driving circuit as the output end S1; the 2-pin and the 5-pin of the comparator CP1 connected to the resistance R17, the 2-pin of the comparator CP1 connected to the pull-up resistance R22 and connected to the driving circuit as the output end S2; the 9-pin and the 14-pin of the comparator CP1 connected to the resistance R19, the 14-pin of the comparator CP1 connected to the pull-up resistance R20 and connected to the 11-pin of the comparator CP1, one end of the resistance R18 connected to the REF1 of the threshold voltage conditioning circuit, the other end connected to the 13-pin of the comparator CP1, the 13-pin of the comparator CP1 connected to the pull-up resistance R21 and connected to the driving circuit as the output end S3; the 1-pin and the 7-pin of the comparator CP2 connected to the resistance R24, the 1-pin of the comparator CP2 connected to the pull-up resistance R31 and connected to the driving circuit as the output end S4; the 2-pin and the 5-pin of the comparator CP2 connected to the resistance R25, the 2-pin of the comparator CP2 connected to the pull-up resistance R30 and connected to the driving circuit as the output end S5; the 9-pin and the 14-pin of the comparator CP2 connected to the resistance R27, the 14-pin of the comparator CP2 connected to the pull-up resistance R28 and connected to the 11-pin of the comparator CP2, one end of the resistance R26 connected to the REF2 of the threshold voltage conditioning circuit, the other end connected to the 13-pin of the comparator CP2, the 13-pin of the comparator CP2 connected to the pull-up resistance R29 and connected to the driving circuit as the output end S6.

9. The pulse distributor circuit of claim 8, wherein: The driving circuit comprises: a differential driving chip U1 and a differential driving chip U2.

10. The pulse distributor circuit of claim 9, wherein: The 1-pin of the differential driving chip U1 connected to the output end S1 from the comparison circuit, the 7-pin of the differential driving chip U1 connected to the output end S2 from the comparison circuit, the 9-pin of the differential driving chip U1 connected to the output end S3 from the comparison circuit, the 15-pin of the differential driving chip U1 connected to the ground M; The 2nd and 3rd pins, the 6th and 5th pins, and the 10th and 11th pins of the differential drive chip U1 are used as three sets of differential signal outputs of the pulse distributor circuit; the 1st pin of the differential drive chip U2 is connected to the output terminal S4 from the comparison circuit, the 7th pin of the differential drive chip U2 is connected to the output terminal S5 from the comparison circuit, the 9th pin of the differential drive chip U2 is connected to the output terminal S6 from the comparison circuit, and the 15th pin of the differential drive chip U2 is connected to the ground GND; the 2nd and 3rd pins, the 6th and 5th pins, and the 10th and 11th pins of the differential drive chip U2 are used as three sets of differential signal outputs of the pulse distributor circuit.