Low-voltage self-checking reset circuit and chip

Abstract

The utility model provides a chip and a low-voltage self-checking reset circuit. The low-voltage self-checking reset circuit comprises a current generation module used for receiving an input voltage and generating a current; the first branch circuit is connected with the current generation module and the ground and comprises a first node, and the first branch circuit is conducted and stabilized at a first stable voltage when reaching a first starting voltage from the first node; the second branch circuit is connected with the current generation module and the ground and comprises a second node, and the second branch circuit is conducted and stabilized at a second stable voltage when reaching a second starting voltage from the second node; and the comparison module comprises a first input end, a second input end and a comparison output end, the first input end is connected with the first node, and the second input end is connected with the second node. According to the utility model, the working stability of the detection reset circuit can be improved.

Description

Technical Field

[0001] This utility model relates to the field of circuit technology, and in particular to a low-voltage self-test reset circuit and chip. Background Technology

[0002] A reset circuit is a common electronic circuit used to monitor the power supply voltage of a system and trigger a reset signal to the system or microcontroller when the voltage is abnormal (e.g., below a set threshold). Its main purpose is to ensure the system operates under reliable power conditions, preventing erroneous operation or data corruption due to insufficient power. For example, in a microcontroller system, a reset circuit protects the MCU from insufficient power, preventing program crashes or data corruption. In embedded devices, a reset circuit ensures the device starts under stable voltage conditions. In storage devices, a reset circuit prevents data loss or damage to storage units caused by power supply fluctuations.

[0003] In existing detection and reset circuits, one method involves using a transistor threshold voltage to achieve comparison switching. This means that the threshold voltage (such as Vbe or Vgs) of a transistor (e.g., BJT or MOSFET) is used to detect the power supply voltage. When the power supply voltage is higher or lower than the transistor's threshold, the circuit output state flips. However, because the transistor's threshold voltage is highly sensitive to temperature, this type of structure exhibits significant temperature drift in its trigger voltage. In other words, the threshold voltage changes with temperature, leading to instability in the trigger voltage detected by the circuit.

[0004] To address this temperature drift issue, another existing detection and reset circuit compares the input voltage with an externally introduced reference voltage. This involves introducing a stable reference voltage and comparing the detected voltage with the reference voltage using a comparator. When the detected voltage falls below the reference voltage, a reset signal is triggered. In this circuit, the temperature drift coefficient depends on the reference voltage, which is typically stable, resulting in a relatively small temperature drift coefficient. However, for the detection circuit to function correctly, the reference voltage must be established before the detected voltage. This means that the reference voltage must establish before the detected voltage in the timing sequence. If the detected voltage changes rapidly while the reference voltage establishes slowly, it can lead to timing errors in the reset signal (e.g., missed or false detections), resulting in unstable operation.

[0005] Therefore, how to improve the stability of the detection and reset circuit has become a technical problem that urgently needs to be solved in this field. Utility Model Content

[0006] The purpose of this invention is to provide a low-voltage self-test reset circuit and chip to solve the aforementioned technical problems in the prior art.

[0007] On the one hand, to achieve the above objectives, this utility model provides a low-voltage self-test reset circuit. This circuit includes a current generation module, a first branch, a second branch, and a comparison module. The current generation module receives the input voltage and generates current. Both the first and second branches are connected between the current generation module and ground. The current generated by the current generation module is supplied to the first and second branches respectively. As the input voltage changes, the voltages of the first node in the first branch and the second node in the second branch also change accordingly. During this period, there exists a voltage threshold such that the first voltage of the first node and the second voltage of the second node are equal. From this point onward, the first voltage is greater than the second voltage, and the signal output by the comparison module changes. Therefore, by observing the signal state output by the comparison module, it can be determined whether the input voltage has reached the voltage threshold, thereby resetting the downstream circuit.

[0008] On the other hand, in order to achieve the above objectives, this utility model also provides a chip, including any of the low-voltage self-test reset circuits provided by this utility model.

[0009] The low-voltage self-test reset circuit and chip provided by this utility model, through the cooperation of a current generation module, a first branch, a second branch, and a comparison module, can realize the detection of the input voltage status and output a detection signal. On this basis, the low-voltage self-test reset circuit does not require an external reference voltage, as the reference voltage is generated internally. This not only reduces the temperature drift effect but also reduces false detections and missed detections caused by timing issues between the external reference voltage and the detection voltage, thus improving the stability of the detection reset circuit and simplifying the circuit structure. Attached Figure Description

[0010] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0011] Figure 1 This is a structural diagram of a low-voltage self-test reset circuit provided in one embodiment of the present invention;

[0012] Figure 2 A voltage change curve of a low-voltage self-test reset circuit provided in one embodiment of this utility model;

[0013] Figure 3 This is a structural diagram of a low-voltage self-test reset circuit provided in another embodiment of the present invention;

[0014] Figure 4 This is a structural diagram of a low-voltage self-test reset circuit provided in another embodiment of the present invention;

[0015] Figure 5 for Figure 4 The diagram shows the structure of the detection section in the low-voltage self-test reset circuit of the embodiment shown.

[0016] Figure 6 for Figure 4 The voltage change curve of the low-voltage self-test reset circuit in the illustrated embodiment is shown in the figure. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without inventive effort are within the scope of protection of this utility model.

[0018] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0019] In the embodiments of this application, it should be noted that, unless otherwise specified, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0020] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0021] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0022] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could be A, B, C, A and B, A and C, B and C, or A and B and C.

[0023] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0024] In the embodiments of this application, the second terminal of each transistor is one of the source and the drain, and the third terminal of each transistor is the other of the source and the drain. For example, when the transistor is a P-type transistor, the third terminal is the source and the second terminal is the drain; for example, when the transistor is an N-type transistor, the second terminal is the drain and the third terminal is the source.

[0025] To address the instability and accuracy issues of existing technologies that rely on transistor thresholds or external reference voltages to detect voltage signals, this invention provides a low-voltage self-test reset circuit. The following embodiments will further explain this invention.

[0026] Figure 1 This is a structural diagram of a low-voltage self-test reset circuit provided in one embodiment of the present invention, as shown below. Figure 1 As shown, the low-voltage self-test reset circuit includes a current generation module, a first branch, a second branch, and a comparison module.

[0027] Specifically, the current generation module receives the input voltage, converts it into current, and provides the generated current to the first branch and the second branch. The first branch is connected to the current generation module and ground. The first branch includes a first node V1. The circuit components in the first branch enable the first branch to conduct when the first node reaches a first turn-on voltage. After the first branch is stably conducting, the voltage of the first node is basically stable at a first stable voltage. The second branch is connected in parallel with the first branch and is also connected to the current generation module and ground. The second branch includes a second node. The circuit components in the second branch enable the second branch to conduct when the second node reaches a second turn-on voltage. After the second branch is stably conducting, the voltage of the second node is basically stable at a second stable voltage. The first turn-on voltage, the second turn-on voltage, the first stable voltage, and the second stable voltage increase sequentially. The comparison module includes a first input terminal, a second input terminal, and a comparison output terminal. The first input terminal is connected to the first node, and the second input terminal is connected to the second node. When the input voltage changes, the on / off states of the first and second branches change, which in turn causes the voltages of the first and second nodes to change. Consequently, the comparison output terminal of the comparison module outputs different level signals. Therefore, the change in input voltage can be determined by the change in the level output by the comparison output terminal.

[0028] Figure 2 The voltage change curve of the low-voltage self-test reset circuit provided in one embodiment of this utility model is shown in the figure. Figure 1 and Figure 2 As shown, the working principle of this low-voltage self-test reset circuit is explained below:

[0029] (1) T1 stage

[0030] Both the first and second branches are initially in the off state. In the first branch, the input voltage V IN The voltage V1 of the first node and the voltage V2 of the second node gradually increase from a lower level, but this is not enough to make the first branch and the second branch conduct.

[0031] At this stage, the first voltage V1 and the second voltage V2 are basically the same, and the output terminal V of the comparator module is... IN-ok Output the first logic signal, for example, the first logic signal is a low level signal.

[0032] (2) T2 stage

[0033] With input voltage V IN As the voltage continues to rise, both the first voltage V1 and the second voltage V2 continue to rise. Since the conduction voltage of the first branch is less than the conduction voltage of the second switch, when the first voltage V1 and the second voltage V2 rise to the conduction voltage of the first branch, that is, the first turn-on voltage, the first branch will start to conduct first.

[0034] During this stage, the current flowing through the second node remains constant, and the rising slope of the second voltage V2 still follows the change in the input voltage. The output of the comparator module, V... IN-ok It still outputs a low-level signal.

[0035] (3) T3 stage

[0036] With input voltage V IN As the voltage increases further, both the first voltage V1 and the second voltage V2 increase further. When the second voltage V2 rises to the conduction voltage of the second branch, that is, the second turn-on voltage, the second branch also begins to conduct.

[0037] When both the first and second branches are fully conducting, the first voltage V1 and the second voltage V2 tend to stabilize. The first voltage V1 stabilizes at the first stable voltage, and the second voltage V2 stabilizes at the second stable voltage, so that the final stabilized first voltage V1 is greater than the second voltage V2.

[0038] In this process, there must be an input voltage V. IN threshold V T This makes the first voltage V1 equal to the second voltage V2. Using this threshold as a dividing point, as the input voltage V... IN As the voltage continues to increase, the first voltage V1 becomes greater than the second voltage V2, and the output of the comparator module V... IN-ok Change the output to a second logic signal, for example, a high-level signal, until both the first voltage V1 and the second voltage V2 are stable, keeping the first voltage V1 greater than the second voltage V2, and then output the comparison module's output V. IN-ok Maintain a high-level output signal.

[0039] As can be seen from the above process, with the input voltage V IN As the voltage changes from low to high, the low-voltage self-test reset circuit operates in different stages. In stage T1, both the first and second branches are off, and the voltage changes with the input voltage V. IN As voltage V1 and V2 increase, the first voltage V1 and the second voltage V2 increase synchronously, and the comparator module outputs a low-level signal. In stage T2, the first branch turns on first from off, while the second branch remains off, and the comparator module continues to output a low-level signal. In stage T3, the second branch also turns on from off until both the first and second branches are fully turned on. During this period, there is a voltage threshold V. T This makes the first voltage V1 and the second voltage V2 equal. From this point on, the first voltage V1 is greater than the second voltage V2, and the comparison module outputs a high-level signal.

[0040] Using the low-voltage self-test reset circuit provided in this embodiment, through the cooperation of the aforementioned current generation module, first branch, second branch, and comparison module, when the input voltage is less than or equal to this voltage threshold, the comparison module outputs a low-level signal; when the input voltage is greater than this voltage threshold, the comparison module outputs a high-level signal. This successfully realizes the detection of the input voltage state and the output of the detection signal. Furthermore, since the aforementioned voltage threshold is used as a reference voltage derived from within the low-voltage self-test reset circuit, no external reference voltage is required during the detection process. This not only reduces the temperature drift effect but also reduces false detections and missed detections caused by timing issues between the external reference voltage and the detection voltage, thereby improving the stability of the detection reset circuit.

[0041] Figure 3 The structural diagram of the low-voltage self-test reset circuit provided in another embodiment of the present invention is shown in the figure. Specifically, the current generation module includes a voltage conversion unit and a current mirror unit connected to each other. The voltage conversion unit receives the input voltage and converts the input voltage into a constant first current. The current mirror unit receives the first current and generates a second current that is proportional to the mirror of the first current, which is input to the first branch and the second branch respectively.

[0042] The first branch includes a first load, a first shunt unit, a current limiting unit, a first switching unit, and a first node. One end of the first load is connected to the output of the current mirror unit, and the other end is connected to the first node. The current limiting unit and the first switching unit are connected in series, and the entire series connection is parallel to the first shunt unit. Specifically, this first branch provides a first voltage V1 for the first node. The second current output by the current mirror unit reaches the first node after passing through the first load. When the first switching unit is in the off state, the line where the first switching unit is located is equivalent to an open circuit, and the second current flows entirely through the first shunt unit. The voltage of the first node is jointly determined by the first load and the first shunt unit. When the first switching unit is in the on state, the second current is shunt at the first node, with one part flowing through the first shunt unit and the other part flowing through the current limiting unit and the first switching unit. As the conduction level of the first switching unit changes, the voltage of the first node dynamically adjusts. When the first switching unit approaches a fully on state, the first voltage V1 tends to stabilize, determined jointly by the first load, the first shunt unit, the current limiting unit, and the first switching unit.

[0043] The second branch includes a second load, a second shunt unit, a second switching unit, and a second node. One end of the second load is connected to the output of the current mirror unit, and the other end is connected to the second node. The second shunt unit and the second switching unit are connected in parallel. Specifically, this second branch provides the second voltage V2 of the second node. The second current output by the current mirror unit reaches the second node after passing through the second load. When the second switching unit is in the off state, the line containing the second switching unit is equivalent to an open circuit, and the second current flows entirely through the second shunt unit. The voltage of the second node is jointly determined by the second load and the second shunt unit. When the second switching unit is in the on state, the second current is shunt at the second node, with one part flowing through the second shunt unit and the other part flowing through the second switching unit. As the conduction level of the second switching unit changes, the voltage of the second node dynamically adjusts. When the second switching unit approaches a fully on state, the second voltage V2 tends to stabilize, determined jointly by the second load, the second shunt unit, and the first switching unit.

[0044] The comparison module includes a first input terminal, a second input terminal, and a comparison output terminal. The first input terminal is connected to the first node and receives the first voltage V1 at the first node. The second input terminal is connected to the second node and receives the second voltage V2 at the second node. The comparison module compares the magnitudes of the first voltage V1 and the second voltage V2 and outputs a logic signal high / low through the comparison output terminal. For example, a high-level signal is output when the first voltage V1 is greater than the second voltage V2, and a low-level signal is output otherwise.

[0045] In this embodiment, the forward voltage of the first switching unit is less than the forward voltage of the second switch. This can be achieved by setting differences in the electronic component structures of the first and second switching units. For example, if the first switching unit includes a first transistor and the second switching unit includes a second transistor, then the effective area of ​​the first transistor is set to be greater than the effective area of ​​the second transistor, so that the forward voltage of the first switching unit is less than the forward voltage of the second switch. Alternatively, if the first switching unit includes a first diode and the second switching unit includes a second diode, then the effective area and / or doping concentration of the first and second diodes are set so that the forward voltage of the first switching unit is less than the forward voltage of the second switch.

[0046] Combination Figure 2 and Figure 3 As shown, the working principle of this low-voltage self-test reset circuit is explained below:

[0047] (1) T1 stage

[0048] Both the first and second switching units are initially in the off state. In the first branch, the second current flowing through the first node completely passes through the first shunt unit; in the second branch, the second current flowing through the second node completely passes through the second shunt unit. Input voltage VIN As the second current gradually increases from a lower level, the first voltage V1 at the first node and the second voltage V2 at the second node both gradually increase, but this is insufficient to turn on the first and second switching units.

[0049] At this stage, the first voltage V1 and the second voltage V2 are basically the same, and the output terminal V of the comparator module is... IN-ok Output the first logic signal, for example, the first logic signal is a low level signal.

[0050] (2) T2 stage

[0051] With input voltage V IN As the voltage continues to rise, the first current continues to increase, and the second current also continues to increase accordingly. Both the first voltage V1 and the second voltage V2 continue to rise. Since the turn-on voltage of the first switching unit is less than the turn-on voltage of the second switch, when the first voltage V1 and the second voltage V2 rise to the turn-on voltage of the first switching unit, the first switching unit begins to conduct first. In the first branch, the first switching unit is on, and part of the second current flowing through the first node is shunt by the current limiting unit and the first switching unit; in the second branch, the second switching unit remains off, and the second current flowing through the second node V1 is not shunt.

[0052] During this stage, the current flowing through the second node remains constant, and the rising slope of the second voltage V2 still follows the change in the input voltage; the current flowing through the first node is shunted, causing the rising slope of the first voltage V1 to decrease, thus the second voltage V2 will be slightly greater than the first voltage V1. The output of the comparator module, V... IN-ok It still outputs a low-level signal.

[0053] (3) T3 stage

[0054] With input voltage V IN As the voltage increases further, the first current increases further, and the second current also increases accordingly. The first voltage V1 and the second voltage V2 both increase further. When the second voltage V2 rises to the conduction voltage of the second switching unit, the second switching unit also begins to conduct.

[0055] During this stage, the current flowing through the second node is also diverted, causing the rise slope of the second voltage V2 to decrease. When both the first and second switching units are fully turned on, the first voltage V1 and the second voltage V2 tend to stabilize, and due to the impedance of the current limiting unit, the final stabilized first voltage V1 is greater than the second voltage V2.

[0056] In this process, there must be an input voltage V. IN threshold V TThis makes the first voltage V1 equal to the second voltage V2. Using this threshold as a dividing point, as the input voltage V... IN As the voltage continues to increase, the first voltage V1 becomes greater than the second voltage V2, and the output of the comparator module V... IN-ok Change the output to a second logic signal, for example, a high-level signal, until both the first voltage V1 and the second voltage V2 are stable, keeping the first voltage V1 greater than the second voltage V2, and then output the comparison module's output V. IN-ok Maintain a high-level output signal.

[0057] As can be seen from the above process, with the input voltage V IN The low-voltage self-test reset circuit operates in different stages as the voltage changes from low to high. In stage T1, both the first and second switching units are off, and the voltage changes with the input voltage V. IN As the input voltage V increases, the first voltage V1 and the second voltage V2 increase and change synchronously, and the comparator module outputs a low-level signal; in stage T2, the first switching unit turns on first from the off state, while the second switching unit remains off, and its voltage V increases with the input voltage V1. IN As the voltage increases, the increase in the first voltage V1 is slower than the increase in the second voltage V2, resulting in the first voltage V1 being less than the second voltage V2. The comparator module still outputs a low-level signal. In stage T3, the second switching unit also turns on from being off until both the first and second switching units are fully turned on. During this period, there is a voltage threshold that makes the first voltage and the second voltage equal. From this point on, the first voltage V1 is greater than the second voltage V2, and the comparator module outputs a high-level signal.

[0058] Figure 4 This is a structural diagram of a low-voltage self-test reset circuit provided in another embodiment of the present invention. Figure 5 for Figure 4 The diagram shows the structure of the detection section in the low-voltage self-test reset circuit of the embodiment shown. Figure 6 This utility model Figure 4 The voltage change curve of the low-voltage self-test reset circuit in the illustrated embodiment is shown in the figure. Figures 4 to 6 As shown, the low-voltage self-test reset circuit includes a detection section, a comparison module, a hysteresis module, and a logic delay module. The detection section includes a current generation module, a first branch, and a second branch.

[0059] The current generation module receives the input voltage V. INThe current is converted into a first current I1 and mirrored to form a second current I2, which is provided to the first and second branches. The first and second branches each include a switching unit, which generates voltage changes at the first and second nodes as the second current I2 changes. Further, the voltages at the first node V1 and the second node V2 are output to a comparison module for comparison. The output of the comparison module is connected to the input of the hysteresis module, and the output of the hysteresis module is input to a logic delay module. The logic delay module also has an enable signal receiver POR_EN to receive an enable control signal. Simultaneously, the hysteresis signal T_Hys output by the hysteresis module is returned to the current generation module. The delay components in the hysteresis module and the logic delay module resist power supply glitches, and the logic component in the logic delay module initializes the module's output state.

[0060] The current generation module includes a voltage conversion unit and a current mirror unit connected to each other. The voltage conversion unit includes a buffer B and a first resistor R1. The current mirror unit includes a third transistor M3, a fourth transistor M4, and a fifth transistor M5. It should be noted that other circuit structures capable of implementing a current mirror are also within the scope of this invention. This embodiment is merely described as one specific circuit form for implementing the current mirror function and does not constitute the sole limitation on the current mirror unit.

[0061] The first branch includes a first load, a first shunt unit, a current limiting unit, a first switching unit, and a first node V1. The first load includes a fourth resistor R4, the first shunt unit includes a second resistor R2, the current limiting unit includes a third resistor R3, and the first switching unit includes a first transistor Q1.

[0062] The second branch includes a second load, a second shunt unit, a second switching unit, and a second node V2. The second load includes a sixth resistor R6, the second shunt unit includes a fifth resistor R5, and the second switching unit includes a second transistor Q2.

[0063] One end of the first resistor R1 is connected to the first terminal of the third transistor M3 in the current mirror unit, and the other end is grounded. The input terminal of buffer B receives the input voltage V. IN The output of buffer B is connected to node V between the third transistor M3 and the first resistor R1. OUT .

[0064] The first and second terminals of the third transistor M3, the first terminal of the fourth transistor M4, and the first terminal of the fifth transistor M5 are connected and connected to the first resistor R1. The third terminals of the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are connected and connected to a power supply. The second terminal of the fourth transistor M4 is connected to the first terminal of the fourth resistor R4, providing a second current I2 to the first branch. The second terminal of the fifth transistor M5 is connected to the sixth resistor R6, providing a second current I2 to the second branch.

[0065] The second terminal of the fourth resistor R4 is connected to the first node V1. The second resistor R2 is connected between the first node V1 and ground. The first terminal of the first transistor Q1 is connected to the first terminal of the second transistor Q2, the second terminal of the first transistor Q1 is connected to the second terminal of the second transistor Q2 and grounded, and the third terminal of the first transistor Q1 is connected to the second terminal of the third resistor R3. The first terminal of the third resistor R3 is connected to the first node V1.

[0066] One end of the sixth resistor R6 is connected to the second terminal of the fifth transistor M5, and the other end is connected to the second node V2. The fifth resistor R5 is connected between the second node V2 and ground. The third terminal of the second transistor Q2 is connected to the second node V2. The fifth resistor R5 is the same as the second resistor R2.

[0067] The non-inverting and inverting inputs of the comparison module at the first node V1 and the second node V2 are connected (or they can be reversed, depending on the system's output logic requirements). The third transistor M3 to the fifth transistor M5 in the current mirror unit can be implemented using MOS transistors, or other transistor structures. In this embodiment, a PMOS transistor is used as an example.

[0068] Optionally, the first resistor R1, the second resistor R2, and the fifth resistor R5 each comprise a resistor network, and the output of the hysteresis module is connected to each resistor network to control and change the equivalent values ​​of the first resistor R1, the second resistor R2, and the fifth resistor R5, thereby achieving hysteresis characteristics when the input voltage rises and falls. Simultaneously, by adjusting each resistor, high-frequency interference in the input voltage can be filtered out, jitter and false triggering can be reduced, and anti-glitches can be improved.

[0069] The self-test process of this embodiment is described as follows:

[0070] T1: In this stage, the input voltage V IN The generated current I1 is mirrored to the first and second branches through the current mirror unit. The voltage rise slope of the first node V1 and the second node V2 follows the input voltage V. IN During this phase, the voltages of the first node V1 and the second node V2 have not reached the base-emitter turn-on voltage Vbe that triggers them. The first transistor Q1 and the second transistor Q2 are not turned on. During this phase, the transistors that are not turned on consume the current in the branch, and the mirror current I2 in the two branches only affects the voltage rise of the nodes.

[0071] T2: Input voltage V INAs the voltage rises, the voltage at the first node V1 reaches the Vbe of the first transistor Q1, and the first transistor Q1 turns on. After the first transistor Q1 turns on, some current flows from the first node V1 through the collector-emitter (CE) path of the first transistor Q1 to ground, thereby reducing the voltage rise slope of the first node V1. At this time, the voltage at the second node V2 has not yet reached the Vbe of the second transistor Q2, and the second transistor Q2 is still not turned on. The current at the second node V2 is not affected, and the voltage rise slope of the second node V2 follows the input voltage Vbe. IN In the first branch, the second resistor R2 is the load resistor, which mainly determines the voltage of the first node V1 and directly affects the voltage rise rate and amplitude of the first node V1; the third resistor R3 is the current limiting resistor, which mainly limits the current flowing through the first transistor Q1 to prevent the first transistor Q1 from being damaged by overcurrent. When the first transistor Q1 is turned on, the third resistor R3 determines the magnitude of the shunt current flowing to ground.

[0072] T3: With the input voltage V IN As the voltage rises further, the voltage at the second node V2 also reaches the Vbe of the second transistor Q2. The first transistor Q1 turns on, and the second transistor Q2 turns on as well. The conduction of the first transistor Q1 partially diverts the current flowing through the first node V1, but the voltage at the first node V1 continues to rise. After the second transistor Q2 turns on, the voltage at the second node V2 is limited by the conduction of the second transistor Q2, causing the rising slope of the second node V2 to decrease and eventually stabilize, ultimately being clamped near the Vbe of the second transistor Q2. During this stage, the voltage at the first node V1 will eventually be greater than the voltage at the second node V2.

[0073] During the changes in voltage at the first node V1 and voltage at the second node V2, there will be a specific input voltage V. IN =V T This makes the voltages of the first node V1 and the second node V2 the same, this specific V T It is the threshold voltage to be detected.

[0074] The specific derivation formula for this threshold voltage is as follows:

[0075]

[0076]

[0077]

[0078] in, For the first current, The first resistor, For the second resistor, The third resistor, Input voltage, Where is the voltage at the first node, and K is the proportionality coefficient of the mirror current. This is the voltage drop across the third resistor, which is also the voltage difference between the first transistor Q1 and the second transistor Q2.

[0079] When the voltage of the first node Voltage of the second node When they are equal, that is The turn-on voltage of the second transistor Q2 Then we have:

[0080]

[0081]

[0082] Differentiating both sides of the equation with respect to temperature, we get:

[0083]

[0084] Then we have:

[0085] The key design guiding formula is:

[0086]

[0087] Based on the above design As can be seen from the formula, different voltages can be detected by setting a coefficient K.

[0088] Furthermore, when V1=V2, the hysteresis trigger signal T_Hys output by the hysteresis module undergoes a logic transition (e.g., high-low, low-high), shorting a portion of the first resistor R1, the second resistor R2, and the fifth resistor R5, forming a power-down hysteresis voltage V_Hys. In other words, the hysteresis module adds two different thresholds—rising and falling—for detection. When the input voltage... When the input voltage changes from low to high, the switching point of the circuit is a higher threshold. When the voltage changes from high to low, the switching point is at a lower threshold, thus avoiding the input voltage from approaching the threshold V. T This is due to jitter caused by slight fluctuations. The final reset signal output by the logic delay module has a delay T_D, meaning that the input voltage V... IN Reaching threshold voltage V T After returning to the normal range, the T_D signal is released after a certain delay to ensure that the system starts under stable power conditions.

[0089] When the input voltage When the voltage changes and gradually decreases, the voltage of the first node V1 and the voltage of the second node V2 gradually decrease accordingly. The first transistor Q1 and the second transistor Q2 are turned off accordingly. The voltage of the first node V1 is less than or equal to the voltage of the second node V2. The logic signal at the output of the comparison module flips, and the signal output by the logic delay module also flips accordingly. The specific process will not be described in detail.

[0090] The low-voltage self-test reset circuit provided in this embodiment exhibits low temperature drift at the detection point and can perform self-testing without a reference voltage. A temperature compensation mechanism provides a stable voltage reference with low temperature drift, ensuring that the detection voltage does not drift due to temperature changes and guaranteeing detection accuracy. Simultaneously, the circuit itself can generate a stable voltage reference, completing voltage detection without the need for an external reference voltage input, simplifying circuit design and improving the independence and reliability of the self-test function.

[0091] Optionally, in one embodiment, a chip is provided that includes any of the low-voltage self-test reset circuits provided by this utility model.

[0092] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0093] The above are merely preferred embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural or circuit transformations made based on the description and drawings of this utility model, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A low voltage self-checking reset circuit, characterized by, The low-voltage self-check reset circuit comprises: a current generation module configured to receive an input voltage and generate a current; a first branch connected to the current generation module and a ground, comprising a first node, the first branch being turned on and stabilized at a first stable voltage when the first node reaches a first turn-on voltage; a second branch connected to the current generation module and the ground, comprising a second node, the second branch being turned on and stabilized at a second stable voltage when the second node reaches a second turn-on voltage, the first turn-on voltage, the second turn-on voltage, the second stable voltage and the first stable voltage increasing in turn; and a comparison module comprising a first input end, a second input end and a comparison output end, the first input end being connected to the first node, and the second input end being connected to the second node.

2. The low-voltage self-check reset circuit according to claim 1, wherein the first branch further comprises a first load, a first shunt unit, a current limiting unit and a first switch unit, one end of the first load is connected to an output end of the current generation module, the other end of the first load is connected to the first node, the current limiting unit and the first switch unit are connected in series, the series connection is connected in parallel with the first shunt unit, and the first turn-on voltage is a turn-on voltage of the first switch unit.

3. The low-voltage self-check reset circuit according to claim 2, wherein the second branch further comprises a second load, a second shunt unit and a second switch unit, one end of the second load is connected to the output end of the current generation module, the other end of the second load is connected to the second node, the second shunt unit and the second switch unit are connected in parallel, and the second turn-on voltage is a turn-on voltage of the second switch unit.

4. The low-voltage self-check reset circuit according to claim 3, wherein the first load comprises a fourth resistor, one end of the fourth resistor is connected to the current generation module, and the other end is connected to the first node; the first shunt unit comprises a second resistor, the second resistor is connected between the first node and the ground; the current limiting unit comprises a third resistor, one end of the third resistor is connected to the first switch unit, and the other end is connected to the first node; the first switch unit comprises a first transistor, a first end and a second end of the first transistor are connected to the second switch unit respectively, and a third end of the first transistor is connected to the current limiting unit; the second load comprises a sixth resistor, one end of the sixth resistor is connected to the current generation module, and the other end is connected to the second node; the second shunt unit comprises a fifth resistor, the fifth resistor is connected between the second node and the ground; and the second switch unit comprises a second transistor, a first end and a second end of the second transistor are connected to the first switch unit respectively, and a third end of the second transistor is connected to the second node. The current generation module comprises a voltage conversion unit and a current mirror unit, one end of the voltage conversion unit receives the input voltage, and the other end of the voltage conversion unit is connected to the current mirror unit. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5. The low voltage self-checking reset circuit of claim 1, wherein, ​ 6. The low-voltage self-checking reset circuit according to claim 5, wherein the voltage conversion unit comprises a buffer and a first resistor; one end of the first resistor is connected to the current mirror unit, and the other end is grounded; the input end of the buffer receives the input voltage, and the output end of the buffer is connected to a node between the current mirror unit and the first resistor.

7. The low-voltage self-checking reset circuit according to claim 5, wherein the current mirror unit comprises a third transistor, a fourth transistor and a fifth transistor; the first end and the second end of the third transistor, the first end of the fourth transistor and the first end of the fifth transistor are connected, and are connected to the voltage conversion unit; the third end of the third transistor, the third end of the fourth transistor and the third end of the fifth transistor are connected, and are connected to a power supply; the second end of the fourth transistor is connected to the first branch; the second end of the fifth transistor is connected to the second branch.

8. The low-voltage self-checking reset circuit according to claim 1, wherein the current generation module, the first branch and the second branch respectively comprise a resistor network; the low-voltage self-checking reset circuit further comprises a hysteresis module, the input end of the hysteresis module is connected to the comparison output end, and the output end of the hysteresis module is connected to each resistor network respectively to control the change of the equivalent value of each resistor network. the low-voltage self-checking reset circuit further comprises a logic delay module, and the logic delay module is connected to the output end of the hysteresis module. a low-voltage self-checking reset circuit according to any one of claims 1 to 9. ​ 9. The low voltage self-checking reset circuit of claim 8, wherein, ​ 10. A chip, characterized by ​

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