Chip stacking packaging structure and electronic equipment

Abstract

The utility model provides a chip stacking packaging structure and electronic equipment, and is suitable for the technical field of semiconductor packaging. The structure comprises a substrate and a chip structure arranged on the substrate, wherein the chip structure comprises a first MOS chip, a second MOS chip and a conductive lead; the substrate, the first MOS chip and the second MOS chip are sequentially stacked along a first direction; the substrate, the first MOS chip and the second MOS chip are electrically connected in sequence; one end of the conductive lead is connected with the second MOS chip, and the other end is connected with the substrate. In this way, the packaging size of the chip stacking packaging structure can be reduced under the condition that it is guaranteed that the impedance is small, and the occupied area of the chip stacking packaging structure in electronic equipment is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a chip stacking packaging structure and electronic device. Background Technology

[0002] With the continued growth in demand for electronic components, especially the trend towards miniaturization, thinning, and high integration of electronic devices, the requirements for chip packaging technology are becoming increasingly stringent. Increasing packaging density not only helps reduce the size of electronic products but also improves product performance. Existing metal-oxide-semiconductor (MOS) packaging technologies mostly employ single-chip packaging designs, which suffer from relatively high impedance. To reduce impedance, multiple MOS chips are typically arranged in parallel on a circuit board. However, while this layout reduces chip impedance, it occupies more printed circuit board (PCB) space, limiting the size optimization of electronic devices. Utility Model Content

[0003] To address the issue of high PCB board area occupied by chip layout, this application provides a chip stacking packaging structure.

[0004] In a first aspect, embodiments of this application provide a chip stacking package structure, including a substrate and a chip structure disposed on the substrate. The chip structure includes a first MOS chip, a second MOS chip, and conductive leads. The substrate, the first MOS chip, and the second MOS chip are stacked sequentially along a first direction. The substrate, the first MOS chip, and the second MOS chip are electrically connected sequentially. One end of the conductive lead is connected to the second MOS chip, and the other end is connected to the substrate.

[0005] It is understood that the chip stacking package structure provided in this application embodiment stacks two MOS chips together while ensuring parallel connection, which can reduce the package size of the chip stacking package structure and reduce the area occupied by the chip stacking package structure in electronic devices while ensuring low impedance.

[0006] In one possible implementation of the first aspect described above, the chip structure further includes a first connection structure and a second connection structure; the first MOS chip includes a first substrate and a first chip circuit disposed on the first substrate; the second MOS chip includes a second substrate and a second chip circuit disposed on the second substrate; the first chip circuit is connected to the substrate along a first direction through the first connection structure, the first substrate and the second substrate are connected along the first direction through the second connection structure, the second chip circuit is connected to one end of a conductive lead, and the other end of the conductive lead is connected to the substrate.

[0007] In one possible implementation of the first aspect described above, the first connection structure includes a first substructure disposed on the surface of the substrate and a second substructure disposed on the surface of the first chip circuit. The chip structure further includes a third connection structure disposed on the surface of the second MOS chip. The third connection structure is electrically connected to the second chip circuit. One end of the conductive lead is connected to the fourth connection structure, and the other end of the conductive lead is connected to the first substructure on the substrate. The first chip circuit is connected to the substrate along the first direction through the first substructure and the second substructure.

[0008] In one possible implementation of the first aspect described above, the first chip circuit is soldered to the substrate along a first direction via a first substructure.

[0009] In one possible implementation of the first aspect described above, the second connection structure is a conductive adhesive, and the first substrate and the second substrate are bonded together along a first direction by the conductive adhesive.

[0010] In one possible implementation of the first aspect described above, the first substructure on the substrate surface is a pad, the second substructure is a copper pillar, and the third connection structure is a pad.

[0011] In one possible implementation of the first aspect described above, the first substrate includes a first metal layer and a first silicon layer; the second substrate includes a second metal layer and a second silicon layer; the first chip circuit, the first silicon layer, and the first metal layer are stacked along a first direction; the second metal layer, the second silicon layer, and the second chip circuit are stacked along the first direction.

[0012] In one possible implementation of the first aspect described above, an external connection structure is also included, the substrate includes opposing first and second surfaces; the first MOS chip is fixed to the first surface of the substrate along a first direction; and the external connection structure is fixed to the second surface of the substrate.

[0013] In one possible implementation of the first aspect described above, a molding compound structure is also included, which is disposed on a first surface of the substrate and is used to encapsulate the chip structure.

[0014] Secondly, embodiments of this application provide an electronic device including a chip stacking package structure according to any one of the first aspects. Attached Figure Description

[0015] Figure 1 According to some embodiments of this application, a schematic diagram of a chip stacked packaging structure is shown;

[0016] Figure 2 According to some embodiments of this application, a schematic diagram of a chip stacked packaging structure is shown;

[0017] Figure 3According to some embodiments of this application, a schematic diagram of a chip stacked packaging structure is shown;

[0018] Figure 4 According to some embodiments of this application, a schematic diagram of a chip stacked packaging structure is shown;

[0019] Figure 5 According to some embodiments of this application, a schematic diagram of a chip stacked packaging structure is shown;

[0020] Figure 6 According to some embodiments of this application, a schematic diagram of a molded chip stacked package structure is shown;

[0021] Figure 7 According to some embodiments of this application, a flowchart of a method for fabricating a chip stacked packaging structure is shown;

[0022] Figures 8A-8G According to some embodiments of this application, a partial structural schematic diagram of the fabrication process of a chip stacked packaging structure is shown;

[0023] Figure 9A According to some embodiments of this application, an external dimension diagram of a single MOS chip is shown;

[0024] Figure 9B According to some embodiments of this application, an external dimension diagram of a two-MOS chip stacked package structure is shown;

[0025] Figure 10A According to some embodiments of this application, a circuit diagram of a single MOS chip is shown;

[0026] Figure 10B According to some embodiments of this application, a circuit diagram of a chip stacked package structure formed by stacking two chips is shown. Detailed Implementation

[0027] This application provides a chip stacking packaging structure and an electronic device. To more clearly illustrate the technical solutions and advantages of this application, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0028] The technical terms involved in the embodiments of this application will be explained below.

[0029] Die attach film (DAF): A high-performance adhesive film used to bond or connect chips to substrates / frames.

[0030] Package (PKG): The finished product after plastic sealing.

[0031] Wire bonding (WB): It uses metal wires to achieve electrical interconnection between chips and substrates and information exchange between chips.

[0032] Molding: refers to sealing the packaged object using molding compound.

[0033] Molding compound: Generally a mixture of resin and silica, etc., and is available in cylindrical and powder forms.

[0034] Molding module: A mold used for molding products, consisting of an upper mold and a lower mold.

[0035] Substrate: refers to the copper-clad laminate used in semiconductor packaging to support chips.

[0036] Flip chip (FC): The chip is directly interconnected downwards to a substrate, carrier, or circuit board via bumps on the chip.

[0037] The chip stacking packaging structure provided in the embodiments of this application is described below.

[0038] Figure 1 A schematic diagram illustrating a chip stacking package structure according to an embodiment of this application is shown, as follows: Figure 1 As shown, the chip stacked package structure 100 includes a substrate 200 and a chip structure 300 disposed on the substrate 200. The chip structure 300 includes a first MOS chip 310, a second MOS chip 320, and conductive leads 330. The substrate 200, the first MOS chip 310, and the second MOS chip 320 are stacked sequentially along a first direction; and the substrate 200, the first MOS chip 310, and the second MOS chip 320 are electrically connected sequentially; one end of the conductive lead 330 is connected to the second MOS chip 320, and the other end is connected to the substrate 200.

[0039] It is understood that the chip stacking package structure provided in this application embodiment stacks two MOS chips together while ensuring parallel connection, which can reduce the package size of the chip stacking package structure and reduce the area occupied by the chip stacking package structure in electronic devices while ensuring low impedance.

[0040] It is understood that the chip stacking package structure including the first MOS chip 310 and the second MOS chip 320 in the embodiments of this application is only an exemplary illustration. In some embodiments, the chip stacking package structure may also include more MOS chips, and the embodiments of this application do not limit this.

[0041] In some embodiments, the conductive leads 330 of the chip structure 300 can be configured as four, with one end of each of the four conductive leads connected to the first source pin of the second MOS chip 320 (i.e., corresponding to...). Figure 10B S1 in the middle), the second source pin (i.e., the corresponding Figure 10B S2 in the middle), the first gate pin (i.e., the corresponding Figure 10B G1 in the middle), the second gate pin (i.e., the corresponding Figure 10B The G2 in the middle is connected, and the other end is connected to the substrate 200.

[0042] In some embodiments, the first MOS chip 310 can be fixed to the substrate 200 along a first direction, and the second MOS chip 320 can be fixed to the first MOS chip 310 along the first direction. The first direction can be as follows: Figure 1 As shown in the vertical y-direction, the first MOS chip 310 and the second MOS chip 320 are stacked on the substrate 200.

[0043] In some embodiments, the substrate 200 may be a platen for carrying chips in the semiconductor packaging field, a copper-clad foil layer, or other structures, which are not limited here.

[0044] Figure 2 A schematic diagram illustrating a chip stacking package structure according to an embodiment of this application is shown, as follows: Figure 2 As shown, the chip structure 300 further includes a first connection structure 311 and a second connection structure 321. The first MOS chip 310 further includes a first substrate 312 and a first chip circuit 313 disposed on the first substrate 312. The second MOS chip 320 further includes a second substrate 322 and a second chip circuit 323 disposed on the second substrate. The first chip circuit 313 is connected to the substrate 200 along a first direction through the first connection structure 311. The first substrate 312 and the second substrate 322 are connected along the first direction through the second connection structure 321. The second chip circuit 320 is connected to one end of a conductive lead 330, and the other end of the conductive lead 330 is connected to the substrate 200.

[0045] In this embodiment of the application, the first MOS chip 310 can be flipped on the substrate, and the second MOS chip 320 can be upright and bonded to the first MOS chip. In some embodiments, the first MOS chip 310 can be referred to as a flip-chip MOS chip, and the second MOS chip 320 can be referred to as a bonded MOS chip.

[0046] In some embodiments, the material of the second connection structure 321 can be a conductive adhesive, and the first substrate 312 and the second substrate 322 are bonded together along a first direction by the conductive adhesive. For example, the second connection structure 321 can be a die-attached film (DAF) formed by a conductive adhesive, with the first surface of the die-attached film connected to the first substrate 312 in the first MOS chip 310, and the second surface of the die-attached film opposite to the first surface connected to the second substrate 322 in the second MOS chip 320.

[0047] Figure 3 A schematic diagram illustrating a chip stacking package structure according to an embodiment of this application is shown, as follows: Figure 3 As shown, the first connection structure 311 further includes a first substructure 3111 disposed on the surface of the substrate 200. The first connection structure 311 may also include a second substructure 3112 disposed on the surface of the first chip circuit 313. The chip structure 300 further includes a third connection structure 324 disposed on the surface of the second MOS chip, and the third connection structure 324 is electrically connected to the second chip circuit. One end of the conductive lead 330 is connected to the third connection structure 324, and the other end of the conductive lead 324 is connected to the first substructure 3112 in the first connection structure 311 on the substrate 200. The first chip circuit 313 is connected to the substrate 200 along a first direction through the first substructure 3111 and the second substructure 3112.

[0048] In some embodiments, the first substructure 3111 can be a pad, and the second substructure 3112 includes copper pillars. Since the first MOS chip is a flip-chip structure, the copper pillars can also be called flip-chip copper pillars. The number of flip-chip copper pillars can be four. One end of the four flip-chip copper pillars is connected to the first source pin, the second source pin, the first gate pin, and the second gate pin of the first MOS chip, respectively, and the other end is connected to the substrate 200.

[0049] In some embodiments, the first substructure 3111 and the second substructure 3112 may also be structures of other shapes or materials that can realize the electrical connection between the first chip circuit 310 and the substrate 200. This application does not limit the embodiments.

[0050] In some embodiments, the second substructure 3112 may also be a structure of other shape or material that can realize the electrical connection between the first chip circuit 310 and the substrate 200, for example, it may be an iron pillar, a composite metal connecting block, etc., which is not limited in the embodiments of this application.

[0051] The first MOS chip 310 can be soldered to the substrate 200 through the first substructure 3111 and the second substructure 3112.

[0052] In some embodiments, the third connection structure 324 can be a pad, and the number of pads can be four, which can respectively correspond to the first source pin, the second source pin, the first gate pin, and the second gate pin of the second MOS chip 320. One end of the conductive lead 330 can be electrically connected to the third connection structure 324 by any method such as soldering or bonding with conductive adhesive.

[0053] Figure 4 A schematic diagram illustrating a chip stacking package structure according to an embodiment of this application is shown, as follows: Figure 4 As shown, the first substrate 312 includes a first metal layer 3121 and a first silicon layer 3122, and the first chip circuit 313, the first metal layer 3121, and the first silicon layer 3122 are stacked along a first direction. The second substrate 322 includes a second metal layer 3221 and a second silicon layer 3222, and the second substrate 322 may include the second metal layer 3221 and the second silicon layer 3222; wherein the second chip circuit 323, the second metal layer 3221, and the second silicon layer 3222 are stacked along the first direction.

[0054] The first metal layer 3121 and the second metal layer 3221 can both be referred to as back gold, which has the function of conduction or heat dissipation. The materials of the first silicon body layer 3122 and the second silicon body layer 3222 can be monocrystalline silicon, polycrystalline silicon, silicon wafers, silicon epitaxial wafers, etc., which are used to prepare semiconductor devices.

[0055] Figure 5 The schematic diagram illustrates a chip stacking package structure according to an embodiment of this application. In some embodiments, the chip stacking package structure 100 further includes an external connection structure 201, such as... Figure 5 As shown, the substrate 200 includes a first surface and a second surface opposite to each other; wherein the first MOS chip 310 is fixed to the first surface of the substrate 200 along a first direction, and the external connection structure 201 is fixed to the second surface of the substrate 200.

[0056] In some embodiments, the external connection structure 201 can be a pad, which is fixed to the second surface of the substrate 200 by welding, wherein the number of pads can be one or more.

[0057] Figure 6 This diagram illustrates a chip stacking package structure after molding according to an embodiment of this application. In some embodiments, the chip stacking package structure further includes a molding compound 400, which is disposed on a first surface of a substrate and used to encapsulate the chip structure 300. The molding compound 400 can be formed from a mixture of resin and silicon dioxide, etc., and the mixture can be in any form, such as cylindrical or powdered. The encapsulated chip stacking structure can be any shape, such as cuboid or cylinder, and is not limited thereto.

[0058] It is understood that in this embodiment of the application, encapsulating the chip structure with molding compound can effectively isolate moisture and improve the mechanical strength of the chip stacked packaging structure.

[0059] In the chip stacking package structure provided in this application embodiment, the first MOS chip (i.e., MOS flip chip) 310 is soldered to the substrate 200 via flip-chip copper pillars, and the second MOS chip (i.e., MOS bonded chip) 320 is fixed to the first MOS chip 310 via a die-casting film. Interconnection with the substrate 200's pads and internal circuitry is achieved through wire bonding and flip-chip copper pillars. This allows for the stacking of two MOS chips while maintaining parallel connectivity, reducing the package size of the chip stacking package structure while ensuring low impedance, thus reducing the area occupied by the chip stacking package structure in electronic devices. Furthermore, encapsulating the chip structure with molding compound effectively isolates moisture and improves the mechanical strength of the chip stacking package structure.

[0060] The following describes the fabrication method of the chip stacked packaging structure mentioned in the embodiments of this application.

[0061] Figure 7 The flowchart illustrating a method for fabricating a chip stacked packaging structure according to an embodiment of this application is shown. Figures 8A-8G The diagram illustrates some of the structural features involved in the preparation process, such as... Figure 7 and Figures 8A-8G As shown, the preparation method includes:

[0062] S101: Process MOS flip wafers, process flip copper pillars, and thin the back gold.

[0063] In some embodiments, a MOS flip wafer may include a silicon body layer, a chip circuit, and a back metal layer of the silicon body layer. After processing the MOS flip wafer, the back metal layer of the MOS flip wafer may be thinned, and then flip copper pillars may be grown on the chip circuit.

[0064] S102: Process MOS bonding wafers and perform back gold thinning.

[0065] In some embodiments, the MOS bonding wafer includes a silicon body layer, a chip circuit, terminals on the chip circuit, and a back metal layer of the silicon body layer. The back metal layer of the MOS bonding wafer can be thinned during fabrication. The terminals on the chip circuit of the MOS bonding wafer can be pads, and the number of terminals on the chip circuit can be four, corresponding to the source pin, substrate pin, drain pin, and gate pin of the second MOS chip 320, respectively.

[0066] It is understood that the order of S101 and S102 is not limited in the embodiments of this application. For example, S101 can be executed first, or S102 can be executed first.

[0067] S103: Divide the MOS flip wafer and MOS bonding wafer to produce a single first MOS chip 310 and a second MOS chip 320.

[0068] It is understood that after fabricating MOS flip wafers and MOS bonding wafers, the MOS flip wafers and MOS bonding wafers can be diced to obtain single chips, such as single MOS flip chips and single bonding chips. The MOS flip chip can refer to the first MOS chip 310 provided in this application, and the bonding chip can refer to the second MOS chip 320 provided in this application. It is understood that a flip chip refers to directly interconnecting the chip face down to a substrate, carrier, or circuit board through connection structures such as bumps and pads on the chip.

[0069] Figure 8A The diagram illustrates the structure of the first MOS chip 310 and the flip-chip copper pillar 3112a formed during fabrication. Figure 8A As shown, the first MOS chip 310 may include a first substrate 312 and a first chip circuit 313. The first substrate 312 includes a first metal layer 3121 and a first silicon layer 3122. The first chip circuit 313, the first metal layer 3121, and the first silicon layer 3122 are stacked along a first direction. A flip-chip copper pillar 3112a is grown on the surface of the first chip circuit 313.

[0070] Figure 8B The diagram illustrates the structure of the fabricated second MOS chip 320 and terminal 324a. (See attached diagram.) Figure 8B As shown, the second MOS chip 320 includes a second substrate 322 and a second chip circuit 323. The second substrate 322 includes a second metal layer 3221 and a second silicon layer 3222. The second chip circuit 323, the second metal layer 3221, and the second silicon layer 3222 are stacked along a first direction. A terminal 324a is grown on the surface of the second chip circuit 323.

[0071] S104: The first MOS chip 310 is soldered onto the substrate 200 by reflow soldering.

[0072] It is understood that the first MOS chip 310 can be fixed on the substrate, and the first MOS chip 310 can be fixed on the substrate 200 by a reflow soldering method. Figure 8C The diagram illustrates the structure of the first MOS chip 310, which is fabricated and fixed on the substrate 200. (See diagram for reference.) Figure 8C As shown, the first MOS chip 310 is soldered to the pad 3111b on the substrate 100 via flip-chip copper pillars 3112a, so as to fix the first MOS chip 310 on the substrate 200.

[0073] S105: Fix the second MOS chip 320 onto the first MOS chip 310 using a conductive adhesive.

[0074] It is understandable that the second MOS chip 310 can be fixed on the first MOS chip by a die 321a formed by a conductive adhesive. Figure 8D The diagram illustrates the structure of the second MOS chip 310, which is formed and fixed on the first MOS chip 310 by a die-mounting mold 321a.

[0075] S106: The second MOS chip 320 and the substrate 200 are connected through conductive leads 330, forming a parallel circuit with the first MOS chip 310.

[0076] In some embodiments, the pads 324a of the second MOS chip 320 and the pads 3111a on the substrate 200 can be connected by conductive leads 330, thereby achieving wire bonding between the pads 324a of the second MOS chip 320 and the pads 3111a on the substrate 200, so that the second MOS chip 320 and the first MOS chip 310 form a parallel circuit. Figure 8E The diagram illustrates the fabricated chip structure 300 fixed on the substrate 200. It can be understood that the conductive leads 330 can be metal bonding wires.

[0077] S107: Chip structure 300 is encapsulated with molding compound.

[0078] In some embodiments, after the chip structure is fabricated, the chip structure 300 can be encapsulated using a molding die based on the molding compound to form a molded structure 400, which can effectively isolate moisture and improve the mechanical strength of the chip stacked packaging structure. Figure 8F The diagram illustrates the fabricated chip structure 300 fixed on the substrate 200. The molding die can be a mold used for molding products, and may include an upper mold and a lower mold.

[0079] S108: Cut the molded substrate 200 to produce a stacked structure of single MOS chips.

[0080] In some embodiments, after the chip structure is encapsulated, the substrate 200 can be cut to form a single MOS chip stack structure. That is, to form... Figure 8G The chip stacking structure shown.

[0081] The actual effects of the chip stacking packaging structure are described below based on the embodiments of this application.

[0082] Figure 9A A diagram showing the external dimensions of a single MOS chip, such as... Figure 9AAs shown, the dimensions of a single MOS chip are 2.98mm in length and 1.49mm in width. Two MOS chips are mounted in parallel on a circuit board (PCB). Due to the filler material between the two MOS chips, after mounting, the two MOS chips mounted in parallel on the circuit board (PCB) are 3.1mm in length and 2.98mm in width, occupying an area of ​​3.1mm*2.98mm on the circuit board.

[0083] Figure 9B This is a dimensional diagram of the two MOS chip stacked package structures provided in the embodiments of this application, such as... Figure 9B As shown, the dimensions of the two stacked MOS chips are approximately 3.2mm in length and 2.42mm in width, occupying a PCB area of ​​approximately 2.42mm x 3.28mm. Compared to the external dimensions of a conventional single MOS chip, the PCB area is reduced by approximately 20%.

[0084] Figure 10A The circuit diagram for a single MOS chip is shown below. Figure 10A As shown, S1 is the first source (or input source) of the MOS chip, S2 is the second source (or output source) of the MOS chip, G1 is the first gate (or input gate) of the MOS chip, and G2 is the second gate (or output gate) of the MOS chip. Figure 10A The impedance of a single chip is 2.2 milliohms.

[0085] Figure 10B The circuit diagram of the chip stacked package structure formed by stacking two chips provided in the embodiments of this application is as follows: Figure 10B As shown, the first sources S1 of the first MOS chip and the second MOS chip are connected in parallel to form a common first source S1, the second sources S2 of the first MOS chip and the second MOS chip are connected in parallel to form a common second source S2, the first gates G1 of the first MOS chip and the second MOS chip are connected in parallel to form a common first gate G1, and the second gates G1 of the first MOS chip and the second MOS chip are connected in parallel to form a common second gate G2. Figure 10B The impedance of the illustrated chip stacked package structure is approximately 1.44 milliohms.

[0086] from Figure 10A and Figure 10B The comparison shows that the chip stacking packaging structure provided in this application embodiment can effectively reduce impedance.

[0087] In summary, in the chip stacking package structure provided in this application embodiment, the first MOS chip (i.e., MOS flip chip) 310 is soldered to the substrate 200 via flip-chip copper pillars, and the second MOS chip (i.e., MOS bonded chip) 320 is fixed to the first MOS chip 310 via a die-casting film. Interconnection with the substrate 200's pads and internal circuitry is achieved through wire bonding and flip-chip copper pillars. This allows for the stacking of two MOS chips while maintaining parallel connectivity, reducing the package size of the chip stacking package structure while ensuring low impedance, thus reducing the area occupied by the chip stacking package structure in electronic devices. Furthermore, encapsulating the chip structure with molding compound effectively isolates moisture and improves the mechanical strength of the chip stacking package structure. In addition, it effectively reduces the impedance of the MOS chip in electronic devices.

[0088] This application provides an electronic device, including the chip stacking package structure mentioned in this application.

[0089] It should be noted that in the examples and description of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0090] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the scope of this application.

Claims

1. A chip stack package structure, characterized by, The chip structure comprises a substrate and a chip structure arranged on the substrate, the chip structure comprises a first MOS chip, a second MOS chip and a conductive lead; The substrate, the first MOS chip and the second MOS chip are sequentially stacked along a first direction; The substrate, the first MOS chip and the second MOS chip are sequentially electrically connected; One end of the conductive lead is connected to the second MOS chip, and the other end is connected to the substrate; The first MOS chip comprises a first base body and a first chip circuit arranged on the first base body; The second MOS chip comprises a second base body and a second chip circuit arranged on the second base body; The chip structure comprises a first connecting structure, the first connecting structure comprises a first substructure arranged on the surface of the substrate and a second substructure arranged on the surface of the first chip circuit, the first chip circuit is connected to the substrate along the first direction through the first substructure and the second substructure, the first base body is connected to the second base body along the first direction, and the second chip circuit is connected to one end of the conductive lead; The second substructure is connected to a first source pin of the first MOS chip, a second source pin of the first MOS chip, a first gate pin of the first MOS chip and a second gate pin of the first MOS chip; The number of the conductive lead is four, one end of the four conductive leads is respectively connected to a first source pin of the second MOS chip, a second source pin of the second MOS chip, a first gate pin of the second MOS chip and a second gate pin of the second MOS chip, and the other end of the four conductive leads is connected to the first substructure.

2. The chip stack package structure of claim 1, wherein, The chip structure further comprises a second connecting structure; The first base body and the second base body are connected along the first direction through the second connecting structure.

3. The chip stack package structure of claim 2, wherein, Wherein, The chip structure further comprises a third connecting structure arranged on the surface of the second MOS chip, and the third connecting structure is electrically connected to the second chip circuit One end of the conductive lead is connected to the third connecting structure, and the third connecting structure corresponds to a first source pin of the second MOS chip, a second source pin of the second MOS chip, a first gate pin of the second MOS chip and a second gate pin of the second MOS chip.

4. The chip stack package structure according to claim 2 or 3, wherein, The first chip circuit is welded to the substrate along the first direction through the first connecting structure.

5. The chip stack package structure according to claim 2 or 3, wherein, The second connecting structure is a conductive adhesive, and the first base body and the second base body are bonded along the first direction through the conductive adhesive.

6. The chip stack package structure of claim 3, wherein, The first substructure is a pad, the second substructure is a copper column, and the third connecting structure is a pad.

7. The chip stack package structure of claim 2, wherein, The first base body comprises a first metal layer and a first silicon body layer, and the second base body comprises a second metal layer and a second silicon body layer; The first chip circuit, the first silicon body layer and the first metal layer are arranged in a stacked manner along the first direction, and the second metal layer, the second silicon body layer and the second chip circuit are arranged in a stacked manner along the first direction.

8. The chip stack package structure of claim 1, wherein, Further comprising an external connection structure, the substrate comprising opposite first and second surfaces; the first MOS chip is fixed to the first surface of the substrate along the first direction; the external connection structure is fixed to the second surface of the substrate.

9. The chip stack package structure of claim 8, wherein, Further comprising a plastic package structure, the plastic package structure being disposed on the first surface of the substrate and used for covering the chip structure.

10. An electronic device, comprising: The chip stack package structure according to any one of claims 1-9.

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