Voltage sampling circuit applied to EPS and capable of reducing sleep current

Abstract

The utility model relates to the technical field of power electronics, in particular to a voltage sampling circuit applied to an EPS (Electric Power Storage) and capable of reducing sleep current, which comprises a power management module, a microcontroller, an NMOS (N-channel Metal Oxide Semiconductor) transistor, a resistor and a capacitor, the other end of the resistor I is divided into two paths which are respectively connected with one end of a divider resistor II and one end of a current-limiting resistor, the other end of the divider resistor II is connected with a drain electrode of an NMOS (N-channel Metal Oxide Semiconductor) transistor, and a grid electrode of the NMOS transistor is connected with a driving resistor in series and then is connected with an I / O (Input / Output) pin of the microcontroller. Compared with the prior art, by turning off the NMOS transistor connected in series in the voltage sampling circuit, the whole voltage sampling circuit is turned off during dormancy, so that the newly added consumption after the CAN chip is added can be made up, the increase influence caused by the rise of the battery voltage can be avoided, and the customer requirement of smaller dormancy current of the whole EPS ECU can be met.

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