Electronic package
By using light guides in wafer-level design to reflect light signals and transmit them to the side of the photonic chip, the contradiction between signal energy loss and production capacity is resolved, enabling efficient semiconductor packaging production.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2026-03-20
AI Technical Summary
There is a trade-off between increasing production capacity and reducing signal energy loss in existing semiconductor packaging, especially when using CPO technology, where signal energy loss is difficult to avoid, and single-chip process leads to reduced production capacity.
The design adopts a wafer-level specification, and the electronic connector is equipped with a first light guide. The fiber array elements are reflected and transmitted to the side of the photonic chip through the first light guide. Combined with the wafer-level substrate specification for single-chip dicing, the optical signal can be directly entered from the side of the photonic chip, avoiding transmission inside the grating structure.
It achieves a balance between high throughput and low signal energy loss, and reduces production costs and improves production efficiency by using existing semiconductor packaging processes.
Smart Images
Figure CN224020037U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor packaging technology, and more particularly to an electronic package having a photonic chip. Background Technology
[0002] Currently, optical communication is used in data centers or network operators to configure 100Gbps communication equipment. However, this speed is gradually becoming insufficient. Therefore, the industry has developed co-packaged optical components (CPO) to solve the problems of bandwidth density limitations and communication latency encountered in the transmission of large amounts of data on the network by more tightly combining the key elements required for communication (i.e., optical and electronic components).
[0003] FIG. 1A This is a cross-sectional schematic diagram of an existing semiconductor package 1a. (See diagram below.) FIG. 1A As shown, the existing semiconductor package 1a adopts CPO technology, which includes: a substrate 10, an electronic chip 11 and a photonic IC 12 disposed on the substrate 10 and electrically connected to the substrate 10, a packaging layer 13 covering the photonic chip 12 and the electronic chip 11, an electronic connector 14a disposed above the top surface 12a of the photonic chip 12 and communicatively connected to the photonic chip 12, and a fiber array unit (FAU) 15 communicatively connected to the electronic connector 14a, so that optical signals are transmitted to the electronic connector 14a via the ribbon cable 150 of the fiber array unit 15, and then transferred to the photonic chip 12.
[0004] When manufacturing the aforementioned semiconductor package 1a, a wafer-level specification can be used, placing the electronic connector 14a above the top surface 12a of the photonic chip 12 to achieve higher throughput. However, the optical signal of the fiber array element 15 needs to pass through the internal grating structure above the top surface 12a of the photonic chip 12, which results in signal energy loss.
[0005] Therefore, as FIG. 1B The semiconductor package 1b shown in the industry also has an electronic connector 14b disposed on the side 12c of the photonic chip 12, so that the optical signal of the fiber array element 15 can directly enter the photonic chip 12 without passing through the internal grating structure above the top surface 12a of the photonic chip 12, thus avoiding the problem of signal energy loss.
[0006] However, when manufacturing the aforementioned semiconductor package 1b, a unit form specification is required to attach the electronic connector 14b from the side 12c of the photonic chip 12. Therefore, compared to a wafer-level process, the production capacity of the semiconductor package 1b is lower.
[0007] Therefore, how to overcome the above problems of the prior art, such as capacity and signal energy loss, has become a difficult problem to be solved in the industry. Practical new type content
[0008] In view of the above shortcomings of the prior art, the present application provides an electronic package, comprising: an electronic element; an electronic connector with a first light guide provided on the electronic element; a photonic chip provided on the electronic element, such that the first light guide is located on the side of the photonic chip; and a transmission component connected to the electronic connector.
[0009] The present application also provides a method for manufacturing an electronic package, comprising: providing a wafer-level substrate containing a plurality of electronic elements; providing an electronic connector with a first light guide on each of the electronic elements; providing a photonic chip on each of the electronic elements, and allowing the first light guide to be located on the side of the photonic chip, to form a plurality of packaging modules; singulating the substrate to separate each of the packaging modules; and connecting a transmission component to the electronic connector.
[0010] In the foregoing electronic package and its manufacturing method, the electronic element is an electronic integrated circuit chip.
[0011] In the foregoing electronic package and its manufacturing method, the first light guide is a mirror.
[0012] In the foregoing electronic package and its manufacturing method, the transmission component is located on the side of the photonic chip.
[0013] In the foregoing electronic package and its manufacturing method, the transmission component is an optical fiber array element.
[0014] In the foregoing electronic package and its manufacturing method, the transmission component has a set of wires. For example, the wires are optical fibers.
[0015] In the foregoing electronic package and its manufacturing method, the transmission component has a second light guide configured corresponding to the first light guide. For example, the second light guide is a mirror.
[0016] In the foregoing electronic package and its manufacturing method, it further includes a bearing structure for accommodating the photonic chip.
[0017] As can be seen from the above, the electronic package of the present application mainly has the first light guide of the electronic connector, so that the optical signal of the transmission component is reflected and transmitted to the side of the photonic chip through the first light guide, to meet the requirement of low energy loss, and the electronic connector and the photonic chip are accommodated by the wafer-level substrate, to improve the production capacity. Therefore, compared with the prior art, the electronic package of the present application can meet the requirements of high production capacity and low signal energy loss at the same time, without the shortcomings of the prior art. BRIEF DESCRIPTION OF DRAWINGS
[0018] FIG. 1A and FIG. 1B are cross-sectional views of different prior semiconductor packages.
[0019] FIGS. 2A-2E is a cross-sectional view of a method of making an electronic package of the present application.
[0020] FIG. 3 is a cross-sectional view of another embodiment of the present application. FIG. 2E
[0021] REFERENCE NUMERALS
[0022] 1a, 1b semiconductor package
[0023] 10 substrate
[0024] 11 electronic chip
[0025] 12, 22 photonic chip
[0026] 12a top surface
[0027] 12c, 22c side surface
[0028] 13 encapsulation layer
[0029] 14a, 14b electronic connector
[0030] 15 fiber array element
[0031] 150, 250 wire array
[0032] 2, 3 electronic package
[0033] 2a package module
[0034] 20 wiring structure
[0035] 200 insulating layer
[0036] 201 wiring layer
[0037] 21 electronic element
[0038] 21a active surface
[0039] 21b inactive surface
[0040] 210 electrode pad
[0041] 211 electrically conductive pad
[0042] 23 electrically conductive bump
[0043] 24 electronic connector
[0044] 240 First light guide
[0045] 25 Transmission Components
[0046] 251 Second light guide
[0047] 27 Conductive elements
[0048] 30 Load-bearing structure
[0049] 8. Substrate
[0050] F Transmission Path
[0051] L is the cutting path. Detailed Implementation
[0052] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0053] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0054] FIGS. 2A-2E This is a cross-sectional schematic diagram of the manufacturing method of the electronic package 2 of this application.
[0055] like FIG. 2A As shown, a wafer-level substrate 8 is provided with an array of multiple electronic components 21. In this embodiment, the electronic component 21 is a semiconductor chip, such as an electronic integrated circuit (EIC) chip, which has an opposing active surface 21a and a non-active surface 21b, and the active surface 21a has multiple electrode pads 210 and electrical connection pads 211.
[0056] like FIG. 2B As shown, an electronic connector 24 with a first light guide 240 is provided on the working surface 21a of each electronic component 21.
[0057] In this embodiment, the electronic connector 24 is electrically connected to the electrical connection pad 211, and the first light guide 240 is a mirror.
[0058] As shown in FIG. 1, the electronic component 21 is provided with a plurality of electrode pads 210 on a surface 21a thereof, and a plurality of photonic chips 22 are combined to the electrode pads 210 of the electronic component 21 to form a plurality of package modules 2a. FIG. 2C As shown in FIG. 1, the electronic component 21 is provided with a plurality of electrode pads 210 on a surface 21a thereof, and a plurality of photonic chips 22 are combined to the electrode pads 210 of the electronic component 21 to form a plurality of package modules 2a.
[0059] In this embodiment, the electronic connector 24 is located at the side surface 22c of the photonic chip 22.
[0060] Further, the photonic chip 22 can be combined to the electrode pads 210 of the electronic component 21 through a plurality of conductive bumps 23, so that the photonic chip 22 is electrically connected to the electronic component 21. For example, the conductive bumps 23 are copper pillars, solder bumps or other metal materials, and are not particularly limited.
[0061] In addition, a circuit structure 20 can be formed on the photonic chip 22, and a plurality of conductive elements 27 such as solder balls can be combined thereto.
[0062] In addition, the circuit structure 20 includes an insulating layer 200 and a circuit layer 201 combined to the insulating layer 200 and electrically connected to the photonic chip 22, such as a fan-out type redistribution layer (RDL). For example, the material forming the circuit layer 201 is copper, and the material forming the insulating layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), Prepreg (PP), or a solder resist material such as green paint, ink, etc.
[0063] As shown in FIG. 1, the electronic component 21 is provided with a plurality of electrode pads 210 on a surface 21a thereof, and a plurality of photonic chips 22 are combined to the electrode pads 210 of the electronic component 21 to form a plurality of package modules 2a. FIG. 2D As shown in FIG. 1, the electronic component 21 is provided with a plurality of electrode pads 210 on a surface 21a thereof, and a plurality of photonic chips 22 are combined to the electrode pads 210 of the electronic component 21 to form a plurality of package modules 2a. FIG. 2C As shown in FIG. 1, the electronic component 21 is provided with a plurality of electrode pads 210 on a surface 21a thereof, and a plurality of photonic chips 22 are combined to the electrode pads 210 of the electronic component 21 to form a plurality of package modules 2a.
[0064] As shown in FIG. 1, the electronic component 21 is provided with a plurality of electrode pads 210 on a surface 21a thereof, and a plurality of photonic chips 22 are combined to the electrode pads 210 of the electronic component 21 to form a plurality of package modules 2a. FIG. 2E As shown in FIG. 1, the electronic component 21 is provided with a plurality of electrode pads 210 on a surface 21a thereof, and a plurality of photonic chips 22 are combined to the electrode pads 210 of the electronic component 21 to form a plurality of package modules 2a.
[0065] In this embodiment, the transmission component 25 is a fiber array unit (FAU) having a set of wires 250 and a second light guide 251 corresponding to the first light guide 240. For example, the second light guide 251 can be a mirror that is communicatively connected to the wires 250 and the first light guide 240, and the wires 250 are optical fibers such that an optical signal is transmitted through the wires 250 to the second light guide 251, and then reflected to the first light guide 240 to be reflected to the side surface 22c of the photonic chip 22 (e.g., the transmission path F), so that the optical signal enters the photonic chip 22 from the side surface 22c of the photonic chip 22.
[0066] In other embodiments, as shown in the electronic package 3, FIG. 3 FIG. 3 the photonic chip 22 can be mounted on a carrier structure 30 through the conductive element 27.
[0067] The carrier structure 30 is a carrier plate for mounting the chip, such as a circuit structure with a core layer, a circuit structure in a coreless form, a through-silicon interposer (TSI) with a through-silicon via (TSV), a lead frame, a wafer, or other plates with metal routing, without particular limitation.
[0068] Therefore, the electronic package 2, 3 of the present application mainly has the first light guide 240 through the electronic connector 24 to generate edge coupling at the side surface 22c of the photonic chip 22, so that the optical signal is reflected to the side surface 22c of the photonic chip 22 through the first light guide 240 to directly enter the photonic chip 22 without passing through the grating structure inside the photonic chip 22, thereby reducing energy loss. Therefore, the electronic package 2, 3 of the present application can effectively avoid the problem of signal energy loss. On the other hand, the aforementioned manufacturing method uses the specifications of the wafer-level substrate 8, so that multiple electronic elements 21 can be mounted on the electronic connector 24 and the photonic chip 22 in a full-page manner, and then a singulation process is performed. Therefore, the aforementioned manufacturing method can improve productivity. Therefore, the electronic package 2, 3 of the present application can meet the requirements of high productivity and low signal energy loss at the same time.
[0069] Furthermore, the electronic package 2, 3 of the present application can be manufactured by using existing semiconductor packaging processes without the need to develop special processes or purchase special equipment, thereby greatly reducing the production cost of the product and meeting the requirement of high feasibility.
[0070] The application also provides an electronic package 2, 3, comprising an electronic element 21, an electronic connector 24 with a first light guide 240, a photonic chip 22, and a transmission assembly 25.
[0071] The electronic connector 24 is arranged on the electronic element 21.
[0072] The photonic chip 22 is arranged on the electronic element 21, so that the first light guide 240 is located on the side surface 22c of the photonic chip 22.
[0073] The transmission assembly 25 is connected to the electronic connector 24.
[0074] In an embodiment, the electronic package 3 further comprises a supporting structure 30 arranged with the photonic chip 22.
[0075] In an embodiment, the electronic element 21 is an electronic integrated circuit chip.
[0076] In an embodiment, the first light guide 240 is a mirror.
[0077] In an embodiment, the transmission assembly 25 is located on the side surface 22c of the photonic chip 22.
[0078] In an embodiment, the transmission assembly 25 is an optical fiber array element.
[0079] In an embodiment, the transmission assembly 25 has a set of wires 250. For example, the wires 250 are optical fibers.
[0080] In an embodiment, the transmission assembly 25 has a second light guide 251 arranged corresponding to the first light guide 240. For example, the second light guide 251 is a mirror.
[0081] In summary, the electronic package of the application, through the design of the electronic connector with the first light guide, enables the optical signal of the transmission assembly to be reflected and transmitted to the side surface of the photonic chip through the first light guide, so as to meet the requirement of low energy loss. Meanwhile, through the specification of the wafer-level substrate, the electronic connector and the photonic chip are arranged on the electronic element, so as to improve the production capacity. Therefore, the electronic package of the application can meet the requirements of high production capacity and low signal energy loss at the same time.
[0082] The above embodiments are used to exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the application. Therefore, the protection scope of the application should be subject to the claims.
Claims
1. An electronic package, characterized in that, include: Electronic components; An electronic connector is disposed on the electronic component and has a first light guide; A photonic chip is disposed on the electronic component, such that the first light guide is located on the side of the photonic chip. as well as The transmission component connects to the electronic connector.
2. The electronic package as described in claim 1, characterized in that... The electronic package also includes a carrier structure for mounting the photonic chip.
3. The electronic package as described in claim 1 or 2, characterized in that, This electronic component is an electronic integrated circuit chip.
4. The electronic package as described in claim 1 or 2, characterized in that, The first light guide is a reflector.
5. The electronic package as described in claim 1 or 2, characterized in that, The transmission component is located on the side of the photonic chip.
6. The electronic package as described in claim 1 or 2, characterized in that, The transmission component is a fiber optic array element.
7. The electronic package as described in claim 1 or 2, characterized in that, The transmission component has a set of ribbon cables.
8. The electronic package as described in claim 7, characterized in that, The cable is made of optical fiber.
9. The electronic package as described in claim 1 or 2, characterized in that, The transmission component has a second light guide that corresponds to the first light guide.
10. The electronic package as claimed in claim 9, characterized in that, The second light guide is a reflector.