Radio frequency front end PA chip power supply time sequence control circuit

Abstract

The utility model relates to the technical field of power supply time sequence control, and specifically relates to a radio frequency front end PA chip power supply time sequence control circuit. The power supply time sequence control circuit comprises two groups of buck circuits, wherein each group of buck circuits adopts Power-I C of a JW5393 model; the input voltage of the Power-I C is 12V, the output voltage of the Power-I C is 5V, and the working frequency of the Power-I C is 600KHz. According to the utility model, the EN pin of the DC-DC Power-I C is controlled, and the output of VOUT-5V voltage is controlled by using a high-level enable signal, so that the sequential control of the power supply of the radio frequency front-end PA chip is realized. Specifically, in the power-on starting process of the system, the Power-I C is in a closed state, after software initialization is completed, an enable signal is pulled up through a GPIO25 pin, the Power-I C begins to output 5V voltage, and a radio frequency front end PA chip begins to work.

Description

TECHNICAL FIELD

[0001] The utility model relates to power time sequence control technical field, concretely is a kind of radio frequency front-end PA chip power time sequence control circuit. BACKGROUND

[0002] The WiFi6-AX3000 home user gateway product of HiSilicon scheme has up to 15W in hardware whole machine power consumption, and four 2.4G-WiFi and 5G-WiFi front-end radio frequency PA chips, with maximum total power consumption of 7.4W, accounting for half of the total power consumption of the product. In the power-on process of traditional power supply design, the radio frequency front-end PA chip will start working immediately, resulting in a large inrush current at the power-on moment. This inrush current not only affects the reliability and stability of the product, but also may cause damage to the power adapter and other circuit components. In addition, the large inrush current also increases the power safety risk of the terminal product and reduces the power efficiency. Therefore, how to effectively control the inrush current at the power-on moment and improve the power efficiency of the power-on transient state has become a technical problem to be solved. SUMMARY

[0003] The utility model provides a kind of radio frequency front-end PA chip power time sequence control circuit to solve the technical problem of how to effectively control the inrush current of power-on moment for the technical problems existing in prior art.

[0004] The technical solution of the utility model to solve the above technical problem is as follows:

[0005] A radio frequency front-end PA chip power time sequence control circuit is provided, and the power time sequence control circuit comprises:

[0006] Two groups of buck circuits, each of the buck circuits uses a Power-IC of JW5393 model;

[0007] The input voltage of the Power-IC is 12V, the output voltage is 5V, and the working frequency is 600KHz;

[0008] The enable end EN of the Power-IC is connected to a GPIO25 pin of the Wi-Fi6-AX3000 chip through a P4R10 resistor, the standard level of the GPIO25 pin is 1.8V, and the default state is low level;

[0009] The output end VOUT of the Power-IC is connected to the power input end of the radio frequency front-end PA chip;

[0010] In the power-on starting process, the Power-IC is in the off state until the software initialization is completed, the enable signal is pulled high through the GPIO25 pin, the Power-IC starts to output 5V voltage, and the radio frequency front-end PA chip starts to work.

[0011] Further, the two groups of buck circuits are used for power supply of 2.4G and 5G radio frequency front-end PA chips respectively, and the enable ends EN of the two groups of buck circuits are connected to the GPIO25 pin of the Wi-Fi6-AX3000 chip through the same P4R10 resistor.

[0012] Further, the input end VIN of the Power-IC is connected to a 12V DC power supply, and the output end VOUT is connected to the power input end of the radio frequency front-end PA chip through filter capacitors C1 and C2, and the filter capacitors C1 and C2 are connected in parallel to reduce the ripple of the output voltage.

[0013] Further, the resistance value of the P4R10 resistor is 10kΩ, which is used for limiting the current of the GPIO25 pin and preventing overcurrent damage to the Wi-Fi6-AX3000 chip.

[0014] Further, the enable end EN of the Power-IC keeps low level at the moment of system power-on until the software initialization of the Wi-Fi6-AX3000 chip is completed, a high level signal is output through the GPIO25 pin to enable the Power-IC to control the power sequence of the radio frequency front-end PA chip.

[0015] Further, the output voltage VOUT of the Power-IC is connected to the power input end of the radio frequency front-end PA chip through a diode D1, and the diode D1 is used for preventing reverse current from damaging the Power-IC.

[0016] Further, the power input end of the radio frequency front-end PA chip is also connected with a protection resistor R1, and the resistance value of the protection resistor R1 is 1Ω, which is used for limiting the starting current of the radio frequency front-end PA chip and reducing the impact current.

[0017] The beneficial effects of the utility model are:

[0018] The utility model discloses a control DC-DC Power-IC's EN pin, utilize high level enable signal to control the output of VOUT-5V voltage, thereby realize the timing control of radio frequency front end PA chip power supply. Specifically, in the system power-on starting process, Power-IC is in the closed state, until software initialization is completed, through the GPIO25 pin pull high enable signal, only then Power-IC starts output 5V voltage, makes radio frequency front end PA chip start working. This design effectively avoids the PA chip in the software initialization process to carry out the load, thereby significantly reduce the impact current of power transient. After testing, when not using the power control timing of the patent, the impact current reaches 18.96A, and after adopting the patent design, the impact current reduces to 5.66A. This not only improves the power efficiency of power transient, enhances the reliability and stability of product, also greatly improves the power safety and electric energy efficiency of terminal product. At the same time, due to the significant reduction of impact current, the power adapter of more optimal specification can be selected, further reduce the cost and improve the power efficiency, meet the green concept of national low carbon environmental protection. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 Circuit for the utility model Figure One ;

[0020] Figure 2 Circuit for the utility model Figure Two . DETAILED DESCRIPTION

[0021] In order to make the purpose, technical scheme and advantage of the utility model more clear and obvious, the following combines the figure and example, and further detailedly explains the utility model. The example of the example is shown in the drawing, wherein the same or similar reference numerals represent the same or similar elements or elements with the same or similar function throughout. The example described below by referring to the drawing is exemplary, and is only used to explain the utility model, and cannot be understood as the limitation of the utility model. In addition, it should be understood that the specific examples described herein are only used to explain the utility model, and are not used to limit the utility model.

[0022] In the description of the utility model, it is understood that the orientation or position relationship indicated by the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom" and the like is the orientation or position relationship shown in the drawing, and is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as the limitation of the utility model.

[0023] In addition, the terms "first", "second", etc. are used only for descriptive purposes and do not connote or imply relative importance or an ordering between or among the indicated technical features. Thus, a feature defined with "first", "second", etc. can include one or more of the features implicitly or explicitly. In the description of the present application, the meaning of "a plurality of" is two or more, unless explicitly specified and limited otherwise.

[0024] In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through intermediate medium, or the communication between two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0025] In the present application, unless explicitly specified and limited otherwise, the "upper" or "lower" of the first feature to the second feature can include that the first and second features are in direct contact, or the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the "upper", "above" and "on" of the first feature to the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The "below", "under" and "under" of the first feature to the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0026] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0027] The present application provides the following preferred embodiments:

[0028] In order to solve the problem of excessive inrush current of WiFi6-AX3000 home user gateway product at power-on moment, the embodiment further optimizes the design of the power timing control circuit of the radio frequency front-end PA chip, as shown in Figure 1 and Figure 2 Specifically, by controlling the enable end EN of the DC-DC Power-IC, the output of the VOUT-5V voltage is controlled by using a high-level enable signal, thereby realizing the timing control of the power supply of the radio frequency front-end PA chip. Embodiment

[0029] In this embodiment, two groups of buck circuits of the same type are used, and each group of buck circuits uses a Power-IC of JW5393 model. The input voltage VIN of JW5393 is 12V, the output voltage VOUT is 5V, and the working frequency is 600KHz. The enable end EN of JW5393 is connected to a GPIO25 pin in Wi-Fi6-AX30 through a P4R10 resistor. The standard level of this GPIO25 pin is 1.8V, and the default state is low level. The output end VOUT of JW5393 is connected to the power input end of the radio frequency front-end PA chip.

[0030] Further, when the system is powered on, the enable end EN of JW5393 is in a low level state, so JW5393 does not work, and its output end VOUT is 0V, and the radio frequency front-end PA chip cannot obtain power and is in a closed state. It should be understood that this design avoids the PA chip from starting to work during the system initialization process, thereby effectively reducing the inrush current at power-on moment.

[0031] After the software initialization is completed, the system outputs a high-level signal through the GPIO25 pin to enable JW5393. At this time, JW5393 starts to work, and its output end VOUT outputs a 5V voltage, so that the radio frequency front-end PA chip starts to work normally. It can be understood that this timing control mechanism ensures that the PA chip starts to work only after the system is completely prepared, thereby significantly reducing the inrush current at power-on moment.

[0032] In addition, in order to further improve the stability and reliability of the circuit, the output end VOUT of JW5393 is also connected to the power input end of the radio frequency front-end PA chip through filter capacitors C1 and C2. The filter capacitors C1 and C2 are connected in parallel to reduce the ripple of the output voltage and ensure that the PA chip obtains stable power supply. Embodiment

[0033] To further optimize the performance of the circuit, in this embodiment, the resistance value of P4R10 is selected as 10kΩ. It should be understood that the main role of P4R10 is to limit the current of GPIO25 pin to prevent overcurrent damage to Wi-Fi6-AX3000 chip. At the same time, P4R10 also plays a certain buffering role to ensure smooth transmission of the enable signal.

[0034] Further, the input end VIN of JW5393 is connected to a 12V DC power supply. At the moment of system power-on, since the enable end EN of JW5393 remains low, JW5393 will not work immediately, thereby avoiding the generation of large current. After the system completes initialization, a high-level signal is output through the GPIO25 pin to enable JW5393, so that it outputs a 5V voltage to control the power supply timing of the radio frequency front-end PA chip.

[0035] In order to further protect the circuit, the output end VOUT of JW5393 is also connected to the power input end of the radio frequency front-end PA chip through a diode D1. The main role of diode D1 is to prevent reverse current from damaging JW5393. Embodiment

[0036] To further enhance the protection function of the circuit, in this embodiment, a protection resistor R1 is also connected to the power input end of the radio frequency front-end PA chip. The resistance value of protection resistor R1 is selected as 1Ω, and the main role is to limit the starting current of the radio frequency front-end PA chip to further reduce the impact current. It should be understood that this design not only improves the stability of the circuit, but also prolongs the service life of the circuit.

[0037] Further, the output voltage VOUT of JW5393 is connected to the power input end of the radio frequency front-end PA chip through filter capacitors C1 and C2. Filter capacitors C1 and C2 are connected in parallel to reduce the ripple of the output voltage and ensure that the PA chip obtains stable power supply. It can be understood that this design further improves the reliability of the circuit.

[0038] In addition, in order to further optimize the performance of the circuit, other possible additional features are also considered in this embodiment. For example, a fuse F1 can be added between the input end VIN of JW5393 and the 12V DC power supply to prevent overcurrent damage to the circuit. The rated current of fuse F1 can be selected according to actual needs, and a value slightly larger than the normal working current is usually selected to ensure the safety of the circuit. Embodiment

[0039] To further improve the flexibility and scalability of the circuit, in this embodiment, the enable end EN of the JW5393 can also be connected to multiple GPIO pins through a logic gate circuit. This design allows the system to control the working state of the JW5393 through different combinations of GPIO pins, enabling more complex control.

[0040] In addition, to further optimize the performance of the circuit, other possible additional features are also considered in this embodiment. For example, a voltage detection circuit can be added between the output end VOUT of the JW5393 and the power input end of the RF front-end PA chip. The voltage detection circuit can monitor the voltage value of VOUT in real time and feed back the detection results to the system. When the voltage value of VOUT is abnormal, the system can take timely measures to ensure the normal operation of the circuit. Embodiment

[0041] To further improve the efficiency and reliability of the circuit, in this embodiment, the output end VOUT of the JW5393 is also connected to the power input end of the RF front-end PA chip through a voltage stabilizing diode Z1. The main function of the voltage stabilizing diode Z1 is to stabilize the output voltage and prevent voltage fluctuations from affecting the PA chip. It should be understood that this design further improves the stability and reliability of the circuit.

[0042] Further, to improve the heat dissipation performance of the circuit, a heat sink can be installed on the shell of the JW5393. The main function of the heat sink is to quickly dissipate the heat generated by the JW5393, preventing overheating damage to the circuit. It can be understood that this design further improves the heat dissipation performance of the circuit, prolonging the service life of the circuit.

[0043] In addition, to further optimize the performance of the circuit, other possible additional features are also considered in this embodiment. For example, an inductor L1 can be added between the input end VIN of the JW5393 and the 12V DC power supply. The main function of the inductor L1 is to filter out high-frequency noise in the input power supply, ensuring the stability of the input power supply. Embodiment

[0044] To further improve the reliability and stability of the circuit, in this embodiment, the enable end EN of the JW5393 is also connected to the GPIO25 pin through an optoelectronic coupler. The main function of the optoelectronic coupler is to isolate electrical signals and prevent external interference from affecting the circuit. It should be understood that this design further improves the anti-interference ability of the circuit.

[0045] Further, to improve the anti-static ability of the circuit, a TVS diode can be added between the input terminal VIN of JW5393 and the 12V DC power supply. The main function of the TVS diode is to absorb the transient high voltage generated by static discharge, preventing static damage to the circuit. It can be understood that this design further improves the anti-static ability of the circuit, enhancing the reliability of the system.

[0046] In addition, to further optimize the performance of the circuit, other possible additional features are also considered in this embodiment. For example, a current detection circuit can be added between the output terminal VOUT of JW5393 and the power input terminal of the RF front-end PA chip. The current detection circuit can monitor the current value of VOUT in real time and feed back the detection result to the system. When the current value of VOUT is abnormal, the system can take timely measures to ensure the normal operation of the circuit. It can be understood that this design further improves the reliability and safety of the circuit. Embodiment

[0047] To further improve the reliability and stability of the circuit, in this embodiment, the output terminal VOUT of JW5393 is also connected to the power input terminal of the RF front-end PA chip through a switch tube Q1. The main function of the switch tube Q1 is to cut off the output of VOUT when necessary, preventing excessive current in abnormal conditions. It should be understood that this design further improves the safety and reliability of the circuit.

[0048] Further, to improve the anti-electromagnetic interference ability of the circuit, a common mode choke can be added between the input terminal VIN of JW5393 and the 12V DC power supply. The main function of the common mode choke is to suppress common mode noise and prevent electromagnetic interference from affecting the circuit. It can be understood that this design further improves the anti-electromagnetic interference ability of the circuit, enhancing the reliability of the system.

[0049] In addition, to further optimize the performance of the circuit, other possible additional features are also considered in this embodiment. For example, a temperature sensor can be added between the output terminal VOUT of JW5393 and the power input terminal of the RF front-end PA chip. The temperature sensor can monitor the temperature of the circuit in real time and feed back the detection result to the system. When the circuit temperature is too high, the system can take timely measures to ensure the normal operation of the circuit.

[0050] The embodiment has the benefits that, by the above design, the inrush current of the WiFi6-AX3000 home user gateway product at the power-on moment is effectively controlled, the power supply efficiency of the power-on transient state is improved, the reliability and stability of the product are enhanced, and the power safety and the power efficiency of the terminal product are greatly improved. Meanwhile, due to the significant reduction of the inrush current, a power adapter with a more optimal specification can be selected, the cost is further reduced and the power supply efficiency is improved, and the green concept of low carbon and environmental protection of the country is met.

[0051] The beneficial effects of the utility model are embodied in the above-mentioned preferred embodiments of the utility model, and are not used to limit the utility model, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model should be included in the protection scope of the utility model.

Claims

1. A power supply timing control circuit for an RF front-end PA chip, characterized in that, The power supply timing control circuit includes: Two sets of buck circuits, each set of buck circuits uses a JW5393 Power-IC; The Power-IC has an input voltage of 12V, an output voltage of 5V, and an operating frequency of 600KHz. The enable pin EN of the Power-IC is connected to a GPIO25 pin of the Wi-Fi 6-AX3000 chip via a P4R10 resistor. The standard voltage level of the GPIO25 pin is 1.8V, and its default state is low. The output terminal VOUT of the Power-IC is connected to the power input terminal of the RF front-end PA chip; During the power-on process, the Power-IC is in a turned-off state until the software initialization is completed. Then, the enable signal is pulled high through the GPIO25 pin, and the Power-IC starts to output a 5V voltage, at which point the RF front-end PA chip begins to work.

2. The power supply timing control circuit for the RF front-end PA chip according to claim 1, characterized in that, The two sets of buck circuits are used to supply power to the 2.4G and 5G RF front-end PA chips, respectively. The enable terminals EN of the two sets of buck circuits are connected to the GPIO25 pin of the Wi-Fi 6-AX3000 chip through the same P4R10 resistor.

3. The power supply timing control circuit for the RF front-end PA chip according to claim 1, characterized in that, The input terminal VIN of the Power-IC is connected to a 12V DC power supply, and the output terminal VOUT is connected to the power input terminal of the RF front-end PA chip through filter capacitors C1 and C2. The filter capacitors C1 and C2 are connected in parallel to reduce the ripple of the output voltage.

4. The power supply timing control circuit for the RF front-end PA chip according to claim 1, characterized in that, The P4R10 resistor has a resistance of 10kΩ and is used to limit the current of the GPIO25 pin to prevent overcurrent damage to the Wi-Fi 6-AX3000 chip.

5. The power supply timing control circuit for the RF front-end PA chip according to claim 1, characterized in that, The enable pin EN of the Power-IC remains low at the moment of system power-on until the Wi-Fi 6-AX3000 chip completes software initialization and outputs a high-level signal through the GPIO25 pin, enabling the Power-IC to control the power timing of the RF front-end PA chip.

6. The power supply timing control circuit for the RF front-end PA chip according to claim 1, characterized in that, The output voltage VOUT of the Power-IC is connected to the power input terminal of the RF front-end PA chip through a diode D1. The diode D1 is used to prevent reverse current from damaging the Power-IC.

7. The power supply timing control circuit for the RF front-end PA chip according to claim 1, characterized in that, The power input terminal of the RF front-end PA chip is also connected to a protection resistor R1, which has a resistance of 1Ω. This protection resistor R1 is used to limit the startup current of the RF front-end PA chip and reduce the inrush current.

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