Parallel analog-to-digital conversion device based on synchronous triggering of single chip microcomputer

Abstract

The utility model relates to the technical field of electronic measurement, in particular to a parallel analog-to-digital conversion device based on synchronous triggering of a single-chip microcomputer, which comprises a preset single-chip microcomputer, a square-wave generator and a parallel analog-to-digital converter, and is characterized in that the preset single-chip microcomputer is connected with the square-wave generator to control the square-wave generator to output two paths of synchronous clock signals; the square wave generator is respectively connected with the preset single-chip microcomputer and the analog-to-digital conversion module so as to trigger the analog-to-digital conversion module to sample at a rising edge and trigger direct memory access of the preset single-chip microcomputer at a falling edge to carry parallel data to a memory according to the two paths of synchronous clock signals; the parallel analog-to-digital converter is connected with the preset single-chip microcomputer so as to carry out analog-to-digital conversion on the sampled external data and input corresponding digital signals to an input and output interface of the preset single-chip microcomputer. Therefore, the problems that a single-chip microcomputer scheme is limited by interrupt response delay and GPIO interface reading speed, and a parallel ADC cannot be directly driven to achieve high-frequency sampling and the like are solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic measurement technical field, especially a kind of parallel analog-digital conversion device based on single-chip synchronous trigger. BACKGROUND

[0002] In high-speed analog-digital conversion system, the driving of parallel ADC (Parallel ADC, analog-digital converter) (such as ADS805) needs to be strictly synchronous with the sampling clock and data storage timing. In the traditional scheme, because the GPIO interface (General Purpose Input Output, general purpose input output interface) is limited in reading speed, high-frequency sampling (≥10MHz) must rely on FPGA (Field-Programmable Gate Array, Field-Programmable Gate Array) to realize clock generation, data capture and cache control. For example, FPGA writes state machine through hardware description language (Verilog / VHDL), directly controls the sampling clock of ADC and reads parallel data. However, such a scheme has the following significant defects:

[0003] (1) High development complexity: FPGA needs special development tools and hardware description language knowledge, and the development cycle is long.

[0004] (2) High cost and resource waste: the cost of FPGA and supporting circuit is much higher than that of single-chip solution, and simple data transfer task occupies FPGA logic resources, causing performance redundancy.

[0005] (3) If you want to complete the equivalent sampling of high-frequency signal, FPGA is difficult to generate sampling clock only by frequency division without relying on phase-locked loop, and the signal distortion is serious

[0006] (4) Inconvenient for subsequent data processing: in the field of digital signal processing, after sampling the signal, data analysis (such as fast Fourier transform FFT or digital filter FIR) is often needed. These algorithms are difficult to implement in FPGA, and even if they are implemented, they will occupy a lot of hardware resources.

[0007] Although the existing single-chip solution is low in cost, it is limited by the interrupt response delay and the reading speed of GPIO interface, and cannot directly drive parallel ADC to realize high-frequency sampling, but there are still a few attempts to use single-chip + DMA (Direct Memory Access, direct memory access) scheme, but this way still has the defect of data misplacement caused by clock desynchronization, and the sampling rate is difficult to break through 1MHz. INVENTION CONTENTS

[0008] The utility model provides a kind of parallel analog-digital conversion device based on single-chip synchronous triggering, to solve the scheme of single-chip is limited to interrupt response delay and GPIO interface reading speed, cannot directly drive parallel ADC to realize high-frequency sampling, and a few attempts to adopt the scheme of single-chip+DMA, still cause data misregistration due to clock asynchronization, and sampling rate is difficult to break through 1MHz etc.

[0009] The utility model provides a kind of parallel analog-digital conversion device based on single-chip synchronous triggering, including: preset single-chip, square wave generator and parallel analog-digital converter, wherein, the preset single-chip is connected with the square wave generator, for controlling the square wave generator output two-way synchronous clock signal, wherein, the two-way synchronous clock signal includes first clock signal and second clock signal;The square wave generator is connected with the preset single-chip and the analog-digital conversion module respectively, for according to the two-way synchronous clock signal, in rising edge trigger the analog-digital conversion module sampling, in falling edge trigger the direct memory access of the preset single-chip and carry parallel data to memory;The parallel analog-digital converter is connected with the preset single-chip, for the external data sampled carries out analog-digital conversion, to obtain corresponding digital signal, and the corresponding digital signal is input to the input and output interface of the preset single-chip.

[0010] Optionally, the preset single-chip uses STM32F407ZGT6 single-chip.

[0011] Optionally, the STM32F407ZGT6 single-chip is connected with the square wave generator through I2C bus, to dynamically configure the clock frequency of the square wave generator, so that the square wave generator outputs the two-way synchronous clock signal.

[0012] Optionally, the square wave generator uses SI5351 chip.

[0013] Optionally, the first clock signal output by the SI5351 chip is connected to the timer input capture pin of the preset single-chip, and the second clock signal output by the SI5351 chip is connected to the sampling clock end of the analog-digital conversion module.

[0014] Optionally, the parallel analog-digital converter uses ADS805 chip.

[0015] Optionally, the digital output pin of the ADS805 chip is connected with the same group of 12 input and output interfaces of the preset single-chip.

[0016] The parallel analog-digital conversion device based on single-chip machine synchronous triggering provided by the utility model replaces traditional FPGA architecture with pure single-chip machine scheme, solves the problems of high FPGA development complexity and high cost, and significantly simplifies the hardware design process while ensuring at least 10MHz equivalent sampling rate, reduces the development threshold, and is applicable to high-speed data acquisition and embedded instrument development scenarios.

[0017] Additional aspects and advantages of the utility model will be partially given in the following description, some will become obvious from the following description, or will be understood through the practice of the utility model. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and / or additional aspects and advantages of the utility model will become apparent and more readily understood from the following description of embodiments, in conjunction with the accompanying drawings, in which:

[0019] Figure 1 It is a block schematic diagram of a parallel analog-digital conversion device based on single-chip machine synchronous triggering provided according to the utility model;

[0020] Figure 2 It is an internal architecture diagram of I5153 square wave generator provided according to the utility model;

[0021] Figure 3 It is a chip pin diagram of ADS805 analog-digital converter provided according to the utility model;

[0022] Figure 4 It is a specific structure schematic diagram of a parallel analog-digital conversion device based on single-chip machine synchronous triggering provided according to the utility model;

[0023] Figure 5 It is a sampling timing diagram of ADS805 analog-digital converter provided according to the utility model;

[0024] Figure 6 It is a waveform diagram of 1MHz sine wave being sampled equivalently and drawn by using 990100Hz clock provided according to the utility model;

[0025] Figure 7 It is a waveform diagram of 5KHz sine wave being sampled in real time by using 1MHz clock provided according to the utility model.

[0026] BRIEF DESCRIPTION OF DRAWINGS

[0027] 10-parallel analog-digital conversion device based on single-chip machine synchronous triggering, 102-square wave generator and 103-parallel analog-digital converter. DETAILED DESCRIPTION

[0028] The embodiments of the present application are described below in detail, examples of which are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the drawings are exemplary and are intended to explain the present application, and cannot be understood as a limitation of the present application.

[0029] The single-chip microcomputer synchronous triggering-based parallel analog-digital conversion device of the embodiments of the present application is described below with reference to the drawings.

[0030] Figure 1 is a block schematic diagram of the single-chip microcomputer synchronous triggering-based parallel analog-digital conversion device of the embodiments of the present application.

[0031] As shown in Figure 1 , the single-chip microcomputer synchronous triggering-based parallel analog-digital conversion device 10 comprises a preset single-chip microcomputer 101, a square wave generator 102 and a parallel analog-digital converter 103.

[0032] The preset single-chip microcomputer 101 is connected with the square wave generator 102, for controlling the square wave generator 102 to output two-way synchronous clock signals, wherein the two-way synchronous clock signals comprise a first clock signal and a second clock signal. The square wave generator 102 is connected with the preset single-chip microcomputer 101 and the analog-digital conversion module 103 respectively, for triggering the analog-digital conversion module to sample according to the two-way synchronous clock signals at the rising edge, and triggering the direct memory access (DMA) of the preset single-chip microcomputer to carry the parallel data to the memory at the falling edge. The parallel analog-digital converter 103 is connected with the preset single-chip microcomputer 101, for performing analog-digital conversion on the sampled external data to obtain corresponding digital signals, and inputting the corresponding digital signals to the input-output interface of the preset single-chip microcomputer.

[0033] In some embodiments, the preset single-chip microcomputer 101 can adopt an STM32F407ZGT6 single-chip microcomputer, which is connected with the square wave generator 102 through an I2C bus to dynamically configure the clock frequency of the square wave generator 102, so that the square wave generator 102 outputs two-way synchronous clock signals (CLK1, CLK2), and realizes the triggering of the DMA of the preset single-chip microcomputer by using the timer input capture function.

[0034] In some embodiments, as Figure 2As shown, the square wave generator 102 adopts the SI5351 chip, the first clock signal output by the SI5351 chip is connected to the timer input capture pin of the preset single-chip microcomputer 101, the CLK1 falling edge triggers the timer capture, the DMA of the preset single-chip microcomputer 101 reads the data of the GPIO interface to carry the parallel data to the memory of the preset single-chip microcomputer 101, thereby omitting the FPGA data caching link, the second clock signal output by the SI5351 chip is connected to the sampling clock end of the parallel analog-digital converter 103, the CLK2 rising edge triggers the analog-digital conversion, and the parallel analog-digital converter 103 performs analog-digital conversion on the sampled external data to obtain the corresponding digital signal. Since the square wave generator 102 has the same crystal oscillator and the phase difference of the two clock signals is small, the sampling and storage can be strictly synchronized, the data transmission rate is consistent with the analog-digital conversion sampling rate, and the highest rate can reach at least 10MSPS, and one rising edge is converted and the other falling edge is carried, so that there is sufficient time to stabilize the ADC conversion result.

[0035] In some embodiments, as shown in Figure 3 The parallel analog-digital converter 103 can adopt the 12-bit parallel output ADS805 chip, the digital output pin of the ADS805 chip is connected to the same group of 12 input and output GPIO interfaces of the preset single-chip microcomputer 101, external data is sampled according to the preset sampling frequency, and analog-digital conversion is performed to obtain the corresponding digital signal, and the corresponding digital signal is input to the GPIO interface of the preset single-chip microcomputer 101, without the intervention of FPGA or external logic devices for data carrying.

[0036] The sampling frequency of the parallel analog-digital converter 103 is adaptively set according to the bearing range of the preset single-chip microcomputer IO port and the output range of the SI5351 chip, which has strong flexibility and can overcome the clock requirement of high-frequency equivalent sampling.

[0037] The working process of the parallel analog-digital conversion device based on single-chip microcomputer synchronous triggering according to the embodiment of the application is described below.

[0038] As shown in Figures 2-4 First, the hardware is built, and the specific process is as follows:

[0039] (1)SI5351 chip SDA, SCL pin through I2C bus and the corresponding pin of STM32F407ZGT6 single-chip microcomputer, and with STM32F407ZGT6 single-chip microcomputer common and connection, so that the STM32F407ZGT6 single-chip microcomputer for SI5351 chip power supply, and dynamically configure the clock frequency of SI5351 chip; The clock signal output by the SMA port of the SI5351 chip is connected to the sampling clock end of the ADS805 chip, and the clock signal output by the pin port of the SI5351 chip is connected to the input capture trigger pin set by the STM32F407ZGT6 single-chip microcomputer.

[0040] (2) The ADS805 chip is powered by an external power supply, the IN pin of the ADS805 chip receives external input, and the B1-B12 output pin of the ADS805 chip is connected to the same group of GPIO interface of the STM32F407ZGT6 single-chip microcomputer.

[0041] (3) The STM32F407ZGT6 single-chip microcomputer can be powered by a computer or an external power supply system, and the STM32F407ZGT6 single-chip microcomputer can complete communication with the SI5351 chip according to the manual of the SI5351 chip, initialize and set the output frequency; The STM32F407ZGT6 single-chip microcomputer selects the 0-11 pin of a certain group of GPIO (A, B, C, D, E, F, G) interface and configures it as a pull-down input mode to connect with the B1-B12 pin of the ADS805 chip; The STM32F407ZGT6 single-chip microcomputer selects an advanced timer (such as TIM1) and configures it to count and enter the input capture mode, sets the input capture pin to falling edge trigger, and connects with the pin port of the SI5351 chip; The STM32F407ZGT6 single-chip microcomputer configures the DMA data stream, which is triggered by the input capture, the data transfer direction is from the GPIO interface to the memory, and the DMA interrupt is set to manually control the sampling.

[0042] Further, after completing the hardware construction, the code is burned, the signal source is input to the ADS805 chip, the appropriate sampling frequency is set, the sampled array is checked in the debugging interface, the script is downloaded into the txt file, and matlab or python drawing is used to show.

[0043] As Figures 5-6As shown, after the hardware building and the code burning are completed, the parallel analog-digital conversion device based on the single-chip microcomputer synchronous triggering is obtained, and the specific working process of the parallel analog-digital conversion device based on the single-chip microcomputer synchronous triggering is as follows: the STM32F407ZGT6 single-chip microcomputer dynamically configures the clock frequency of the SI5351 chip through the I2C bus, so that the SI5351 chip outputs two synchronous clock signals CLK1 and CLK2, the SI5351 chip synchronously sends the clock signal CLK1 to the timer input capture pin of the STM32F407ZGT6 single-chip microcomputer, and sends the clock signal CLK2 to the sampling clock end of the ADS805 chip, when the clock signal CLK2 is a rising edge, the analog-digital conversion of the ADS805 chip is triggered, external data is sampled according to the preset sampling frequency, and analog-digital conversion is performed, and 12 corresponding digital signals are output, when the clock signal CLK1 is a falling edge, the timer capture is triggered, and the DMA of the STM32F407ZGT6 single-chip microcomputer reads the corresponding digital signals of the GPIO interface, so as to carry the parallel data to the memory.

[0044] In summary, the parallel analog-digital conversion device based on the single-chip microcomputer synchronous triggering has the following beneficial effects:

[0045] (1) The pure single-chip microcomputer scheme replaces the traditional FPGA architecture, and only the single-chip microcomputer, the square wave generator and the parallel analog-digital converter are used to realize the clock generation, data acquisition and storage functions, so that the problems of high development complexity and high cost of the FPGA are solved, the hardware design process is significantly simplified, the development threshold is reduced, and the device is suitable for high-speed data acquisition and embedded instrument development scenes;

[0046] (2) The performance bottleneck of the single-chip microcomputer driving the parallel ADC is broken, the sampling rate can reach more than 10MSPS, the timing synchronization accuracy is high, and the sampling result is stable;

[0047] (3) The use threshold of the parallel analog signal to digital signal is reduced, and the device can be popularized to all 16-bit or below parallel analog signal to digital signal driving, so that the applicability of the single-chip microcomputer scheme is significantly improved;

[0048] (4) The external parallel analog signal to digital signal mode solves the defect that the on-chip analog signal to digital signal of the single-chip microcomputer can only collect positive voltage, and improves the performance of the single-chip microcomputer.

[0049] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or N embodiments or examples. Furthermore, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples, without mutual contradiction.

[0050] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "N" is at least two, for example, two, three, etc., unless otherwise specifically limited.

Claims

1. A parallel analog-to-digital conversion device based on single-chip synchronous triggering, characterized in that, The application relates to a single-chip microcomputer, a square wave generator and a parallel analog-digital converter. The preset single-chip microcomputer is connected with the square wave generator and is used for controlling the square wave generator to output two-way synchronous clock signals, wherein the two-way synchronous clock signals comprise a first clock signal and a second clock signal. The square wave generator is connected with the preset single-chip microcomputer and the parallel analog-digital converter respectively, is used for triggering the parallel analog-digital converter to sample according to the two-way synchronous clock signals at a rising edge, and triggering the direct memory access of the preset single-chip microcomputer to carry parallel data to a memory at a falling edge. The parallel analog-digital converter is connected with the preset single-chip microcomputer and is used for carrying out analog-digital conversion on sampled external data to obtain corresponding digital signals and inputting the corresponding digital signals into an input-output interface of the preset single-chip microcomputer. The preset single-chip microcomputer adopts an STM32F407ZGT6 single-chip microcomputer.

2. The single-chip microcomputer-based parallel analog-digital conversion device according to claim 1, characterized in that, The STM32F407ZGT6 single-chip microcomputer is connected with the square wave generator through an I2C bus to dynamically configure the clock frequency of the square wave generator, so that the square wave generator outputs the two-way synchronous clock signals.

3. The single-chip microcomputer-based parallel analog-digital conversion device according to claim 2, characterized in that, The square wave generator adopts an SI5351 chip.

4. The single-chip microcomputer-based parallel analog-digital conversion device according to claim 1, characterized in that, The first clock signal output by the SI5351 chip is connected with a timer input capture pin of the preset single-chip microcomputer, and the second clock signal output by the SI5351 chip is connected with a sampling clock end of the parallel analog-digital converter.

5. The single-chip microcomputer-based parallel analog-digital conversion device according to claim 4, characterized in that, The parallel analog-digital converter adopts an ADS805 chip.

6. The single-chip microcomputer-based parallel analog-digital conversion device according to claim 1, characterized in that, Digital output pins of the ADS805 chip are connected with 12 input-output interfaces of the preset single-chip microcomputer.

7. The single-chip microcomputer-based synchronous trigger parallel analog-digital conversion device according to claim 6, characterized in that, ​

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