Time sequence control equipment and broadcasting system
By employing FPGA chips and multi-module timing control devices in the broadcast system, the problem of insufficient timing control accuracy in traditional equipment has been solved, achieving precise synchronization of equipment and improved system stability, ensuring power stability and data security.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-13
- Publication Date
- 2026-03-24
AI Technical Summary
Traditional timing control equipment has limited timing control accuracy in broadcast systems, making it difficult to meet the strict requirements of starting, running, and shutting down multiple devices, leading to signal conflicts and interference, and affecting the continuity and clarity of sound quality.
An FPGA chip is used as the timing control core, combined with a power module, an execution module and a storage module. The power module includes a TVS diode surge absorption circuit, a two-stage voltage regulator unit and a supercapacitor power-off sustaining unit. The execution module includes multiple MOSFET drive channels and an RC snubber circuit. The storage module uses a ferroelectric memory and is configured with a dual-storage area structure.
It achieves precise synchronization of equipment in the broadcasting system, improves system stability and reliability, avoids signal conflicts, ensures stable power supply, protects equipment from surges and transient voltage impacts, prevents data loss, and improves the overall reliability and stability of the system.
Smart Images
Figure CN224037493U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of industrial automation control technology, and in particular to broadcasting systems. Background Technology
[0002] In the field of industrial automation control technology, especially in the operation and management of broadcasting systems, timing control equipment plays an indispensable role as a key component ensuring stable system operation and precise control. However, traditional timing control equipment often reveals numerous problems when faced with the complex control requirements of broadcasting systems.
[0003] Traditional equipment has limited timing control precision, making it difficult to meet the strict requirements of multiple devices in a broadcasting system for startup, operation, and shutdown times. This leads to frequent signal conflicts and interference, affecting the continuity and clarity of broadcast audio quality. Utility Model Content
[0004] This invention addresses the problem of limited timing control accuracy in existing technologies by providing a timing control device and a broadcasting system.
[0005] The technical solution adopted in this utility model is:
[0006] A timing control device includes a timing control module, a power supply module, an execution module, and a storage module, wherein:
[0007] The timing control module uses an FPGA chip, which integrates a clock divider submodule, a state machine submodule, and a pulse width modulation submodule.
[0008] The power module includes a TVS diode surge absorption circuit, a two-stage voltage regulation unit, and a supercapacitor power failure maintenance unit.
[0009] The execution module includes multiple MOSFET drive channels;
[0010] The storage module adopts a ferroelectric memory and is configured with a dual-storage area structure;
[0011] The power supply pins of the FPGA chip are connected to the 3.3V output terminal of the power module;
[0012] The storage module is connected to the I / O pins of the FPGA chip;
[0013] The input terminal of each MOSFET drive channel is connected to the IO pin of the FPGA chip, and the output terminal of each MOSFET drive channel is connected to the power supply line of an external device.
[0014] The input terminal of the power module is connected to an external power supply, and the output terminal supplies power to the timing control module, the execution module, and the storage module.
[0015] Furthermore, the power module includes a TVS diode surge absorption circuit, a two-stage voltage regulator unit, a supercapacitor power-off sustaining unit, and a Schottky diode; the Schottky diode is used to prevent reverse current.
[0016] The two-stage voltage regulation unit includes a front-end DC / DC converter, a π-type filter circuit, and a rear-end LDO regulator.
[0017] The TVS diode surge absorption circuit is connected in parallel between the power input terminal and ground.
[0018] The output of the front-stage DC / DC converter is connected to the rear-stage LDO regulator through the π-type filter circuit.
[0019] The supercapacitor power failure sustaining unit is connected in parallel with the main power supply through the Schottky diode to form a power failure sustaining circuit.
[0020] Furthermore, each of the MOSFET drive channels includes a MOSFET drive circuit, a current-limiting resistor, and a resettable fuse;
[0021] The gate of the MOSFET driving circuit is the input terminal of the MOSFET driving channel.
[0022] The gate of the MOSFET driving circuit is connected to the IO pin of the FPGA chip through the current-limiting resistor, and the drain of the MOSFET driving circuit is connected to the power line of the external device after being connected in series with the self-resetting fuse.
[0023] Furthermore, the dual-storage area structure of the storage module includes a main storage area and a mirrored storage area;
[0024] The main storage area and the mirror storage area are connected to the I / O pins of the FPGA chip, and the FPGA chip controls the read and write operations of the main storage area and the mirror storage area.
[0025] Furthermore, the clock divider submodule is connected to the state machine submodule and the pulse width modulation submodule, providing clock signals to the state machine submodule and the pulse width modulation submodule; the clock divider submodule is connected to an external crystal oscillator, and the clock divider submodule divides the external crystal oscillator clock into two clock signals, one clock signal entering the input terminal of the state machine submodule, and the other clock signal entering the input terminal of the pulse width modulation submodule;
[0026] Each state machine in the state machine submodule includes a 32-bit prescaler counter and a 4-bit state register. The state machine submodule generates control signals to control the level of the IO pins of the FPGA chip connected to the storage module.
[0027] The output of the pulse width modulation submodule is connected to the PWM dedicated pin of the FPGA chip to generate a drive waveform with an adjustable duty cycle; the PWM dedicated pin of the FPGA chip is connected to the gate of the MOSFET drive circuit.
[0028] Furthermore, the execution module also includes an RC snubber circuit; the RC snubber circuit is connected in series between the drain of the MOSFET driving circuit and the external device to suppress transient voltage surges.
[0029] Based on the same inventive concept, this utility model also provides a broadcasting system, which includes the aforementioned timing control device.
[0030] The beneficial effects of this utility model are:
[0031] First, the timing control device provided by this invention uses an FPGA chip, which has powerful parallel processing capabilities and can realize complex timing logic control, ensuring precise synchronization of various devices in the broadcasting system and improving the overall system stability. Second, the power supply module includes multiple protection and voltage regulation units, effectively absorbing surge voltages, providing stable power, and providing sustaining power during power outages to ensure safe shutdown or switching to a safe state. Third, the execution module includes multiple MOSFET drive channels and is designed with self-resetting fuses and RC snubber circuits, which can reliably control the power supply to external devices, protecting them from overcurrent and transient voltage surges. Finally, the storage module uses ferroelectric memory with a dual-storage area structure, which has the advantages of fast read / write speeds and strong anti-interference capabilities, ensuring safe and reliable data storage, preventing data loss from causing abnormal device operation, and improving the overall reliability and stability of the system. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 This is a schematic diagram of a timing control device. Detailed Implementation
[0034] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.
[0035] The following disclosure provides many different embodiments or examples for implementing various structures of this invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this invention.
[0036] The embodiments of the utility model will now be described in detail with reference to the accompanying drawings.
[0037] The timing control device disclosed in this embodiment includes the following modules: timing control module 2, power supply module 1, execution module 3, and storage module 4. (See attached...) Figure 1 As shown.
[0038] The following describes the internal components of timing control module 2 and the connections between them:
[0039] The timing control module 2 uses an FPGA chip, which integrates a clock divider submodule FD, a state machine submodule SM, and a pulse width modulation (PWM) submodule. The clock divider submodule FD connects to the state machine submodule SM and the PWM submodule, providing them with clock signals. Specifically, the clock divider submodule FD connects to an external crystal oscillator, dividing the external crystal clock into two clock signals: one input to the state machine submodule SM and the other to the PWM submodule. Each state machine in the state machine submodule SM contains a 32-bit prescaler counter and a 4-bit state register, generating control signals to control the I / O pin levels of the FPGA chip connected to the storage module 4. The output of the PWM submodule connects to the FPGA chip's dedicated PWM pin, generating a drive waveform with an adjustable duty cycle.
[0040] The following describes the internal components of power module 1 and the connections between them:
[0041] Power module 1 includes a TVS diode surge absorption circuit, a two-stage voltage regulator unit, and a supercapacitor SC power-off sustaining unit. The TVS diode surge absorption circuit is connected in parallel between the power input terminal and ground to absorb surge voltage. The two-stage voltage regulator unit consists of a pre-stage DC / DC converter, a π-type filter circuit, and a post-stage LDO regulator. The output of the pre-stage DC / DC converter is connected to the post-stage LDO regulator through the π-type filter circuit to achieve voltage regulation of the input voltage. The supercapacitor SC power-off sustaining unit is connected in parallel with the main power supply VDD through a Schottky diode SBD (to prevent reverse current), forming a power-off sustaining circuit to ensure that the equipment can continue to operate normally for a period of time during a power outage, completing critical operations or entering a safe state. (See attached diagram) Figure 1 As shown.
[0042] The following describes the internal components of Module 3 and the connections between them:
[0043] Execution module 3 includes multiple MOSFET drive channels, each containing a MOSFET drive circuit, a current-limiting resistor R, and a resettable fuse FU. The gate of the MOSFET drive circuit serves as the input, connected to the FPGA chip's I / O pin via the current-limiting resistor R. The current-limiting resistor R ensures the MOSFET drive circuit's gate is at a low level when the FPGA chip is not outputting a signal, preventing false triggering. The drain of the MOSFET drive circuit is connected in series with the resettable fuse FU to the external device's power supply line. The resettable fuse FU automatically disconnects the circuit in case of abnormal current, providing protection. Furthermore, execution module 3 includes an RC snubber circuit, connected in series between the drain of the MOSFET drive circuit and the external device, used to suppress transient voltage surges and protect the external device from high-voltage spikes. (See attached diagram) Figure 1 As shown.
[0044] The following describes the internal components of storage module 4 and the connections between them:
[0045] Storage module 4 employs a ferroelectric memory with a dual-storage-area structure: a primary storage area (PSA) using HP's FM28V202A and a mirror storage area (MSA) also using HP's FM28V202A. Both the primary PSA and the mirror MSA are connected to the FPGA chip's I / O pins, and their read / write operations are controlled by the FPGA chip. During normal operation, the primary PSA stores various data generated during device operation, such as configuration parameters, operating status information, and monitoring data. The mirror MSA serves as a backup area, used to quickly recover data in case of primary PSA failure or data loss, ensuring normal device operation and data integrity, and improving system reliability and stability. (See attached diagram) Figure 1 As shown.
[0046] The following describes the connection relationships and signal flow between the modules:
[0047] Connections between power module 1 and other modules: The input of power module 1 is connected to an external power supply, and the output powers the timing control module 2, the execution module 3, and the storage module 4. Specifically, the power supply pins of the FPGA chip are connected to the 3.3V output of power module 1.
[0048] Connection between storage module 4 and timing control module 2: Storage module 4 is connected to the IO pins of the FPGA chip. Furthermore, both the main storage area PSA and the mirror storage area MSA are connected to the IO pins of the FPGA chip, and their read / write operations are controlled by the FPGA chip.
[0049] Connection between execution module 3 and timing control module 2: The input of each MOSFET drive channel is connected to the IO pin of the FPGA chip, and the output is connected to the external device power line and the external power supply VCC. The external device power line is connected to the broadcast system's device BE. Specifically, the gate of the MOSFET drive circuit serves as the input, connected to the IO pin of the FPGA chip through a current-limiting resistor R, while its drain is connected to the external device power line via a self-resetting fuse FU in series. In addition, execution module 3 includes an RC snubber circuit, which is connected in series between the drain of the MOSFET drive circuit and the external device to suppress transient voltage surges. Its source is grounded to GND via the ground pin of the broadcast system's device BE.
[0050] Connections of internal submodules in timing control module 2: The clock divider submodule FD is connected to the state machine submodule SM and the pulse width modulation submodule, responsible for providing clock signals to them. The clock divider submodule FD connects to an external crystal oscillator, dividing the external crystal clock into two clock signals: one enters the input of the state machine submodule SM, and the other enters the input of the pulse width modulation submodule. Each state machine in the state machine submodule SM contains a 32-bit prescaler counter and a 4-bit state register. The generated control signals are used to control the level of the IO pins of the FPGA chip connected to storage module 4. The output of the pulse width modulation submodule is connected to the PWM dedicated pin of the FPGA chip, generating a drive waveform with an adjustable duty cycle. This PWM dedicated pin is connected to the gate of the MOSFET drive circuit. (See attached diagram) Figure 1 As shown.
[0051] The working principle of the timing control device disclosed in this embodiment is described below:
[0052] After the timing control device starts, power module 1 first obtains power from an external power supply. After the surge voltage is absorbed by the TVS diode surge absorption circuit, it is input to the two-stage voltage regulation unit. The front-stage DC / DC converter performs preliminary voltage conversion, and the output is filtered by the π-type filter circuit. Then, the voltage is further regulated by the rear-stage LDO regulator to provide a stable 3.3V power supply to each module.
[0053] In timing control module 2, an external crystal oscillator provides a clock signal to the clock divider submodule FD. The two clock signals generated after frequency division are transmitted to the state machine submodule SM and the pulse width modulation submodule, respectively. The state machine submodule SM performs state transitions according to the preset logic state and clock signal, and generates control signals using a 32-bit prescaler counter and a 4-bit state register. These control signals control the read and write operations of the storage module 4 through the IO pins of the FPGA chip.
[0054] Simultaneously, the pulse width modulation (PWM) submodule generates a PWM signal with an adjustable duty cycle based on the input clock signal, and outputs it to the gate of the MOSFET driver circuit through the PWM dedicated pin of the FPGA chip. In execution module 3, the MOSFET driver circuit is turned on or off under the control of the PWM signal, thereby controlling the power supply line of the connected external device. The current-limiting resistor R ensures that the gate of the MOSFET driver circuit is in a low-level state when the FPGA chip is not outputting a signal, avoiding false triggering. The resettable fuse FU automatically disconnects the circuit in case of abnormal current, providing protection.
[0055] The main storage area PSA and the mirror storage area MSA in storage module 4 work together under the control of the FPGA chip. The main storage area PSA is used to store data during normal operation, and the mirror storage area MSA is used to store backup data, thereby improving data security and reliability.
[0056] When the equipment loses power, the supercapacitor SC power failure maintenance unit is connected in parallel with the main power supply VDD through the Schottky diode SBD. It uses the electrical energy stored in the supercapacitor SC to provide temporary maintenance power to each module, ensuring that the equipment can complete its current operating tasks or enter a safe state.
[0057] Based on the same inventive concept, this embodiment also provides a broadcasting system that includes the timing control device described above.
[0058] The timing control device disclosed in this embodiment has several advantages. First, it uses an FPGA chip as the timing control core, possessing powerful parallel processing capabilities. It can process multiple timing signals simultaneously, enabling more complex timing logic control. This ensures that all devices in the broadcast system start, run, and shut down according to a precisely set time sequence, avoiding signal conflicts and interference, and improving the overall stability and reliability of the system. Second, the power module includes a TVS diode surge absorption circuit, a two-stage voltage regulator unit, and a supercapacitor power-off sustaining unit. This effectively absorbs surge voltage at the power input, protecting downstream circuits from voltage fluctuations and providing a stable and reliable power environment for each module, ensuring stable operation even when facing external power fluctuations. Third, the execution module includes multiple MOSFET drive channels. Each channel includes a MOSFET drive circuit, a current-limiting resistor, and a resettable fuse. This reliably controls the power supply to external devices, achieving precise power management for various devices in the broadcast system. This prevents damage to drive circuits and external devices due to overcurrent or other issues. Simultaneously, the RC absorption circuit effectively suppresses transient voltage surges, protecting external devices from high-voltage spikes and extending their lifespan. Finally, the storage module adopts ferroelectric memory and is configured with a dual-storage area structure. Ferroelectric memory has the advantages of fast read and write speed, low power consumption, and strong anti-interference ability. The main storage area and the mirror storage area work together to ensure the security and reliability of data storage, avoid abnormal device operation due to data loss, and improve the overall reliability and stability of the system.
Claims
1. A timing control device, comprising a timing control module, a power supply module, an execution module, and a storage module, characterized in that, in: The timing control module uses an FPGA chip, which integrates a clock divider submodule, a state machine submodule, and a pulse width modulation submodule. The power module includes a TVS diode surge absorption circuit, a two-stage voltage regulation unit, and a supercapacitor power failure maintenance unit. The execution module includes multiple MOSFET drive channels; The storage module adopts a ferroelectric memory and is configured with a dual-storage area structure; The power supply pins of the FPGA chip are connected to the 3.3V output terminal of the power module; The storage module is connected to the I / O pins of the FPGA chip; The input terminal of each MOSFET drive channel is connected to the IO pin of the FPGA chip, and the output terminal of each MOSFET drive channel is connected to the power supply line of an external device. The input terminal of the power module is connected to an external power supply, and the output terminal supplies power to the timing control module, the execution module, and the storage module.
2. The timing control device according to claim 1, characterized in that, The power module includes a TVS diode surge absorption circuit, a two-stage voltage regulator unit, a supercapacitor power-off sustaining unit, and a Schottky diode; the Schottky diode is used to prevent reverse current. The two-stage voltage regulation unit includes a front-end DC / DC converter, a π-type filter circuit, and a rear-end LDO regulator. The TVS diode surge absorption circuit is connected in parallel between the power input terminal and ground. The output of the front-stage DC / DC converter is connected to the rear-stage LDO regulator through the π-type filter circuit. The supercapacitor power failure sustaining unit is connected in parallel with the main power supply through the Schottky diode to form a power failure sustaining circuit.
3. The timing control device according to claim 1, characterized in that, Each of the MOSFET drive channels includes a MOSFET drive circuit, a current-limiting resistor, and a resettable fuse; The gate of the MOSFET driving circuit is the input terminal of the MOSFET driving channel; the gate of the MOSFET driving circuit is connected to the IO pin of the FPGA chip through the current limiting resistor, and the drain of the MOSFET driving circuit is connected to the power line of the external device after being connected in series with the self-resetting fuse.
4. The timing control device according to claim 1, characterized in that, The dual-storage area structure of the storage module includes a main storage area and a mirror storage area; The main storage area and the mirror storage area are connected to the I / O pins of the FPGA chip, and the FPGA chip controls the read and write operations of the main storage area and the mirror storage area.
5. The timing control device according to claim 3, characterized in that, The clock divider submodule is connected to the state machine submodule and the pulse width modulation submodule, providing clock signals to the state machine submodule and the pulse width modulation submodule; the clock divider submodule is connected to an external crystal oscillator, and the clock divider submodule divides the external crystal oscillator clock into two clock signals, one clock signal enters the input terminal of the state machine submodule, and the other clock signal enters the input terminal of the pulse width modulation submodule; Each state machine in the state machine submodule includes a 32-bit prescaler counter and a 4-bit state register. The state machine submodule generates control signals to control the level of the IO pins of the FPGA chip connected to the storage module. The output of the pulse width modulation submodule is connected to the PWM dedicated pin of the FPGA chip to generate a drive waveform with an adjustable duty cycle; the PWM dedicated pin of the FPGA chip is connected to the gate of the MOSFET drive circuit.
6. The timing control device according to claim 3 or 5, characterized in that, The execution module also includes an RC snubber circuit; the RC snubber circuit is connected in series between the drain of the MOSFET driving circuit and the external device to suppress transient voltage surges.
7. A broadcasting system, characterized in that, It includes the timing control device according to any one of claims 1-6.