Groove type silicon carbide MOSFET device

Abstract

The utility model relates to the technical field of semiconductor devices, and provides a groove type silicon carbide MOSFET device. The device comprises a substrate, an epitaxial layer and a polycrystalline silicon gate. The epitaxial layer includes a bottom screen junction and a side screen junction. The bottoms of the side screen knots are connected with the bottom screen knots in a staggered mode to form grid staggering. The epitaxial layer is provided with a groove, the connecting position of the side wall and the bottom of the groove is in an arc shape, the bottom of the groove is sunken in the bottom screen junction, and the groove is located between the side screen junctions. Through the three-dimensional grid shielding system formed by the bottom screen junction and the side screen junction, surrounding type shielding can be formed on the polycrystalline silicon gate region below the bottom and the side wall of the groove, the peak electric field intensity borne by the polycrystalline silicon gate oxide layer under high voltage is dispersed and reduced to the maximum extent, and the voltage endurance capability and the gate oxide reliability of the device are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a trench type silicon carbide metal oxide semiconductor field effect transistor (MOSFET) device. BACKGROUND

[0002] Silicon carbide (SiC) material is widely used in the field of power electronics due to its excellent high-temperature, high-frequency and high-power characteristics, especially in high-voltage devices. As one of the core devices, MOSFET is highly concerned due to its high switching speed and low on-state loss. Currently, SiC MOSFET is mainly divided into two structures: planar gate and trench gate. The planar gate structure has simple process and high reliability, but it has the effect of junction field effect transistor (JFET), which leads to large on-state resistance. The trench gate structure eliminates the area with JFET effect through vertical channel, significantly improves the channel mobility and reduces the on-state resistance, but the gate oxide field concentration problem at the bottom of the trench seriously affects the reliability of the device.

[0003] To solve the above problems, the industry usually adopts various means to optimize the performance of the trench type MOSFET. For example, by improving the gate oxide growth process to improve the quality of the gate oxide, or introducing a specific doping region on the sidewall of the trench to improve the electric field distribution. In addition, it also includes optimizing the trench geometry, such as adjusting the sidewall angle or using a round bottom design, and introducing P+ implantation in the source region to alleviate the electric field concentration problem. Although these methods can improve the performance of the device to some extent, there are still certain limitations.

[0004] Specifically, the conventional means in the related art cannot simultaneously consider the goals of reducing the electric field concentration at the bottom of the trench and optimizing the on-state resistance. Especially in the case of high gate oxide field at the bottom of the trench, the long-term reliability of the device is seriously threatened, which further limits its further promotion in high-voltage and high-temperature application scenarios. CONTENT OF THE INVENTION

[0005] In order to more effectively reduce the electric field concentration at the bottom of the trench and optimize the on-state resistance, the present application provides a trench type silicon carbide MOSFET device, which adopts the following technical solution:

[0006] A trench type silicon carbide MOSFET device includes:

[0007] The substrate with an epitaxial layer includes bottom screen junctions and side screen junctions which are staggered with each other, the bottom screen junctions are sunken in the upper surface of the epitaxial layer, the sinking depth of the bottom screen junctions is greater than the depth of the trench; the side screen junctions extend to the upper surface of the epitaxial layer and are staggered with the bottom of the bottom screen junctions to form a grid stagger; the epitaxial layer is provided with a trench, the side wall of the trench is connected with the bottom to form a circular arc shape, the bottom of the trench is recessed in the bottom screen junction, and the trench is located between the side screen junctions.

[0008] A polysilicon gate is arranged in the trench.

[0009] By combining the deep bottom screen junctions and the side screen junctions which form a grid stagger and the bottom of the trench which is recessed in the bottom screen junction, a three-dimensional shielding structure with surrounding shielding effect on the trench bottom area is constructed, which can effectively reduce the gate electric field concentration at the trench bottom and corner, significantly improve the device voltage resistance and reliability, and form a working MOSFET basic unit. By making the side wall connected with the bottom in a circular arc shape, the existence of sharp corners is avoided, which helps to make the electric field distribution of the trench bottom corner area more gentle, further reduces the electric field concentration in this area, and cooperates with the screen junction structure to enhance the reliability of the gate oxide layer.

[0010] Optionally, the substrate and the epitaxial layer have a first type of impurity, and the bottom screen junction and the side screen junction have a second type of impurity which is opposite in polarity to the first type of impurity.

[0011] The above technical solution clearly defines the necessary semiconductor doping type configuration for device operation, so that the PN junction formed by the bottom screen junction and the side screen junction (second type of impurity, such as P type) and the epitaxial layer (first type of impurity, such as N type) can generate a depletion layer under reverse bias, thereby effectively modulating the electric field distribution in the epitaxial layer and realizing the electric field shielding function of the trench area.

[0012] Optionally, a body layer is located in the epitaxial layer, and the body layer has the second type of impurity.

[0013] An epitaxial bottom layer is located below the body layer and the bottom screen junction.

[0014] A first doped layer is located on the body layer, and the first doped layer has the first type of impurity.

[0015] A second doped layer is located on the first doped layer, and the second doped layer has the first type of impurity, wherein the doping concentration of the second doped layer is higher than that of the first doped layer.

[0016] The body layer, the first doped layer and the second doped layer fill the gap between the side screen junction and the gate.

[0017] The vertical MOSFET active structure including the body layer, the first doped layer (such as N-drift / source extension) and the second doped layer (N+ source) is constructed in the region defined by the side screen junction, which ensures the conduction function of the device and places the active region in the protection of the side screen junction, which helps to form a clearly defined conduction path while achieving the shielding effect.

[0018] Optionally, a gate oxide layer is arranged between the polysilicon gate and the inner wall of the trench.

[0019] The gate oxide layer is arranged between the polysilicon gate and the inner wall of the trench (including the surface of the body layer), which provides the necessary electrical insulation, so that the polysilicon gate can control the formation and turn-off of the channel on the surface of the body layer by crossing the insulation layer through the electric field effect, which is the core structure of the MOSFET switching function.

[0020] Optionally, the angle between the sidewall of the trench and the bottom of the trench is 80-91°.

[0021] The angle of the sidewall of the trench is controlled within a specific range (80-91°), which helps to optimize the formation of the vertical channel, control the length and uniformity of the channel, and affect the sidewall electric field distribution and carrier mobility, thereby facilitating the obtaining of stable and good device characteristics, such as lower on-resistance and consistent threshold voltage.

[0022] Optionally, the trench-type silicon carbide MOSFET device further comprises: an interlayer dielectric layer located above the polysilicon gate, the second doped layer and the side screen junction, the interlayer dielectric layer having a contact hole, the contact hole exposing a part of the surface of the second doped layer.

[0023] The interlayer dielectric layer (ILD) is arranged to realize the electrical isolation between different conductive regions (polysilicon gate, source, screen junction) on the surface of the device and the upper metal wiring; the formation of the contact hole provides a predetermined channel for the electrical connection between the upper metal conductor and the second doped layer (N+ source) of the device.

[0024] Optionally, the trench-type silicon carbide MOSFET device further comprises: a metal silicide layer arranged on the exposed surface of the second doped layer in the contact hole.

[0025] The metal silicide layer formed on the surface of the N+ source (second doped layer) at the bottom of the contact hole can greatly reduce the contact resistance between the subsequently deposited metal conductive layer and the highly doped silicon, ensuring that the source current can be efficiently injected / extracted, which plays an important role in improving the large current performance of the device and reducing the on-state loss.

[0026] Optionally, the trench-type silicon carbide MOSFET device further comprises: a metal conductive layer on the interlayer dielectric layer and the metal silicide layer; and a passivation layer and a buffer protection layer arranged in sequence on the metal conductive layer.

[0027] By the above technical solution, the metal conductive layer constitutes the source electrode and the surface wiring structure of the device; and the passivation layer and the buffer protection layer (resin layer) on the metal conductive layer together provide effective environmental isolation (moisture-proof and pollution-proof) and mechanical protection (scratch-proof and stress buffering) for the device, thereby significantly improving the reliability and stability of the device during packaging, testing and long-term use.

[0028] Optionally, the trench-type silicon carbide MOSFET device further comprises: a metal back plate connected to the back surface of the substrate through an ohmic contact layer.

[0029] By the above technical solution, the ohmic contact layer and the metal back plate formed on the back surface of the substrate constitute a low-resistance drain electrode of the device, which not only ensures that the drain current can be efficiently extracted, reduces the total on-resistance of the device, but also facilitates the heat generated during the operation of the device to be conducted through the back surface, thereby improving the heat dissipation performance of the device and providing a good interface for chip mounting.

[0030] In summary, the present application has at least one of the following beneficial technical effects:

[0031] 1. By combining the deep bottom junction and the side junction formed in a grid staggered manner and the trench bottom recessed in the bottom junction, a three-dimensional shielding structure with a surrounding shielding effect on the trench bottom area is constructed, and a basic active region structure (body layer, doped layer) is defined, which can not only effectively reduce the polysilicon gate electric field concentration at the trench bottom and corner, significantly improve the device voltage resistance and reliability, but also constitute a working MOSFET basic unit.

[0032] 2. By optimizing the shape of the trench bottom surface and making the connection between the side wall and the bottom be in an arc shape, the existence of sharp corners is avoided, which helps to make the electric field distribution at the trench bottom corner area more gentle, further reduces the electric field concentration in this area, and cooperates with the junction structure to enhance the reliability of the polysilicon gate oxide layer. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structure schematic diagram of a planar silicon carbide MOSFET device of related art;

[0034] Figure 2 is a structure schematic diagram of a trench-type silicon carbide MOSFET device of related art;

[0035] Figure 3 is Figure 2An electric field schematic diagram of a trench type silicon carbide MOSFET device in the related art;

[0036] Figure 4 A structure schematic diagram of another trench type silicon carbide MOSFET device in the related art;

[0037] Figure 5 A surface schematic diagram of an epitaxial layer of a trench type silicon carbide MOSFET device of Embodiment 1 of the present application;

[0038] Figure 6 A sectional view of a trench type silicon carbide MOSFET device of the present application, wherein Figure 6 a is a sectional view along Figure 5 line A-A in FIG. 1, Figure 6 b is a sectional view along Figure 5 line B-B in FIG. 1, Figure 6 c is a sectional view along Figure 5 line C-C in FIG. 1;

[0039] Figure 7 A flow schematic diagram of a construction method of a trench type silicon carbide MOSFET device of Embodiment 2 of the present application;

[0040] Figure 8 A sectional view of a structure after step S1 in Figure 7 is executed, wherein Figure 8 a is a sectional view along Figure 5 line A-A in FIG. 1, Figure 8 b is a sectional view along Figure 5 line B-B in FIG. 1;

[0041] Figure 9 A sectional view of a structure after step S2 of Figure 7 is executed, wherein Figure 9 a is a sectional view along Figure 5 line A-A in FIG. 1, Figure 9 b is a sectional view along Figure 5 line C-C in FIG. 1;

[0042] Figure 9 A sectional view of a structure along Figure 10 line C-C in FIG. 1 after step S3 of Figure 7 is executed;

[0043] Figure 5 A sectional view of a structure along Figure 11 line C-C in FIG. 1 after step S4 of Figure 7 is executed;

[0044] Figure 5 A sectional view of a structure after step S5 of Figure 12 is executed, wherein Figure 7 a is a sectional view along Figure 12A cross-sectional view of line AA in the middle. Figure 5 b is along Figure 12 A cross-sectional view of the BB line in the middle. Figure 5 c is along Figure 12 A cross-sectional view of the CC line in the diagram;

[0045] Figure 5 Is execution Figure 13 The structure after step S6 Figure 7 A cross-sectional view of the CC line in the diagram;

[0046] Figure 5 Is execution Figure 14 The structure after step S7 Figure 7 A cross-sectional view of the CC line in the diagram;

[0047] Figure 5 Is execution Figure 15 The structure after step S8 Figure 7 A cross-sectional view of the CC line in the diagram;

[0048] Figure 5 Is execution Figure 16 The structure after step S9 Figure 7 A cross-sectional view of the CC line in the diagram;

[0049] Figure 5 Is execution Figure 17 The structure after step S10 along Figure 7 A cross-sectional view of the CC line in the diagram;

[0050] Figure 5 Is execution Figure 18 The structure after step 11 Figure 7 A cross-sectional view of the CC line in the diagram;

[0051] Figure 5 This is a schematic flowchart of the construction method of the trench-type silicon carbide MOSFET device according to Embodiment 3 of this application;

[0052] Figure 19 Is execution Figure 20 A sectional view of the structure after step S1, wherein Figure 19 a is along Figure 20 A cross-sectional view of line AA. Figure 5 b is along Figure 20 A cross-sectional view of the BB line. Figure 5 c is along Figure 20 A cross-sectional view of the DD line;

[0053] Figure 5 Is execution Figure 21 A sectional view of the structure after step S2, wherein Figure 19 a is along Figure 21 A cross-sectional view of line AA.Figure 5 b is a sectional view along the C-C line of Figure 21

[0054] Figure 5 is a flowchart of a trench type silicon carbide MOSFET device construction method according to Embodiment 4 of the present application;

[0055] Figure 22 is a sectional view of the structure after step S1 in Figure 23 Figure 22 a is a sectional view along the A-A line of Figure 23 Figure 5 b is a sectional view along the B-B line of Figure 23 Figure 5 c is a sectional view along the D-D line of Figure 23

[0056] Figure 23 is a sectional view of the structure after step S2 in Figure 24 Figure 22 a is a sectional view along the A-A line of Figure 24 Figure 5 b is a sectional view along the C-C line of Figure 24

[0057] BRIEF DESCRIPTION OF REFERENCE NUMERALS: 110, drain; 120, N-type substrate; 130, N-type drift region; 131, JEFT region; 140, P-type base region; 141, channel; 150, polysilicon gate; 160, source; 170, source region N-type doped region; 180, trench; 190, source region P-type shield region; 10, substrate; 20, epitaxial layer; 20a, main body region; 20b, side shield region; 20c, trench region; 20d, bottom shield region; 21, epitaxial bottom layer; 22, bottom shield junction; 23, side shield junction; 23a, first depth range; 23b, second depth range; 24, body layer; 25, first doped layer; 26, second doped layer; 27, trench; 30, polysilicon gate; 31, gate oxide layer; 40, interlayer dielectric layer; 41, contact hole; 50, metal silicide layer; 61, metal conductive layer; 62, passivation layer; 63, buffer protection layer; 64, metal back plate; 70, mask; 71, mask opening; 80, protection layer. DETAILED DESCRIPTION

[0058] The present application will be further described in detail below with reference to Figure 5 - Figure 1 The present application will be further described in detail below with reference to

[0059] Figure 24 is a structure schematic diagram of a planar type silicon carbide MOSFET device according to the related art. Refer to Figure 1 ​​​​​​​​The planar SiC MOSFET device includes a drain 110, an N+ substrate 120, an N- drift region 130, a P- base 140, a polysilicon gate 150, a source 160, and an N+ source region 170.

[0060] The polysilicon gate 150 is located on the N- drift region 130 and the P- base 140, where a channel 141 is formed at the P- base 140 underneath the polysilicon gate 150. When an appropriate voltage is applied to the polysilicon gate 150, the channel 141 forms a conductive path allowing electrons to flow from the source 160 to the N- drift region 130, and eventually to the drain 110.

[0061] However, the N- drift region 130 between the two P- bases 140 forms a JEFT region 131, through which the current from the channel 141 to the drain 110 flows. The depletion layers formed by the P- bases 140 on both sides of the JEFT region 131 extend towards the JEFT region 131, creating a JFET-like pinch effect on the current path of the JEFT region 131, which in turn increases the on-resistance of the device.

[0062] Figure 1 is a schematic diagram of a trench SiC MOSFET device of the related art. Referring to Figure 2 The trench SiC MOSFET device includes a drain 110, an N+ substrate 120, an N- drift region 130, a P- base 140, a polysilicon gate 150, a source 160, an N+ source region 170, and a trench 180, where the main body of the polysilicon gate 150 is located within the trench 180.

[0063] Compared to the planar SiC MOSFET device in Figure 2 , the channel 141 of the trench SiC MOSFET device is formed near the sidewall of the trench 180. When an appropriate voltage is applied to the polysilicon gate 150, a conductive path is formed along the sidewall of the trench 180 in the P- base 140, through which electrons flow from the source 160 to the N- drift region 130, and eventually to the drain 110. Since the current directly enters the N- drift region 130 underneath the trench 180, the JFET effect in the planar SiC MOSFET device is substantially eliminated, which helps to achieve a lower on-resistance.

[0064] However, the trench type silicon carbide MOSFET device also brings other problems. Figure 1 Figure 3 is a schematic diagram of an electric field of a trench type silicon carbide MOSFET device in the related art. Figure 2 At this time, the electric field at the bottom and corners of the trench 180 is easy to concentrate, which can affect the reliability of the polysilicon gate oxide.

[0065] Figure 3 is a schematic diagram of another trench type silicon carbide MOSFET device in the related art. Referring to Figure 4 The trench type silicon carbide MOSFET device includes a drain 110, an N-type substrate 120, an N-type drift region 130, a P-type base region 140, a polysilicon gate 150, a source 160, a source region N-type doped region 170, a trench 180, and a source region P-type shielding region 190, wherein the source region P-type shielding region 190 is located at the side of the trench 180.

[0066] Compared with the trench type silicon carbide MOSFET device in Figure 4 , the trench type silicon carbide MOSFET device further sets the source region P-type shielding region 190 located at the side of the trench 180, which can shield at the side of the trench 180, expand the depletion layer and adjust the electric field distribution, thereby reducing the electric field concentration at the bottom and corners of the trench 180 and improving the reliability of the polysilicon gate oxide.

[0067] However, the source region P-type shielding region 190 is mainly located at the side of the trench 180, although they can indirectly alleviate the bottom electric field by affecting the electric field distribution, but they are not the most effective for the electric field shielding of the region directly below the trench 180, and the highest electric field peak often appears at the bottom corner of the trench 180.

[0068] In view of the above problems in the related art, the embodiment of the present application discloses a trench type silicon carbide MOSFET device.

[0069] Figure 2 is a schematic diagram of the surface of the epitaxial layer of the trench type silicon carbide MOSFET device of the embodiment 1 of the present application. Figure 5 is a sectional view of the trench type silicon carbide MOSFET device of the embodiment 1 of the present application, wherein, Figure 6 a is a sectional view along the A-A line in Figure 6 , Figure 5 b is a sectional view along the B-B line in Figure 6 , Figure 5 c is a sectional view along the C-C line in Figure 6 . Referring to Figure 5 ​The trench type silicon carbide MOSFET device comprises a substrate 10, an epitaxial layer 20, a polysilicon gate 30, an inter-layer dielectric (ILD) 40, a metal silicide layer 50, a metal conductive layer 61, a passivation layer 62, a buffer protection layer 63, an ohmic contact layer (not shown in the figure) and a metal back plate 64, wherein the epitaxial layer 20 comprises an epitaxial bottom layer 21, a bottom junction (P+) 22, a side junction (source P+) 23, a body layer (P body) 24, a first doped layer (N-) 25 and a second doped region (N+) 26, and the epitaxial layer 20 is provided with a trench 27.

[0070] The epitaxial layer 20 is located on the substrate 10, and the material of the epitaxial layer 20 includes but is not limited to SiC, and the doping type of the substrate 10 and the epitaxial layer 20 can be N type or P type. The embodiment is described by taking the epitaxial layer 20 as N type, and it is easy to understand that when the epitaxial layer 20 is P type, all the corresponding doping types need to be changed to the opposite type.

[0071] The epitaxial bottom layer 21 is located below the bottom junction 22 and the body layer 24.

[0072] The bottom junction 22 is sunken in the upper surface of the epitaxial layer 20, and the sinking depth of the bottom junction 22 sinking from the epitaxial layer 20 is greater than the depth of the trench 27; the side junction 23 is continuously formed in the epitaxial layer 20, the side junction 23 extends to the upper surface of the epitaxial layer 20, and the bottom of the side junction 23 is staggered with the bottom junction 22 to form a grid stagger. The bottom junction 22 and the side junction 23 have P type impurities.

[0073] The epitaxial layer 20 is provided with a trench 27, the bottom of the trench 27 is recessed in the bottom junction 22, and the trench 27 is located between the side junctions 23.

[0074] The trench 27 is filled with polysilicon to constitute a polysilicon gate 30, and the polysilicon gate 30 and the inner wall of the trench 27 have a gate oxide (GOX) 12 therebetween.

[0075] The bottom surface of the trench 27 can be a plane or an arc surface. The inclination angle between the sidewall of the trench 27 and the trench 27 is 80-91°. Preferably, the inclination angle between the sidewall of the trench 27 and the trench 27 is 86°. The connection part of the bottom surface of the trench 27 and the sidewall of the trench 27 can be a circular arc shape.

[0076] The body layer 24 is located in the epitaxial layer 20 and has P-type impurities. The first doped layer 25 is located on the body layer 24 and has N-type impurities. The second doped layer 26 is located on the first doped layer 25 and has N-type impurities, thereby forming an N+N-P type structure. The doping concentration of the second doped layer 26 is higher than that of the first doped layer 25.

[0077] The body layer 24, the first doped layer 25 and the second doped layer 26 fill the gap between the side screen junction 23 and the polysilicon gate 30.

[0078] The interlayer dielectric layer 40 covers the polysilicon gate 30, the second doped layer 26 and the side screen junction 23. The material of the interlayer dielectric layer 40 can be silicon dioxide (SiO2) and / or silicon nitride (SiN).

[0079] The contact hole (CONT) 41 is formed in the interlayer dielectric layer 40 to expose at least a portion of the second doped layer 26 around the side screen junction 23. The metal silicide layer 50 is located on the surface of at least a portion of the side screen junction 23 and the second doped layer 26 at the contact hole 41.

[0080] The metal conductive layer 61 is located on the metal silicide layer 50 and the interlayer dielectric layer 40, and constitutes the source electrode of the trench-type silicon carbide MOSFET device. The material of the metal conductive layer 61 can be Al, Cu, Al / Cu alloy (such as AlSi alloy, AlCu alloy and AlSiCu alloy) or a combination of the above-mentioned materials.

[0081] The passivation layer 62 is located on the metal conductive layer 61. The material of the passivation layer 62 can be silicon dioxide (SiO2), silicon nitride (SiN) or a combination thereof. The thickness of the passivation layer 62 can be 0.1-20um.

[0082] The buffer protection layer 63 is located on the passivation layer 62. The material of the buffer protection layer 63 can be polyimide (PI), polyamide, polybenzoxazole (PBO) or a combination thereof. The thickness of the buffer protection layer 63 can be 1-50um, preferably 10-15um.

[0083] The thickness of the substrate 10 is 80-250um, preferably 150-200um.

[0084] The metal back plate 64 is connected with the substrate through an ohmic contact layer, and constitutes a drain of the trench type silicon carbide MOSFET device. The material of the metal back plate 64 can be Ti, Ni, Ag, Pd, Au and alloys or combinations thereof.

[0085] The implementation principle of the embodiment 1 of the application is that the three-dimensional grid shielding system formed by the bottom shielding junction and the side shielding structure can form surrounding shielding for the gate region below the trench bottom and the side wall, maximally disperses and reduces the peak electric field intensity borne by the gate oxide layer under high voltage, and significantly improves the voltage resistance capability and gate oxide reliability of the device.

[0086] The structure of the device will be further described below in combination with the construction method of the device.

[0087] Embodiment 2

[0088] Figure 6 is a flow schematic diagram of the construction method of the trench type silicon carbide MOSFET device of the embodiment 2 of the application. Referring to Figure 7 , the method comprises:

[0089] S1, providing a substrate 10 with an epitaxial layer 20, the upper surface of the epitaxial layer 20 is defined with mutually parallel body regions 20a and side shielding regions 20b, a trench region 20c located in the body regions 20a and parallel to the side shielding regions 20b, and a bottom shielding region 20d staggered with the trench region 20c, P-type impurities are injected in alignment with the bottom shielding region 20d to form a bottom shielding junction 22 in the epitaxial layer 20 in a sinking manner, the bottom shielding junction 22 sinks below the upper surface of the epitaxial layer 20, and the sinking depth is greater than the trench depth.

[0090] S2, P-type impurities are injected in alignment with the side shielding regions 20b to form a side shielding junction 23 in the epitaxial layer 20 in a longitudinally continuous extension manner, the side shielding junction 23 continuously extends to the upper surface of the epitaxial layer 20, the bottom of the side shielding junction 23 is staggered with the bottom shielding junction 22 and connected, and a grid stagger is formed.

[0091] S3, P-type impurities are injected in alignment with the body regions 20a to form a body layer 24 in the epitaxial layer 20 in a sinking manner, the body layer 24 sinks below the upper surface of the epitaxial layer 20, and the lower surface of the body layer 24 is flush with the upper surface of the bottom shielding junction 22.

[0092] S4, implanting N-type impurities in alignment with the body region 20a to form a first doped layer 25 and a second doped layer 26 in sequence, a lower surface of the first doped layer 25 is flush with an upper surface of the body layer 24, a lower surface of the second doped layer 26 is flush with an upper surface of the first doped layer 25, and the second doped layer 26 extends to an upper surface of the epitaxial layer 20, wherein a doping concentration of the first doped layer 25 is lower than a doping concentration of the second doped layer 26.

[0093] S5, forming a trench 27 in the epitaxial layer 20 in alignment with the trench region 20c, wherein a circular arc is formed at a junction between a side wall and a bottom of the trench 27, the bottom of the trench 27 is recessed from the bottom well junction 22, and the trench 27 is located between the side well junctions 23.

[0094] S6, activating the implanted N-type impurities and P-type impurities by a high-temperature annealing process.

[0095] S7, forming a gate oxide layer 31 on an inner wall of the trench 27.

[0096] S8, filling the trench 27 with polysilicon to form a polysilicon gate 30.

[0097] S9, forming an interlayer dielectric layer 40 on a surface of the wafer.

[0098] S10, forming a contact hole 41 on the interlayer dielectric layer 40 to expose at least a portion of the second doped layer 26 located around the side well junctions 23.

[0099] S11, forming a metal silicide layer 50 at the contact hole 41.

[0100] S12, forming a metal conductive layer 61, a passivation layer 62, and a buffer protection layer 63 in sequence on the wafer, thinning the substrate 10, and forming an ohmic contact layer and a metal back plate 64 in sequence on a back surface of the substrate 10.

[0101] The structures of the device will be described in detail in combination with the steps of the method.

[0102] Figure 7 is a sectional view of the structure after step S1 in the method is performed Figure 8 a is a sectional view along line A-A in Figure 7 b is a sectional view along line B-B in Figure 8 Figure 5 Figure 8 Figure 5 ​​​In step S1, a substrate 10 having an epitaxial layer 20 is provided. The upper surface of the epitaxial layer 20 defines a main region 20a and a side screen region 20b that are parallel to each other, a trench region 20c located in the main region 20a and parallel to the side screen region 20b, and a bottom screen region 20d that intersects with the trench region 20c. P-type impurities are implanted into the bottom screen region 20d to form a bottom screen junction 22 in the epitaxial layer 20 by means of deposition. The bottom screen junction 22 is deposited on the upper surface of the epitaxial layer 20, and the deposition depth is greater than the trench depth.

[0103] In this process, a mask 70 is formed on the surface of the epitaxial layer 20. A mask opening 71, corresponding to the shape and position of the bottom screen region 20d, is formed on the mask 70 by photolithography. The bottom screen region 20d is aligned, and P-type impurities are implanted using an ion implantation process to form a bottom screen junction 22 in the epitaxial layer 20 via deposition. The mask 70 is then removed. The ion implantation process can be either channeling implantation or high-energy implantation.

[0104] When implanting P-type impurities (such as boron or aluminum ions), the ion beam bombards the entire surface of the epitaxial layer 20. However, ions can only penetrate and enter the underlying epitaxial layer 20 at the mask opening 71. In the area covered by the mask 70, ions are blocked. By precisely controlling the energy of the implanted ions, they can penetrate the surface of the epitaxial layer 20 and eventually stop below the predetermined location where the trench 27 is formed.

[0105] The materials of the substrate 10 and the epitaxial layer 20 include, but are not limited to, SiC. The doping types of the substrate 10 and the epitaxial layer 20 can be N-type or P-type. This embodiment uses N-type epitaxial layer 20 as an example for illustration. It is easy to understand that when the epitaxial layer 20 is P-type, all corresponding doping types need to be changed to the opposite type.

[0106] Figure 8 Is execution Figure 9 A sectional view of the structure after step S2, wherein Figure 7 a is along Figure 9 A cross-sectional view of line AA in the middle. Figure 5 b is along Figure 9 A cross-sectional view along the CC line. (Refer to...) Figure 5 In step S2, P-type impurities are injected into the side screen region 20b to form a side screen junction 23 in the epitaxial layer 20 in a longitudinally continuous manner. The side screen junction 23 extends continuously to the upper surface of the epitaxial layer 20, and the bottom of the side screen junction 23 is interleaved with the bottom screen junction 22 to form a grid.

[0107] Wherein, a mask is formed on the surface of the epitaxial layer 20, a mask opening corresponding to the shape and position of the side screen region 20b is formed on the mask by photoetching, P-type impurities are injected by ion implantation process to form the side screen junction 23 in the epitaxial layer 20, and the mask is removed.

[0108] Figure 9 is a sectional view along the C-C line in Figure 10 after step S3 is executed. Figure 7 Referring to Figure 5 , in step S3, P-type impurities are injected in alignment with the body region 20a to form a body layer 24 in the epitaxial layer 20 in a precipitated manner, the body layer 24 sinks to the upper surface of the epitaxial layer 20, and the lower surface of the body layer 24 is flush with the upper surface of the bottom screen junction 22.

[0109] Figure 10 is a sectional view along the C-C line in Figure 11 after step S4 is executed. Figure 7 Referring to Figure 5 , in step S4, N-type impurities are injected in alignment with the body region 20a to sequentially form a first doped layer 25 and a second doped layer 26, the lower surface of the first doped layer 25 is flush with the upper surface of the body layer 24, the lower surface of the second doped layer 26 is flush with the upper surface of the first doped layer 25, and the second doped layer 26 extends to the upper surface of the epitaxial layer 20, wherein the doping concentration of the first doped layer 25 is lower than the doping concentration of the second doped layer 26. Wherein, N-type impurities can be injected to the surface of the epitaxial layer 20 by ion implantation process or diffusion process, and finally an N+N-P type structure is formed.

[0110] Figure 11 is a sectional view of the structure after step S5 is executed. Figure 12 Wherein Figure 7 a is a sectional view along the A-A line in Figure 12 , Figure 5 b is a sectional view along the B-B line in Figure 12 , Figure 5 c is a sectional view along the C-C line in Figure 12 . Referring to Figure 5 , in step S5, a trench 27 is opened in the epitaxial layer 20 in alignment with the trench region 20c, wherein a circular arc is formed at the connection between the sidewall and the bottom of the trench 27, the bottom of the trench 27 is recessed from the bottom screen junction 22, and the trench 27 is located between the side screen junctions 23.

[0111] The bottom surface of the trench 27 can be a flat surface or an arc surface. The angle between the sidewall of the trench 27 and the trench 27 is 80-91°. Preferably, the angle between the sidewall of the trench 27 and the trench 27 is 86°. The connection part between the bottom surface of the trench 27 and the sidewall of the trench 27 can be a circular arc.

[0112] Figure 12 is a sectional view along the C-C line of the structure after step S6 of performing Figure 13 is performed. Figure 7 Figure 5 In step S6, the implanted N-type and P-type impurities are activated by a high-temperature annealing process.

[0113] In the previous steps, the P-type and N-type impurities are implanted into the lattice of the epitaxial layer 20 by ion implantation. At this time, most of these impurity atoms are in interstitial positions and do not replace lattice atoms, so they do not have electrical activity (i.e., they cannot effectively provide holes or electrons). This step provides energy to make the implanted impurity atoms migrate to the replacement position of the lattice by high-temperature annealing (high-temperature activation), so that they become electrically active and can change the conductivity type and conductivity of the semiconductor to form the required P region and N region.

[0114] Because the semiconductor surface may be decomposed, volatilized (for example, Si atoms sublimate), or become rough during high-temperature activation, a protective layer (Capping Layer) 80 is needed to be covered before activation to prevent the surface from being damaged at high temperature, and the protective layer 80 is removed after high-temperature activation is completed. The material of the protective layer 80 can be photoresist (PR), sputter carbon (Sputter C), aluminum nitride (AlN), etc. The temperature of high-temperature activation can be 1400-2100°C, and preferably can be 1700-1800°C.

[0115] Figure 13 is a sectional view along the C-C line of the structure after step S7 of performing Figure 14 is performed. Figure 7 Figure 5 In step S7, a polysilicon gate oxide (Gate Oxide, GOX) 31 is formed on the inner wall of the trench 27.

[0116] First, the surface of the wafer is oxidized at high temperature to form a sacrificial oxide (Sacrificial Oxide, SAC OX) on the inner wall of the trench 27 to eliminate the damage layer or contamination left on the surface of the semiconductor structure due to previous processes (such as trench etching, surface residues or damage after ion implantation), and the sacrificial oxide is removed. Here, the term "wafer" refers to the entire semiconductor structure formed after the previous steps are performed.​​

[0117] Furthermore, a gate oxide layer 31 is formed on the inner wall of the trench 27 by processes such as thermal oxidation or chemical vapor deposition (CVD).

[0118] Figure 14 Is execution Figure 15 The structure after step S8 Figure 7 A cross-sectional view along the CC line. (Refer to...) Figure 5 In step S8, polysilicon is filled into the trench 27 to form a polysilicon gate 30. Specifically, polysilicon is deposited on the surface of the semiconductor structure to fill the trench 27, and the polysilicon outside the trench 27 is removed by polyetch back.

[0119] Figure 15 Is execution Figure 16 The structure after step S9 Figure 7 A cross-sectional view along the CC line. (Refer to...) Figure 5 In step S9, an interlayer dielectric layer 40 is formed on the surface of the wafer. The interlayer dielectric layer 40 covers the polysilicon gate 30, the second doped layer 26, and the side junction 23. The material of the interlayer dielectric layer 40 may be silicon dioxide (SiO2) and / or silicon nitride (SiN).

[0120] Figure 16 Is execution Figure 17 The structure after step S10 along Figure 7 A cross-sectional view along the CC line. (Refer to...) Figure 5 In step S10, a contact hole (CONT) 41 is formed on the interlayer dielectric layer 40 to expose at least a portion of the second doped layer 26 located around the side-screen junction 23.

[0121] In this process, a mask 70 is formed on the surface of the interlayer dielectric layer 40. A mask opening 71 corresponding to the position of the side-mount junction 23 is formed on the mask 70 by photolithography. The interlayer dielectric layer 40 located at the mask opening is etched away. After removing the interlayer dielectric layer 40, a portion of the side-mount junction 23 and the second doped layer 26 located at that point is etched to form a contact hole 41. The mask 70 is then removed. The etching depth of the side-mount junction 23 and the second doped layer 26 can be 30-40 angstroms.

[0122] Figure 17 Is execution Figure 18 The structure after step 11 Figure 7 A cross-sectional view along the CC line. (Reference) Figure 5In step S11, a metal silicide layer 50 is formed at the contact hole 41. In this step, a metal layer (e.g. Ti, Ni, Co) is deposited on the surface of the wafer (including the side junction 23, the second doped layer 26 and the surrounding interlayer dielectric layer 40 surface exposed at the contact hole 41); the deposited metal reacts with the silicon of the side junction 23 and the second doped layer 26 at high temperature to form the metal silicide layer 50, while the deposited metal does not react with the interlayer dielectric layer 40; finally, the deposited metal on the interlayer dielectric layer 40 which does not react is removed.

[0123] Figure 18 is a cross-sectional view of a trench-type silicon carbide MOSFET device according to an embodiment of the present application, Figure 6 a is a cross-sectional view along line A-A in Figure 6 b is a cross-sectional view along line B-B in Figure 5 c is a cross-sectional view along line C-C in Figure 6 Figure 5 Figure 6

[0124] Referring to Figure 5 In step S12, a metal conductive layer 61, a passivation layer 62 and a buffer protection layer 63 are sequentially formed on the wafer, the substrate 10 is thinned, and an ohmic contact layer and a metal back plate 64 are sequentially formed on the back surface of the substrate 10 to form the trench-type silicon carbide MOSFET device.

[0125] The metal conductive layer 61 is located on the metal silicide layer 50 and the interlayer dielectric layer 40, and constitutes the source electrode of the trench-type silicon carbide MOSFET device. The material of the metal conductive layer 61 can be Al, Cu, Al / Cu alloy (e.g. AlSi alloy, AlCu alloy and AlSiCu alloy) or a stacked combination of the above materials.

[0126] The passivation layer 62 is located on the metal conductive layer 61. The material of the passivation layer 62 can be silicon dioxide (SiO2), silicon nitride (SiN) or a combination thereof. The thickness of the passivation layer 62 can be 0.1-20um.

[0127] The buffer protection layer 63 is located on the passivation layer 62. The material of the buffer protection layer 63 includes but is not limited to polyimide (PI), polyamide, polybenzoxazole (PBO) and a combination thereof. The thickness of the buffer protection layer 63 can be 1-50um, and preferably can be 10-15um.

[0128] ​​​The thickness of the substrate 10 after thinning is 80-250um, preferably 150-200um.

[0129] The metal back plate 64 is connected with the substrate through an ohmic contact layer, constituting the drain of the trench type silicon carbide MOSFET device. The material of the metal back plate 64 can be Ti, Ni, Ag, Pd, Au and alloys or combinations thereof.

[0130] The implementation principle of the embodiment 2 of the present application is: precisely defining the bottom screen area, the side screen area and the trench area, and processing in a specific order (first forming the interlaced deep bottom screen combined with the side screen junction grid, and then opening the trench in it), so as to reliably manufacture the trench type silicon carbide MOSFET with the three-dimensional grid shielding structure, ensuring the accurate relative position of the shielding structure and the trench, and realizing the high reliability advantage brought by the device structure.

[0131] Embodiment 3

[0132] Figure 6 is a flowchart of the construction method of the trench type silicon carbide MOSFET device of the embodiment 3 of the present application. Referring to Figure 19 , the difference between the present embodiment and the embodiment 2 is the step S1 and the step S2.

[0133] Figure 19 is a sectional view of the structure after the step S1 in Figure 20 , wherein Figure 19 a is a sectional view along the A-A line of Figure 20 , Figure 5 b is a sectional view along the B-B line of Figure 20 , Figure 5 c is a sectional view along the D-D line of Figure 20 . Referring to Figure 5 , in the step S1, P-type impurities are injected into the bottom screen area 20d in alignment, so as to form the bottom screen junction 22 in the epitaxial layer 20, while P-type impurities are injected into the side screen area 20b within the first depth range 23a in alignment.

[0134] Figure 20 is a sectional view of the structure after the step S2 in Figure 21 , wherein Figure 19 a is a sectional view along the A-A line of Figure 21 , Figure 5 b is a sectional view along the C-C line of Figure 21 . Referring to Figure 5 , in the step S2, P-type impurities are injected into the side screen area 20b at a depth outside the first depth range 23a, so as to form the side screen junction 23 in the epitaxial layer 20.

[0135] In this embodiment, step S2 omits the process of implanting P-type impurities at a depth within the first depth range 23a, thus simplifying the process. The remaining steps and the final device formation in this embodiment are the same as in Embodiment 2, and will not be repeated here.

[0136] The implementation principle of Example 3 is as follows: By combining the bottom screen junction implantation with the shallow implantation of the side screen junction, and by using a mask to complete partial doping of multiple regions in the same step, the number of ion implantations can be effectively reduced, thereby simplifying the manufacturing process, reducing process complexity and production costs, and improving production efficiency.

[0137] Example 4

[0138] Figure 21 This is a schematic flowchart illustrating the construction method of the trench-type silicon carbide MOSFET device according to Embodiment 4 of this application. (Refer to...) Figure 22 The difference between this embodiment and embodiment 2 lies in steps S1 and S2.

[0139] Figure 22 It is execution Figure 23 A sectional view of the structure after step S1, wherein Figure 22 a is along Figure 23 A cross-sectional view of line AA. Figure 5 b is along Figure 23 A cross-sectional view of the BB line. Figure 5 c is along Figure 23 A cross-sectional view of line DD of a. (Refer to...) Figure 23 In step S1, P-type impurities are injected into the bottom screen region 20d to form a bottom screen junction 22 in the epitaxial layer 20. At the same time, P-type impurities are injected into the side screen region 20b within a second depth range 23b, where the depth of the second depth range 23b is greater than the depth of the first depth range 23a.

[0140] Figure 23 It is execution Figure 24 A sectional view of the structure after step S2. Figure 22 a is along Figure 24 A cross-sectional view of line AA. Figure 5 b is along Figure 24 A cross-sectional view along the CC line. (Refer to...) Figure 5 Figure 24 In step S2, the side screen region 20b is aligned, and P-type impurities are injected at a depth other than the second depth range 23b to form a side screen junction 23 in the epitaxial layer 20.

[0141] In this embodiment, step S2 omits the process of implanting P-type impurities at a depth of 23b in the second depth range, thus simplifying the process. The remaining steps and the final device formation in this embodiment are the same as in Embodiment 2, and will not be repeated here.

[0142] The implementation principle of the embodiment 4 is that the bottom screen junction injection is combined with the deep injection of the side screen junction, and the partial doping of multiple regions is completed simultaneously by using a mask in the same step, so that the number of ion implantation is effectively reduced, the manufacturing process is simplified, the process complexity and production cost are reduced, and the production efficiency is improved.

[0143] The above are preferred embodiments of the present application, and are not intended to limit the protection scope of the present application, so that: any equivalent changes made according to the structure, shape, principle of the present application should be covered within the protection scope of the present application.

Claims

1. A trench-type silicon carbide MOSFET device, characterized in that, include: A substrate (10) having an epitaxial layer (20) comprising interleaved bottom screen junctions (22) and side screen junctions (23), wherein the bottom screen junction (22) is recessed into the upper surface of the epitaxial layer (20), and the recess depth of the bottom screen junction (22) from the epitaxial layer (20) is greater than the depth of the trench (27); the side screen junctions (23) are continuously formed in the epitaxial layer (20). The side screen junction (23) extends to the upper surface of the epitaxial layer (20), and the bottom of the side screen junction (23) is interlocked with the bottom screen junction (22) to form an interlocked grid; the epitaxial layer (20) has a groove (27), the sidewall of the groove (27) and the bottom are connected to form an arc shape, the bottom of the groove (27) is recessed in the bottom screen junction (22), and the groove (27) is located between the side screen junctions (23); A polysilicon gate (30) is disposed within the trench (27).

2. The trench-type silicon carbide MOSFET device according to claim 1, characterized in that, The substrate (10) and the epitaxial layer (20) have a first type of impurity, and the bottom screen junction (22), the side screen junction (23) and a second type of impurity with the opposite polarity to the first type of impurity.

3. The trench-type silicon carbide MOSFET device according to claim 2, characterized in that, Also includes: A body layer (24) is located within the epitaxial layer (20), and the body layer (24) has a second type of impurity; The epitaxial layer (21) is located below the body layer (24) and the bottom screen junction (22).

4. The trench-type silicon carbide MOSFET device according to claim 3, characterized in that, It also includes a first doped layer (25) located on the bulk layer (24), the first doped layer (25) having a first type of impurity; A second doped layer (26) is located on the first doped layer (25), wherein the doping concentration of the second doped layer (26) is higher than that of the first doped layer (25); The body layer (24), the first doped layer (25) and the second doped layer (26) fill the gap between the side screen junction (23) and the polysilicon gate (30).

5. The trench-type silicon carbide MOSFET device according to claim 4, characterized in that, Also includes: An interlayer dielectric layer (40) is located above the polysilicon gate (30), the second doped layer (26) and the side junction (23), and the interlayer dielectric layer (40) has a contact hole (41) that exposes a portion of the surface of the second doped layer (26).

6. The trench-type silicon carbide MOSFET device according to claim 5, characterized in that, Also includes: A metal silicide layer (50) is disposed on the exposed surface of the second doped layer (26) within the contact hole (41).

7. The trench-type silicon carbide MOSFET device according to claim 6, characterized in that, Also includes: A metal conductive layer (61) located on the interlayer dielectric layer (40) and the metal silicide layer (50); and a passivation layer (62) and a buffer protection layer (63) sequentially disposed on the metal conductive layer (61).

8. The trench-type silicon carbide MOSFET device according to claim 1, characterized in that, A gate oxide layer (31) is disposed between the polysilicon gate (30) and the inner wall of the trench (27).

9. The trench-type silicon carbide MOSFET device according to claim 1, characterized in that, The angle between the sidewall of the groove (27) and the bottom of the groove (27) is 80-91°.

10. The trench-type silicon carbide MOSFET device according to claim 1, characterized in that, Also includes: Metal backplate (64) connected to the back side of the substrate (10) via an ohmic contact layer.

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