Semiconductor device

Abstract

The embodiment of the utility model relates to a semiconductor device. The semiconductor device comprises a first substrate which is provided with a first front side and a first back side opposite to the first front side. The semiconductor device includes a first source / drain S / D member over the first front side. The semiconductor device includes a first barrier gate and a first plunger gate between first S / D members, wherein the first plunger gate defines a first qubit region. The semiconductor device includes a second substrate having a second front side and a second back side opposite the second front side. The semiconductor device includes a second S / D member over the second front side. The semiconductor device includes a second barrier gate and a second plunger gate between the second S / D members, wherein the second plunger gate defines a second qubit region aligned with the first qubit region along the first direction. The semiconductor device includes a doped well extending along a first direction between a first backside and a second backside.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices and methods of manufacturing the same. BACKGROUND

[0002] Quantum operations relate to the field of research associated with computing systems that use quantum mechanical phenomena to manipulate data. Several milestones have been achieved on the roadmap to building a scalable, silicon-based quantum computer. Quantum operations can involve initializing states of N qubits, creating controlled entanglements among them, allowing these states to evolve, and reading out the states of the qubits after evolution. A qubit is a system that has two degenerate (i.e., with equal energy) quantum states, with a non-zero probability of being found in either state. Thus, N qubits can define an initial state that is a combination of 2N classical states. While prior art relating to silicon-based devices configured to perform quantum operations has generally been adequate, it has not been entirely satisfactory in all respects. N SUMMARY Embodiments of the present application relate to semiconductor devices and methods of manufacturing the same.

[0003] According to embodiments of the present application, a semiconductor device includes a first substrate having a first front side and a first back side separated along a first direction; first source / drain members over the first front side; a first barrier gate between the first source / drain members over the first front side; a first plunger gate adjacent to the first barrier gate along a second direction perpendicular to the first direction, the first plunger gate defining a first qubit region over the first front side; a second substrate having a second front side and a second back side separated along the first direction; second source / drain members over the second front side; a second barrier gate between the second source / drain members over the second front side; a second plunger gate adjacent to the second barrier gate, the second plunger gate defining a second qubit region over the second front side, the second qubit region aligned with the first qubit region along the first direction; and a doped well extending between the first back side and the second back side along the first direction.

[0004] According to embodiments of the present application, a semiconductor device includes: a first substrate having a first side and a second side opposite the first side; a second substrate having a third side and a fourth side opposite the third side; a first doped well merging the second side and the fourth side; a first channel region extending along a first direction over the first side; first plug gate structures and first barrier gate structures alternately arranged in the first channel region along the first direction, the first plug gate structures each defining a first qubit region; a second channel region extending along the first direction over the third side; second plug gate structures and second barrier gate structures alternately arranged in the second channel region along the first direction, the second plug gate structures each defining a second qubit region; and a second doped well disposed in the first substrate and adjacent to one of the first plug gate structures along the first direction, the second doped well coupled to the first doped well.

[0005] According to embodiments of the present application, a method includes: forming first source / drain members over a front side of a first substrate, the first substrate having a back side opposite the front side; forming first plug gates between the first source / drain members, the first plug gates each defining a first qubit region over the front side of the first substrate; forming first barrier gates each interposed between two adjacent first plug gates; forming a first doped well over the back side of the first substrate; forming second source / drain members over a front side of a second substrate, the second substrate having a back side opposite the front side; forming second plug gates between the second source / drain members, the second plug gates each defining a second qubit region over the front side of the second substrate; forming second barrier gates each interposed between two adjacent second plug gates; forming a second doped well over the back side of the second substrate; and merging the first doped well with the second doped well, thereby coupling the first substrate to the second substrate. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a top view of an example semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 2A is a top view of an example semiconductor device according to some embodiments of the present disclosure. Figure 1 is a cross-sectional view of the example semiconductor device of

[0009] Figure 2B is an example semiconductor device according to some embodiments of the present disclosure Figure 1 is a cross-sectional view of an example semiconductor device of

[0010] Figure 2C is an example semiconductor device according to some embodiments of the present disclosure Figure 1 is a cross-sectional view of an example semiconductor device of

[0011] Figure 2D is an example semiconductor device according to some embodiments of the present disclosure Figure 1 is a cross-sectional view of an example semiconductor device of

[0012] Figure 2E is an example semiconductor device according to some embodiments of the present disclosure Figure 1 is a cross-sectional view of an example semiconductor device of

[0013] Figure 3A and Figure 3B together illustrate an example method for fabricating an example semiconductor device according to some embodiments of the present disclosure Figures 1 to 2E

[0014] Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12 and Figure 13 are cross-sectional views of portions of an example semiconductor device of Figure 1 along line A-A' of Figure 3A and Figure 3B at intermediate stages of the method of

[0015] Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B are cross-sectional views of portions of an example semiconductor device of Figure 1 along line B-B' of Figure 3A and Figure 3B at intermediate stages of the method of

[0016] Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C ,​Figure 9C , Figure 10C and Figure 11C It is according to some embodiments of this disclosure along Figure 1 The C-C' example of a semiconductor device in Figure 3A and Figure 3B A cross-sectional view of the intermediate stage of the method.

[0017] Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D , Figure 9D , Figure 10D and Figure 11D It is according to some embodiments of this disclosure along Figure 1 The part of the D-D' example semiconductor device in Figure 3A and Figure 3B A cross-sectional view of the intermediate stage of the method.

[0018] Figure 4E and Figure 11E It is according to some embodiments of this disclosure along Figure 1 The example of line E-E' in the semiconductor device is part of Figure 3A and Figure 3B A cross-sectional view of the intermediate stage of the method. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples of various components for implementing the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, embodiments may include a first component forming above or on a second component in which the first and second components are in direct contact, and embodiments may also include additional components formed between the first and second components such that the first and second components are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “above,” and the like are used herein to describe the relationship between one element or component and another element or component as illustrated in the figures. Spatial relative terms are intended to cover different orientations of the apparatus in use or operation other than those depicted in the figures. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0021] As used herein, "about," "approximately," "near," or "substantially" shall generally mean within 20% or within 10% or within 5% of a given value or range. Numerical quantities given herein are approximate, meaning that the term "about" "approximately," "near," or "substantially" can be inferred if not expressly stated. One of ordinary skill in the art will appreciate that dimensions can vary according to different technology nodes. One of ordinary skill in the art will recognize that dimensions depend on specific device type, technology generation, minimum feature size, and the like. Thus, the stated terms are intended to be interpreted in view of the technology being assessed.

[0022] Embodiments of the present disclosure provide a semiconductor qubit device having two semiconductor substrates coupled in a back-to-back configuration (i.e., a double-sided configuration), where a front side of each semiconductor substrate includes an array of quantum dot qubit regions (or qubit regions) extending in a lateral direction. The qubits are configured for controlling and reading out the spin of a single carrier (electron or hole) in the semiconductor substrate. Each of the qubit regions is defined in a channel region of the semiconductor substrate and is traversed by a plunger gate placed adjacent to a barrier gate. The semiconductor qubit device further includes a doped well separating the back sides of the semiconductor substrates. By applying a voltage to the doped well, a potential barrier between the array of quantum dot qubit regions along the vertical direction increases, thereby providing improved electrostatic control and confinement between the carriers (electrons or holes) along the vertical direction. In some embodiments, transistors formed in the semiconductor qubit device can be implemented as planar field effect transistors (FETs), multi-gate transistors, FinFETs, nanosheet FETs, or surround gate FETs.

[0023] Figure 1 is a top view of the device 10 according to some embodiments of the present disclosure, Figure 2A is Figure 1 is a cross-sectional view of the device 10 of Figure 2B is Figure 1 is a cross-sectional view of the device 10 of Figure 2C is Figure 1 is a cross-sectional view of the device 10 of Figure 2D is Figure 1 is a cross-sectional view of the device 10 of Figure 2E is Figure 1 is a cross-sectional view of the device 10 of Figures 2A to 2E Referring to

[0024] The front side of each of the top die 100 and the bottom die 200 (e.g., the front side of the substrate 102 and the front side of the substrate 202) includes a two-dimensional (e.g., along the XY plane as Figure 1 The XY plane depicted in the middle, each quantum dot defines a qubit ("qubit") region in a channel region of a FET. Each qubit region is defined by a portion of the channel region that is traversed by a plunger gate structure (e.g., the plunger gate structure 140) and is between two adjacent barrier gate structures (e.g., the barrier gate structure 150). In this embodiment, confinement of carriers (e.g., electrons) is achieved along both the lateral direction (e.g., the X-axis) and the vertical direction (e.g., the Z-axis) through physical boundaries and electrostatic control, resulting in improved entanglement between laterally adjacent and vertically adjacent quantum dots. Collectively, coupling the top die 100 to the bottom die 200 in a back-to-back configuration allows parallel quantum dot arrays to be entangled along an additional (i.e., vertical) direction. It should be understood that the number of each type of component (e.g., active regions, gate structures, contacts, etc.) in the device 10 depicted in this disclosure is for illustrative purposes only and, as such, is not intended to limit the structure of the device 10.

[0025] Referring to Figures 1 to 2E In general, the top die 100 includes a substrate 102 having a front side 102a and a back side 102b opposite the front side 102a along the Z-axis. The top die 100 at the front side 102a includes a plurality of active regions 104a-c (collectively, active regions 104) and an isolation region 106 surrounding a bottom of each active region 104. In some embodiments, the active regions 104 are configured as three-dimensional fin structures that extend vertically from the substrate 102 along the Z-axis and laterally in a longitudinal direction along the X-axis. As such, the resulting FETs formed by the active regions 104a-c can be referred to as FinFETs. Alternatively, the active regions 104a-c can be configured as planar structures that extend above the substrate 102 in the XY plane, and the resulting FETs formed by the active regions 104a-c can be referred to as planar FETs. In this disclosure, the active regions 104a-c are depicted as fin structures and are referred to hereinafter as fins 104a-c. Referring to Figure 1 The fins 104a-c extend longitudinally along the X-axis and are spaced apart from one another along the Y-axis. In this embodiment, the top die 100 at the back side 102b includes a doped well (e.g., a second doped well 170 as discussed in detail below) embedded therein (or otherwise formed thereover).

[0026] The substrate 102 includes a semiconductor substrate (or semiconductor layer), such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which can be doped (e.g., with P-type or N-type dopants) or undoped. The substrate 102 can be a wafer, such as a silicon wafer. In general, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as a multilayer or graded substrate, can also be used. In some embodiments, the semiconductor material of the substrate 102 can include silicon, germanium, compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. In some embodiments, the substrate 102 includes a p-type silicon substrate (p-substrate). For example, p-type dopants are introduced into the substrate 102 to form the p-substrate.

[0027] In some embodiments, the isolation regions 106 include shallow trench isolation (STI) members having recessed top surfaces, such that the upper portions of the fins 104 protrude between adjacent portions of the isolation regions 106. The isolation regions 106 can include oxide (e.g., silicon oxide (SiO and / or SiO2)), nitride, low-k (e.g., having a dielectric constant less than that of silicon oxide, approximately 3.9) dielectric materials (e.g., phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.), the like, or combinations thereof.

[0028] Referring to Figure 1 , Figure 2A and Figure 2EThe substrate 102 at the front side 102a includes a plurality of first doped wells 108a-c (collectively, first doped wells 108), each first doped well 108a-c embedded in the substrate 102 (e.g., under the isolation regions 106) and disposed along the X-axis adjacent to a respective fin (e.g., adjacent to one of the source / drain members disposed over the fin) 104a-c. The first doped wells 108 include a top surface (over the front side 102a) coupled to (e.g., in physical or electrical contact with) the doped well contact 164. The first doped wells 108 further include a bottom surface (facing the back side 102b) coupled to the second doped well 170 disposed on the back side 102b of the substrate 102. As such, by applying a voltage to the first doped wells 108 through the doped well contact 164, the electric field of the second doped well 170 can be adjusted to create or otherwise affect a potential barrier between a quantum dot in the top die 100 and a corresponding quantum dot in the bottom die 200 along the Z-axis, and thus electrostatic control of the quantum dots.

[0029] The first doped wells 108 include a suitable dopant determined based on a type of carrier (e.g., electron or hole) present in the qubit region 134 provided in the top die 100. Further, the first doped wells 108 and the second doped well 170 include a dopant of the same conductivity type. For embodiments in which the carrier includes an electron, both the first doped wells 108 and the second doped well 170 include a p-type dopant to provide a potential barrier between two electrons of a parallel quantum dot array along the Z-axis. In this regard, both the first doped wells 108 and the second doped well 170 are p-wells. Example p-type dopants include boron (B), gallium (Ga), indium (In), the like, or combinations thereof. Conversely, for embodiments in which the carrier includes a hole, both the first doped wells 108 and the second doped well 170 include an n-type dopant. Example n-type dopants include phosphorus (P), arsenic (As), the like, or combinations thereof. In some embodiments, the dopant concentration of the first doped wells 108 is substantially the same as the dopant concentration of the second doped well 170. In some examples, the dopant concentration of the first doped wells 108 and the second doped well 170 can each be about 1 x 1018cm-3to about 1 x 1020cm-3. 18 cm -1 to about 1 x 1020cm-3. 19 cm -1 .

[0030] The doped well contact 164 can include a metal fill layer containing any suitable metal, such as tungsten (W), copper (Cu), ruthenium (Ru), aluminum (Al), gold (Au), cobalt (Co), the like, or combinations thereof. In some embodiments, the doped well contact 164 further includes a barrier layer (not depicted) placed between the first doped well 108 and the metal fill layer. The barrier layer can include any suitable material, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), the like, or combinations thereof.

[0031] Referring to Figure 1 , Figure 2A and Figure 2B Each of the fins 104a-c includes a pair of source / drain (S / D) members (or S / D regions) 130a-c (collectively, S / D members 103), respectively, with S / D member 130a placed over (or in) fin 104a, S / D member 130b placed over (or in) fin 104b, and S / D member 130c placed over (or in) fin 104c. At least a bottom portion of each S / D member 130 can be embedded in the corresponding fin 104, while a top portion of the S / D member 130 can protrude from a top surface of the fin 104, as depicted herein. For a planar FET, the top portion of the S / D member 130 is substantially coplanar with the top surface of the substrate 102. A portion of each of the fins 104a-c interposed between each pair of S / D members 130a-c along the X-axis is defined as a channel region 132a-c (collectively, channel regions 132), respectively. In the present embodiment, each channel region 132 defines a qubit region of the device 10, within which a quantum dot is provided.

[0032] In some embodiments, the substrate 102 and the channel regions 132 are both of a first conductivity type, and the S / D members 130 are of a second conductivity type different from the first conductivity type. In some embodiments, the substrate 102 is a p-type silicon substrate (p-substrate), the channel regions 132 are p-type, and the S / D members 130 are n-type, resulting in an n-type FET. In some embodiments, the substrate 102 and the channel regions 132 are both n-type, and the S / D members 130 are p-type, resulting in a p-type FET.

[0033] In some embodiments, the top die 100 includes a plurality of S / D contacts 160 each coupled to the S / D member 130. The S / D contacts 160 can each include a metal fill layer having a composition similar to that of the doped well contacts 164 described above. In some embodiments, each S / D contact 160 further includes a barrier layer (not depicted) disposed between the S / D member 130 and the metal fill layer, where the barrier layer can have a composition similar to that of the barrier layer of the doped well contacts 164. In some embodiments, the top die 100 further includes a silicide layer (not depicted) disposed between each S / D contact 160 and the S / D member 130.

[0034] Referring to Figure 1 , Figure 2A and Figure 2C , the top die 100 includes a plurality of plunger gate structures 140a, 140b, 140c, and 140d (collectively, plunger gate structures 140) disposed over the channel region 132 of each of the fins 104a-c. The plunger gate structures (or plunger gates) 140 extend longitudinally along the Y-axis (i.e., perpendicular to the fins 104) and are spaced apart from one another along the X-axis. Each plunger gate structure 140 includes a plunger gate dielectric layer 142 and a plunger gate electrode 144 disposed over the plunger gate dielectric layer 142, where the plunger gate dielectric layer 142 traverses a portion of the channel region 132. In the depicted embodiment, the two outermost plunger gate structures 140 along the X-axis are each separated from an adjacent S / D member 130 by a corresponding gate spacer 120. In some embodiments, an interface layer (not depicted) can be formed between the plunger gate dielectric layer 142 and the channel region 132 and can include an oxide, such as silicon oxide.

[0035] The plunger gate dielectric layer 142 can include any suitable dielectric material, such as silicon oxide, silicon nitride, a high-k dielectric material (i.e., having a dielectric constant greater than that of silicon oxide, on the order of 3.9), the like, or combinations thereof. The high-k dielectric material can include an oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, the like, or combinations thereof. The plunger gate electrode 144 can include any suitable metal, such as tungsten (W), copper (Cu), ruthenium (Ru), aluminum (Al), gold (Au), cobalt (Co), the like, or combinations thereof.

[0036] Referring to Figure 2A , the top die 100 further includes a gate spacer 120 disposed along the sidewall of each plunger gate structure 140. The gate spacer 120 can include one or more layers of a suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, the low-k materials described above, the like, or combinations thereof.

[0037] ReferringFigure 1 、 Figure 2A and Figure 2D The top die 100 further includes a plurality of barrier gate structures 150a, 150b, and 150c (collectively, barrier gate structures 150) each interposed between two adjacent plunger gate structures 140 along the X-axis. In this regard, each qubit region 134 (e.g., qubit regions 134a, 134b, 134c, and 134d corresponding to plunger gate structures 140a, 140b, 140c, and 140d, respectively) is defined as a portion of the channel region 132 between two adjacent barrier gate structures (or barrier gates) 150, i.e., a portion of the channel region 132 traversed by each plunger gate structure 140. In this embodiment, each of the carriers (e.g., electrons or holes) 180a, 180b, 180c, and 180d (collectively, carriers 180) is confined to the qubit region 134 of the corresponding quantum dot. In some embodiments, by adjusting the voltage (i.e., electric potential) applied to two adjacent barrier gate structures 150 along the X-axis, each qubit region 134 interposed between barrier gate structures 150 only allows a single carrier (e.g., electron or hole) to pass from an entrance of the qubit region 134 (i.e., a portion of the channel region 132 traversed by a first of the barrier gate structures 150) to an exit of the qubit region 134 (i.e., a portion of the channel region 132 traversed by a second of the barrier gate structures 150) before allowing another carrier to enter into the qubit region 134.

[0038] In some embodiments, the top die 100 includes a dielectric layer 124 separating each barrier gate structure 150 from the channel region 132 and the adjacent gate spacers 120. The dielectric layer 124 can include any suitable dielectric material, such as an oxide (e.g., silicon oxide, metal oxide, etc.), a nitride (e.g., silicon nitride), a silicide (e.g., metal silicide), the like, or a combination thereof. In some embodiments, the dielectric layer 124 has a composition different from that of the gate spacers 120. In this embodiment, a top surface of the dielectric layer 124, a top surface of the barrier gate structures 150 above the dielectric layer 124, and a top surface of the adjacent plunger gate structures 140 are formed coplanar or substantially coplanar.

[0039] Referring to Figure 2A 、 Figure 2B 、 Figure 2D and Figure 2EThe top die 100 further includes an interlayer dielectric (ILD) layer 138 disposed over the S / D members 130, where the ILD layer 138 provides isolation between contact members (e.g., between one of the S / D contacts 160 and the doped well contact 164) and between one of the contact members and an adjacent gate structure (e.g., between one of the S / D contacts 160 and one of the outer plunger gate structures 140). The ILD layer 138 can include an oxide (e.g., silicon oxide (SiO and / or SiO2)), a nitride, the low-k dielectric materials described above, the like, or combinations thereof. In some embodiments, the ILD layer 138 includes silicon oxide. In some embodiments, to achieve etch selectivity, the ILD layer 138 and the dielectric layer 124 have different compositions. It should be noted that the ILD layer 138 is omitted in FIGS. 1A-1C for purposes of illustrating various device members of the device 10. Figure 1

[0040] Although not depicted herein, the device 10 can further include additional contact members (e.g., gate contacts coupled to the plunger gate structures 140 and the barrier gate structures 150) and a plurality of interconnect structures coupled to the contact members over the front side 102a. The interconnect structures can include horizontal interconnect structures (e.g., conductive lines) extending laterally over the substrate 102 and vertical interconnect structures (e.g., vias) configured to couple the horizontal interconnect structures along a vertical direction (e.g., the Z-axis). The interconnect structures can be disposed in various intermetal dielectric (IMD) layers stacked along the vertical direction to form a front side multilayer interconnect (MLI) structure (alternatively referred to as a back end of line or BEOL structure of the top die 100) coupled to the front end of line (FEOL) members as depicted herein through various contact members (alternatively referred to as a middle end of line or MEOL structure of the top die 100). The MLI structure can be further coupled to a front side power rail configured to provide a voltage to the FEOL members (e.g., the plunger gate structures 140, the barrier gate structures 150, the S / D members 130, the first doped well 108, etc.). In some embodiments, the interconnect structures can each have a composition similar to that of the doped well contact 164, and the IMD layers can each have a composition identical to that of the ILD layer 138.

[0041] ​Furthermore, in some embodiments, the top die 100 includes one or more through-substrate vias (or through-silicon vias; TSVs) 174 extending through the substrate 102, which includes the second doped well 170 at the backside 102b. In the depicted embodiment, the TSVs 174 are formed adjacent to the fins (i.e., active regions) 104 and / or the first doped well 108 along the X-direction. In the present embodiment, each TSV 174 is configured to couple a conductive member (e.g., a BEOL structure) placed over the frontside 102a of the top die 100 to a conductive member placed over the frontside 202a of the bottom die 200 through a TSV (e.g., TSV 274) formed in a substrate (e.g., substrate 202) of the bottom die 200. Each TSV 174 can include any suitable conductive material, and can have a composition similar to that of the doped well contact 164.

[0042] Still referring to Figures 1 to 2E , the bottom die 200 includes members corresponding to those of the top die 100. For example, the bottom die 200 includes a substrate 202. The substrate 202 includes a frontside 202a and a backside 202b opposite the frontside 202a along the Z-axis, where the backside 202b includes a third doped well 270 embedded therein (or otherwise formed thereover). The bottom die 200 includes a plurality of fins 204a-c (collectively, fins 204) over the frontside 202a of the substrate 202 and an isolation region 206 surrounding the bottoms of the fins 204.

[0043] Each of the fins 204a-c includes a pair of S / D members (or S / D regions) 230a, 230b, and 230c (collectively, S / D members 230) placed thereover, respectively. A portion of each of the fins 204a-c interposed between each pair of S / D members 230a-c along the X-axis is defined as a channel region 232a-c (collectively, channel regions 232), respectively. In some embodiments, the substrate 202 and the channel regions 232 are both of a first conductivity type, and the S / D members 230 are of a second conductivity type different from the first conductivity type. The bottom die 200 further includes a plurality of S / D contacts 260 each coupled to the S / D members 230.

[0044] Above each channel region 232, the bottom die 200 includes a plurality of plunger gate structures 240a, 240b, 240c, and 240d (collectively, plunger gate structures 240). Each plunger gate structure 240 includes a plunger gate dielectric layer 242 and a plunger gate electrode 244 disposed above the plunger gate dielectric layer 242, where the plunger gate dielectric layer 242 traverses a portion of the channel region 232. The bottom die 200 further includes a gate spacer 220 disposed along a sidewall of each plunger gate structure 240. In the depicted embodiment, the two outermost plunger gate structures 240 are each separated from an adjacent S / D member 230 by a corresponding gate spacer 220.

[0045] The bottom die 200 further includes a plurality of barrier gate structures 250a, 250b, and 250c (collectively, barrier gate structures 250) each interposed between two adjacent plunger gate structures 240 along the X-axis. In this regard, a qubit region 234 (e.g., qubit regions 234a, 234b, 234c, and 234d corresponding to plunger gate structures 240a, 240b, 240c, and 240d, respectively) is defined as a portion of the channel region 232 between two adjacent barrier gate structures 250, i.e., a portion of the channel region 232 traversed by each plunger gate structure 240. In the present embodiment, each of a plurality of carriers (e.g., electrons or holes) 280a, 280b, 280c, and 280d (collectively, carriers 280) is confined to a qubit region 234 of a corresponding quantum dot of the channel region 232.

[0046] In the present embodiment, the bottom die 200 further includes a dielectric layer 224 separating each barrier gate structure 250 from the channel region 232 and adjacent gate spacers 220, and an ILD layer 238 disposed above the S / D members 230 to isolate contact members (e.g., S / D contacts 260) from any adjacent conductive members (e.g., plunger gate structures 240). Similar to the top die 100, the bottom die 200 can further include additional contact members (e.g., gate contacts coupled to the plunger gate structures 240 and the barrier gate structures 250) as part of the MEOL structure, and a plurality of interconnect structures coupled to the contact members above the front side 202a as part of the BEOL structure of the bottom die 200. Still further, the bottom die 200 includes one or more TSVs 274 extending through the substrate 202 (including the third doped well 270), where each TSV 274 is configured to couple a conductive member disposed above the front side 202a of the bottom die 200 (e.g., the BEOL structure of the bottom die 200) to a conductive member disposed above the front side 102a of the top die 100.

[0047] The bottom die 200 at the back side 202b includes a third doped well 270 that is directly coupled to the second doped well 170, e.g., by a wafer bonding mechanism, to form a common doped well DW sandwiched between the front side 102a and the front side 202a. In this regard, both the second doped well 170 and the third doped well 270 are coupled to the first doped well 108 and thus can be controlled by a voltage applied to the first doped well 108. In the present embodiment, the first doped well 108, the second doped well 170, and the third doped well 270 all include dopants of the same conductivity type. Further, the concentration of the dopants in the second doped well 170 and the third doped well 270 can be substantially the same, such that the common doped well DW has a substantially uniform composition across its thickness T along the Z-axis. If the carriers include electrons, then both the third doped well 270 and the second doped well 170 include p-type dopants (i.e., both are p-wells) to provide an electrostatic barrier between two electrons across the two parallel arrays of quantum dots along the Z-axis. As depicted, the common doped well DW is interposed between the plurality of qubit regions 134 and the plurality of qubit regions 234 along the Z-axis, thereby allowing entanglement between carriers (e.g., carriers 180 and 280) in the two parallel arrays of quantum dots along the Z-axis.

[0048] During operation of the top die 100, an external magnetic field (not depicted) is applied to the qubit regions 134. A voltage is applied to the plunger gate structure 140, which turns on the channel region 132 and generates a current that flows from one of the S / D members 130 through the channel region 132 to the other one of the S / D members 130. For embodiments in which the carriers 180 include electrons, each of the carriers 180 in each qubit region 134 exhibits electron spin according to the voltage applied to the plunger gate structure 140 above the qubit region. The barrier gate structure 150, which is arranged in alternation with the plunger gate structure 140, is used to define the location of each qubit region 134 as described above, and to control the tunneling coupling or confinement of the carriers 180 between laterally adjacent qubit regions 134. For example, adjusting the voltage applied to the barrier gate structure 150 can increase or decrease the potential barrier (i.e., the electrostatic control thereof) for the carriers 180 through each qubit region 134. The controlled tunneling coupling of only a single electron (or hole) through a qubit region 134 before allowing any other electrons (or holes) to move into the same qubit region 134 is referred to as a qubit.

[0049] In the present embodiment, by adjusting the voltage applied to each of the plunger gate structure 140 and the barrier gate structure 150, electrostatic control and confinement of the quantum dots present in the channel region 132 along the X-direction can be achieved, thereby allowing the carriers 180 in two laterally adjacent qubit regions 134 to entangle (as indicated by the dashed lines in FIG. 1A) as indicated by the dashed lines in FIG. 1A. Figure 2AThe horizontal dashed line between qubit regions 134a and 134b in the bottom chip 200 indicates, and forms, a stable eigenstate. The operating mechanism of the bottom chip 200 is substantially similar to that of the top chip 100 described above, and is therefore omitted for brevity.

[0050] The coupling (e.g., by wafer bonding) of the bottom chip 200 to the top chip 100 merges the second doped well 170 with the third doped well 270 to form a common doped well DW between the first array of quantum dots 180 in the top chip 100 and the second array of quantum dots 280 in the bottom chip 200. Thus, by applying a voltage to the second doped well 170 through the first doped well 108, in addition to applying a voltage to the barrier gate structure 150, the potential barrier along the Z-axis between the quantum dots of the first and second arrays (e.g., between qubit regions 134a and 234a) can be adjusted in a similar manner to that of adjusting the potential barrier between two laterally adjacent qubit regions 134 (e.g., between qubit regions 134a and 134b).

[0051] Thus, the device 10 is configured to produce additional electrostatic control and confinement of the quantum dots in the two-dimensional array Al in the top chip 100 (each corresponding to a qubit region 134) or the two-dimensional array of quantum dots (not depicted) in the bottom chip 200 (each corresponding to a qubit region 234) along the vertical direction (e.g., the Z-axis). In this regard, each of the carriers 180 in the top chip 100 (e.g., carrier 180a) can not only be entangled with laterally adjacent carriers 180 (e.g., carrier 180b), but also with vertically adjacent carriers 280 (e.g., carrier 280a), where this vertical entanglement is indicated by the vertical dashed line between qubit regions 134a and 234a in the bottom chip 200, resulting in a more stable eigenstate of the corresponding quantum dots. Figure 2A The vertical dashed line between qubit regions 134a and 234a in the bottom chip 200 indicates, and forms, a stable eigenstate of the corresponding quantum dots.

[0052] Figure 3A and Figure 3B A flowchart of a method 300 of forming the device 10 according to one or more embodiments of the present disclosure is collectively illustrated. It should be noted that the method 300 is merely an example and as such is not intended to limit the present disclosure. Accordingly, additional operations can be provided before, during, and after the method 300, and some other operations described herein can be omitted. The order of the operations / processes can be interchangeable. In some embodiments, the operations of the method 300 can be performed with the device 10 as described in FIGS. 1-2, and as such, the description of the device 10 is incorporated by reference herein. Figure 3A and Figure 3B Additional operations can be provided before, during, and after the method 300, and some other operations described herein can be omitted. The order of the operations / processes can be interchangeable. In some embodiments, the operations of the method 300 can be performed with the device 10 as described in FIGS. 1-2, and as such, the description of the device 10 is incorporated by reference herein. Figures 4A to 13The cross-sectional views of the different manufacturing stages are associated with the different views shown, which will be discussed in further detail below. Throughout the various views and illustrative embodiments, the same element symbols are used to designate the same elements. Moreover, embodiments of the device 10 are not limited to the embodiments depicted herein. For example, the device 10 can include several other devices, such as inductors, fuses, capacitors, coils, etc., which are not shown herein for the sake of clarity.

[0053] Figure 4A Figure 5A Figure 6A Figure 7A Figure 8A Figure 9A Figure 10A Figure 11A Figure 12 is a cross-sectional view of a portion of the device 10 (e.g., the top die 100) along the line A-A’ of FIG. 1 at an intermediate stage of the method 300 according to some embodiments of the present disclosure. Figure 1 is a cross-sectional view of a portion of the device 10 (e.g., the bottom die 200) along the line A-A’ of FIG. 1 at an intermediate stage of the method 300 according to some embodiments of the present disclosure. Figure 13 Figure 1 Figure 4B Figure 5B Figure 6B Figure 7B Figure 8B Figure 9B Figure 10B Figure 11B is a cross-sectional view of a portion of the device 10 along the line B-B’ of FIG. 1 at an intermediate stage of the method 300 according to some embodiments of the present disclosure. Figure 1 Figure 4C Figure 5C Figure 6C Figure 7C Figure 8C Figure 9C Figure 10C Figure 11C is a cross-sectional view of the device 10 along the line C-C’ of FIG. 1 at an intermediate stage of the method 300 according to some embodiments of the present disclosure. Figure 1 Figure 4D Figure 5D Figure 6D Figure 7D Figure 8D Figure 9D Figure 10D Figure 11D is a cross-sectional view of the device 10 along the line D-D’ of FIG. 1 at an intermediate stage of the method 300 according to some embodiments of the present disclosure. Figure 1 Figure 4E Figure 11E ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​is a device 10 along line E-E' of some embodiments in accordance with the present disclosure Figure 1 is a cross-sectional view of some embodiments of the device 10 along line E-E' of the method 300 at an intermediate stage.

[0054] Referring to Figure 3A and Figures 4A to 4E At operation 302, a first doped well 108 (e.g., as depicted 108b) is formed in the substrate 102. The substrate 102 includes a front side 102a opposite a backside 102b. In some embodiments, the substrate 102 includes a p-type silicon substrate (p-substrate). For example, a p-type dopant is introduced into the substrate 102 to form the p-substrate.

[0055] In some embodiments, an implantation process is performed to introduce a first dopant into the substrate 102 to form the first doped well 108 over the front side 102a of the substrate 102. Depending on the type of carriers through the qubit region 134, the first dopant can be a p-type dopant or an n-type dopant. For example, the first doped well 108 includes a p-type dopant for providing electrostatic control of electrons (e.g., carriers 180) in the qubit region 134. In this regard, the first doped well 108 is a p-well formed in a p-substrate.

[0056] Referring to Figure 3A and Figures 4A to 4E At operation 304, fins (i.e., active regions) 104a-c are formed adjacent to respective first doped wells 108a-c along the X-axis over the front side 102a. The fins 104 vertically protrude or extend from the substrate 102 along the Z-axis.

[0057] In some embodiments, the fins 104 are formed by patterning the substrate 102 using, for example, lithography and etching techniques. For example, a mask layer (not depicted) including a pad oxide layer and an overlying pad nitride layer is formed over the substrate 102. The pad oxide layer can be a thin film including, for example, silicon oxide formed using a thermal oxidation process. The pad oxide layer 210 can act as an adhesion layer between the substrate 102 and the overlying pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof. The pad oxide layer and the pad nitride layer can each be formed using, for example, low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0058] The mask layer can be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material (not depicted) that is deposited, irradiated (or exposed), and developed to remove portions of the photoresist material. The remaining photoresist material protects underlying materials (e.g., the mask layer in this example) from subsequent processing steps, such as etching. For example, the photoresist material is used to pattern the liner oxide and liner nitride layers to form a patterned mask that is subsequently used to pattern exposed portions of the substrate 102 to form trenches (not depicted), thereby defining fins 104 that are separated by the trenches. In some embodiments, the fins 104 are formed by etching trenches in the substrate 102 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), the like, or combinations thereof. The etching can be implemented anisotropically. In some embodiments, the trenches can be parallel strips (as viewed from the top) and closely spaced relative to each other. In some embodiments, the trenches can be continuous and surround each fin 104. In this regard, although not depicted herein, the top surface of the resulting fins 104 is overlaid with the patterned mask until it is removed by subsequent fabrication steps.

[0059] In some embodiments, an implantation process is performed to dope the fins 104 such that the channel region 132 subsequently defined in each fin 104 contains dopants appropriate for the intended conductivity type of the resulting FET. For example, for an n-type FET, the fins 104 can be doped with p-type dopants, and for a p-type FET, the fins 104 can be doped with n-type dopants.

[0060] The fins 104 can be patterned by other suitable methods. In one example, the fins 104 can be patterned using one or more photolithography processes, including a double patterning or multiple patterning process. Generally, double patterning or multiple patterning processes combine photolithography with self-alignment processes, allowing patterns to be generated with, for example, smaller pitch than would otherwise be possible using a single direct photolithography process. For example, in one embodiment, a sacrificial layer (not depicted) is formed over the substrate 102 and patterned using a photolithography process. Spacers (not depicted) are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins 104.

[0061] In another example, the top portion of the substrate 102 can be replaced by or overlaid with a suitable material, such as an epitaxial material (not depicted) appropriate for the intended conductivity type (e.g., n-type or p-type) of the semiconductor devices to be formed. The epitaxial material can be grown over the substrate 102 by any suitable epitaxial process. Thereafter, the substrate 102 with the epitaxial material provided over the top portion is patterned by, for example, the photolithography processes described herein to form the fins 104 that include the epitaxial material.

[0062] In some examples, each fin 104 can be formed to a fin height FH, defined as the height by which the fin 104 extends above the isolation region 106, ranging from about 0 nm (indicating a planar surface rather than a fin active region) to about 20 nm. Each fin 104 can be formed to a fin root height FRH, defined as the height of the portion of the fin 104 embedded in the isolation region 106, ranging from about 0 nm (indicating a planar surface rather than a fin active region) to about 20 nm. Each fin 104 can be formed to a fin base height FBH, defined as the height of the portion of the substrate 102 below the fin 104, ranging from about 0 nm (indicating a planar surface rather than a fin active region) to about 20 nm. Each fin 104 can be formed to a fin width FW ranging from about 5 nm to about 20 nm. Each fin 104 can be formed to a fin pitch FP greater than about 50 nm.

[0063] Still referring to Figure 3A and Figures 4A to 4E At operation 306, an isolation region 106 is formed over the substrate 102 to surround the bottom of the fin 104. The isolation region 106 can be formed by high-density plasma chemical vapor deposition (HDPCVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by an anneal or cure process to densify the deposited material into another material, such as an oxide), spin-on, the like, or a combination thereof.

[0064] In some embodiments, the dielectric material of the isolation region 106 includes silicon oxide formed by a FCVD process. Once the dielectric material is deposited, an anneal process can be performed. A planarization process, such as a chemical mechanical polishing / planarization (CMP) process, can remove any excess dielectric material such that a top surface of the dielectric material is substantially coplanar with a top surface of the fin 104 (or a top surface of the substrate 102 if the top die 100 includes planar devices). A patterned mask over the top surface of the fin 104 can also be removed by the planarization process. Subsequently, the dielectric material is recessed to form the isolation region 106 in a trench each placed between two adjacent fins 104. In some embodiments, the isolation region 106 includes a shallow trench isolation (STI) member. The isolation region 106 is recessed such that an upper portion of the fin 104 protrudes between adjacent isolation regions 106.

[0065] As another example of forming the fins 104 and isolation regions 106, a dielectric layer (not depicted) can be formed over the top surface of the substrate 102; trenches can be etched through the dielectric layer; a homoepitaxial structure can be epitaxially grown in the trenches; and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fins 104. In yet another example, a dielectric layer (not depicted) can be formed over the top surface of the substrate 102; trenches can be etched through the dielectric layer; a heteroepitaxial structure can be epitaxially grown in the trenches using a material different from the substrate 102; and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 104. The epitaxially grown material or structure can be doped in situ during growth, which can avoid prior and subsequent implantation, although in situ and implantation doping can be used together.

[0066] Referring to Figure 3A and Figures 5A to 5D At operation 308, dummy gate structures 110a-d (collectively, dummy gate structures 110) are formed over the portion of each fin 104 defined as the channel region 132. Each dummy gate structure 110 can include a dummy gate dielectric layer (not separately depicted) over the fin 104 and a dummy gate electrode (not separately depicted) over the dummy gate dielectric layer. The dummy gate structure 110 can optionally include an interface layer between the fin 104 and the dummy gate dielectric layer, where the interface layer can include an oxide, such as silicon oxide. The dummy gate dielectric layer can include any suitable dielectric material, such as silicon oxide, silicon nitride, multilayers thereof, or the like. The dummy gate electrode can include polysilicon. In some examples, each dummy gate structure 110 can be formed to a first gate length LI in a range of about 5 nm to about 20 nm.

[0067] The various layers of each dummy gate structure 110 can be sequentially deposited over the fin 104 as blanket layers by any suitable process, such as CVD, atomic layer deposition (ALD), or physical vapor deposition (PVD), thermal growth, or chemical growth, and then planarized, such as by a CMP process. A mask layer (not depicted) including silicon nitride or the like can be deposited over the various blanket layers of the dummy gate structure 110. The mask layer can be patterned using a series of lithography and etching processes, and then transferred to the blanket layers using any suitable etching process to form the dummy gate structure 110.

[0068] Referring to Figure 3A and Figures 6A to 6DAt operation 310, gate spacers 120 are formed over the sidewalls of each dummy gate structure 110. Gate spacers 120 are formed to surround each dummy gate structure 110 (e.g., along and contact the sidewalls of each dummy gate structure 110). It should be understood that any number of gate spacers can be formed around dummy gate structures 110 while remaining within the scope of the present disclosure.

[0069] Gate spacers 120 can be formed by first conformally depositing a dielectric layer over dummy gate structures 110 using any suitable deposition process (e.g., thermal oxidation, CVD, or the like), and then removing portions of the dielectric layer using a suitable etching process (e.g., a directional or anisotropic dry etching process), leaving gate spacers 120 along the opposing sidewalls of dummy gate structures 110. In some embodiments, etching the dielectric layer removes the topmost portions of gate spacers 120, resulting in a rounded profile in gate spacers 120, as depicted herein.

[0070] Referring back to Figure 3A and Figures 6A to 6D At operation 312, a dielectric layer 124 is selectively formed over channel region 132. In the present embodiment, dielectric layer 124 overlies portions of each dummy gate structure 110, gate spacers 120, and fins 104 interposed between gate spacers 120 in channel region 132. In some embodiments, dielectric layer 124 is configured as a protective or masking layer over channel region 132 during subsequent formation of S / D members 130.

[0071] Dielectric layer 124 can be formed by any suitable process. For example, dielectric layer 124 can first be conformally deposited over substrate 102 by any suitable process (e.g., CVD, ALD, or PVD). A patterned mask layer (e.g., a patterned photoresist layer; not depicted) can be formed over portions of dielectric layer 124 over channel region 132, and then the remaining portions of dielectric layer 124 exposed by the patterned mask layer can be removed using any suitable etching process, leaving dielectric layer 124 over channel region 132. The patterned mask layer can then be removed by any suitable process (e.g., plasma ashing or photoresist stripping).

[0072] Still referring back to Figure 3A and Figures 6A to 6D At operation 314, the pair of S / D members 130 are formed over fins 104. S / D members 130 are each placed adjacent to the outermost dummy gate structure 110 along the X-axis.

[0073] In some embodiments, forming the S / D members 130 includes first removing portions of the fin 104 adjacent to the channel regions 132 to form S / D recesses (not depicted). The S / D recesses can be formed by performing any suitable etching process, such as a dry etching process. For example, the S / D recesses can be formed by a non-isotropic dry etching process using the dummy gate structures 110 (e.g., dummy gate structures 110 formed in adjacent channel regions 132 along the X-axis, not depicted herein) as an etching mask. The depth of the S / D recesses can be controlled by varying one or more parameters of the etching process. Subsequently, the S / D members 130 are formed (or grown) in their respective S / D recesses by any suitable process, such as metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or combinations thereof, each S / D member 130 including one or more doped epitaxial layers. Each pair of S / D members 130 includes one or more dopants corresponding to the conductivity type of the resulting FET. For example, the S / D members 130 can include p-type dopants to form a p-type FET, and alternatively, the S / D members 130 can include n-type dopants to form an n-type FET. In some embodiments, the S / D members 130 are doped with n-type dopants to form n-type FETs over a substrate 102 including a p-substrate.

[0074] Referring to Figure 3A and Figures 7A to 7D At operation 316, an ILD layer 138 is formed over the top die 100. In some embodiments, prior to forming the ILD layer 138, a contact etch stop layer (CESL; not depicted) is formed over the top die 100. The ILD layer 138 and the CESL include different materials to provide etch selectivity between them in subsequent fabrication processes. The CESL can be formed by a suitable formation method, such as CVD, ALD, PVD, the like, or combinations thereof. The ILD layer 138 can be deposited by any suitable method, such as CVD, PECVD, FCVD, or the like. After depositing the ILD layer 138, a planarization process, such as a CMP process, can be performed to achieve substantially coplanar top surfaces of, for example, the ILD layer 138, the dummy gate structures 110, and the dielectric layer 124.

[0075] Referring to Figure 3B and Figures 8A to 8DAt operation 318, dummy gate structures 110 are replaced with plunger gate structures 140 between gate spacers 120. Replacing dummy gate structures 110 includes first removing dummy gate structures 110 to form gate trenches (not depicted) between gate spacers 120. In some embodiments, dummy gate structures 110 are removed by one or more etching steps between respective gate spacers 120 to expose portions of channel regions 132 corresponding to qubit regions 134. In some embodiments, a dummy gate dielectric layer (not depicted) can be used as an etch stop layer when etching the dummy gate electrodes. Then, after removing the dummy gate electrodes, the dummy gate dielectric layer can be removed.

[0076] Subsequently, plunger gate structures 140 are formed in the gate trenches, each plunger gate structure 140 including at least a plunger gate dielectric layer 142 and a plunger gate electrode 144. For example, plunger gate dielectric layer 142 can be formed in the gate trenches by any suitable method, such as ALD, CVD, PECVD, molecular beam deposition (MBD), the like, or combinations thereof. Plunger gate electrode 144 can be formed as a blanket layer over plunger gate dielectric layer 142 by any suitable method, such as PVD, CVD, electroplating, electroless plating, the like, or combinations thereof, and then planarized, such as by a CMP process, to expose top surfaces of gate spacers 120. In some examples, each of plunger gate structures 140 inherits the first gate length LI of dummy gate structures 110, which can be in a range of about 5 nm to about 20 nm.

[0077] Although not depicted, plunger gate electrode 144 can further include a barrier layer, a seed layer, the like, or combinations thereof. In one example, the barrier layer can include Ti, Ta, TiN, TaN, the like, or combinations thereof, and can be deposited by any suitable method, such as CVD or ALD. In some embodiments, an interface layer (not depicted) can be formed in the gate trenches prior to forming plunger gate dielectric layer 142. The interface layer can include an oxide, such as silicon oxide, and can be formed by any suitable method, such as ALD, CVD, thermal oxidation, chemical oxidation, the like, or combinations thereof.

[0078] In some embodiments, although not depicted, one or more work function layers can be conformally formed over the plug gate dielectric layer 142 prior to forming the plug gate electrode 144. The work function layers can include a p-type work function layer, an n-type work function layer, multilayers thereof, or combinations thereof. In the discussion herein, the work function layers can also be referred to as work function metals. Examples of the work function layers can include TiN, TaN, Ru, Mo, Al, ZrSi2, MoSi2, TaSi2, NiSi2, WN, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, the like, or combinations thereof. The work function layers can be deposited by CVD, PVD, ALD, the like, or combinations thereof. Additional layers (not depicted) including a capping layer, a glue layer (or adhesion layer), the like, or combinations thereof can also be formed between the plug gate dielectric layer 142 and the plug gate electrode 144 by any suitable method, such as CVD, PVD, ALD, MBD, the like, or combinations thereof.

[0079] Referring to Figure 3B and Figures 9A to 9D At operation 320, the ILD layer 138 is patterned to form openings 148a, 148b, and 148c (collectively, openings 148) interspersed between the plug gate structures 140a-140d. In some embodiments, the openings 148 are formed by first forming a patterned mask layer 146 over the ILD layer 138, where the patterned mask layer 146 can include a patternable material, such as a photoresist material, by a suitable method, such as the photolithography process described above. The patterned mask layer 146 includes a plurality of openings corresponding to portions of the ILD layer 138 to be removed, i.e., between two adjacent plug gate structures 140, while portions of the ILD layer 138 over the plug gate structures 140, the S / D members 130, the first doped well 108, etc. remain under the patterned mask layer 146. Subsequently, the exposed portions of the ILD layer 138 are removed by any suitable etching process, such as a dry etching process or a wet etching process, to form the openings 148. The resulting openings 148 each expose a portion of the dielectric layer 124 between two adjacent plug gate structures 140. Thereafter, the patterned mask layer 146 is removed by any suitable method, such as plasma ashing or photoresist stripping.

[0080] Referring to Figure 3B and Figures 10A to 10DAt operation 322, barrier gate structures 150a-150c are respectively formed in openings 148a-148c. In some embodiments, barrier gate structures 150 are formed by forming a metal layer over plunger gate structures 140, thereby filling openings 148, and then planarizing the metal layer to form barrier gate structures 150 between two adjacent plunger gate structures 140. As described above, two adjacent barrier gate structures 150 respectively define an entrance and an exit of each qubit region 134 corresponding to each quantum dot. In some examples, a bottom of each barrier gate structure 150 can be formed to a second gate length L2, and a top of each barrier gate structure 150 can be formed to a third gate length L3 that is greater than the second gate length L2. Each of the second gate length L2 and the third gate length L3 can be in a range of about 5 nm to about 20 nm.

[0081] Referring to Figure 3B and Figures 11A to 11E At operation 324, various contact members (i.e., MEOL structures) are formed in ILD layer 138, such as S / D contacts 160 and doped well contacts 164. As described above, each S / D contact 160 is coupled to an S / D member 130, while a doped well contact 164 is coupled to first doped well 108 (and subsequently to second doped well 170). In some embodiments, ILD layer 138 is first patterned to form a plurality of contact openings (not depicted) to expose a corresponding member (e.g., S / D member 130 or first doped well 108) by a series of photolithographic patterning and etching processes similar to those described above. In the case of S / D contacts 160, etching of the corresponding contact openings can stop on S / D members 130 and / or a silicide layer (not depicted) formed over S / D members 130. In the case of doped well contacts 164, etching of the corresponding contact openings can stop on first doped well 108. Subsequently, a metal fill layer described above is deposited over top die 100, thereby filling each contact opening. A planarization process (e.g., a CMP process) is performed to remove portions of the metal fill layer formed over ILD layer 138, resulting in S / D contacts 160 and doped well contacts 164. In some embodiments, a barrier layer described above is formed in the contact openings prior to depositing the metal fill layer.

[0082] Additional contact members can also be formed at operation 324, such as gate contacts (not depicted) respectively coupled to plunger gate structures 140 and gate contacts (not depicted) respectively coupled to barrier gate structures 150. Furthermore, MLI structures (i.e., BEOL structures; not depicted) described above can also be formed over and coupled to the contact members at operation 324.

[0083] Referring to Figure 3B and Figure 12At operation 326, a second doped well 170 is formed over the backside 102b of the substrate 102, resulting in the top die 100. Prior to forming the second doped well 170, the top die 100 is inverted such that the backside 102b is exposed for processing. Subsequently, an implantation process is performed to dope at least a region of the backside 102b corresponding to the channel region 132 of the top die 100. In some embodiments, the parameters of the implantation process (e.g., doping energy) are tuned to ensure that the second doped well 170 is thick enough to physically contact the bottom of the first doped well 108.

[0084] Referring to Figure 3B and Figure 13 , and at operation 328, the bottom (second) die 200 is formed after or concurrently with the top (first) die 100 by implementing operations 302-326. The bottom die 200 includes substantially similar components to those of the top die 100 as described above, except that the bottom die 200 does not include any doped well contacts similar to the doped well contacts 164 of the top die 100.

[0085] Thereafter, as Figures 1 to 2E depicted, at operation 330, the top die 100 is coupled or bonded to the bottom die 200 by merging the second doped well 170 with a third doped well 270 to form a common doped well DW in the device 10. The top die 100 can be coupled to the bottom die 200 by any suitable wafer bonding process. In some examples, the top die 100 and the bottom die 200 can be bonded by connection of TSVs 174 and 274 or other die-to-die connections including hybrid bonding via a bonding interface layer, solder bumps, the like, or combinations thereof. In some examples, referring to Figure 2A , the thickness T of the DW is in the range of about 5 nm to about 20 nm. By bonding the top die 100 and the bottom die 200 together, the channel regions 132 and 232 are vertically aligned such that entanglement between the carriers 180 and 280 along the Z-axis can be achieved in response to a voltage applied to the common doped well DW by the first doped well 108.

[0086] According to an aspect of the disclosure, a semiconductor device includes a first substrate having a first front side and a first back side separated along a first direction. The semiconductor device includes first source / drain members over the first front side. The semiconductor device includes first barrier gates between the first source / drain members over the first front side. The semiconductor device includes a first plunger gate adjacent to the first barrier gates along a second direction perpendicular to the first direction. The first plunger gate defines a first qubit region over the first front side. The semiconductor device includes a second substrate having a second front side and a second back side separated along the first direction. The semiconductor device includes second source / drain members over the second front side. The semiconductor device includes second barrier gates between the second source / drain members over the second front side. The semiconductor device includes a second plunger gate adjacent to the second barrier gates. The second plunger gate defines a second qubit region over the second front side. The second qubit region is aligned with the first qubit region along the first direction. The semiconductor device includes a doped well extending between the first back side and the second back side along the first direction.

[0087] According to another aspect of the disclosure, a semiconductor device includes a first substrate having a first side and a second side opposite the first side. The semiconductor device includes a second substrate having a third side and a fourth side opposite the third side. The semiconductor device includes a first doped well merging the second side and the fourth side. The semiconductor device includes a first channel region extending along a first direction over the first side. The semiconductor device includes first plunger gate structures and first barrier gate structures alternately arranged in the first channel region along the first direction. The first plunger gate structures each define a first qubit region. The semiconductor device includes a second channel region extending along the first direction over the third side. The semiconductor device includes second plunger gate structures and second barrier gate structures alternately arranged in the second channel region along the first direction. The second plunger gate structures each define a second qubit region. The semiconductor device includes a second doped well placed in the first substrate and adjacent to one of the first plunger gate structures along the first direction. The second doped well is coupled to the first doped well.

[0088] According to yet another aspect of the disclosure, a method includes forming first source / drain members over a front side of a first substrate. The first substrate includes a back side opposite the front side. The method includes forming first plunger gates between the first source / drain members. The first plunger gates each define a first qubit region over the front side of the first substrate. The method includes forming first barrier gates each interposed between two adjacent first plunger gates. The method includes forming first doped wells over the back side of the first substrate. The method includes forming second source / drain members over a front side of a second substrate. The second substrate includes a back side opposite the front side. The method includes forming second plunger gates between the second source / drain members. The second plunger gates each define a second qubit region over the front side of the second substrate. The method includes forming second barrier gates each interposed between two adjacent second plunger gates. The method includes forming second doped wells over the back side of the second substrate. The method includes merging the first doped wells with the second doped wells, thereby coupling the first substrate to the second substrate.

[0089] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

[0090] Legend

[0091] 10: device

[0092] 100: top die

[0093] 102: substrate

[0094] 102a: front side

[0095] 102b: back side

[0096] 104: active region

[0097] 104a-c: active regions

[0098] 106: isolation region

[0099] 108: first doped well

[0100] 108a-c: first doped wells

[0101] 110a to 110d: dummy gate structures

[0102] 120: gate spacers

[0103] 124: dielectric layer

[0104] 130: source / drain (S / D) features

[0105] 130a to 130c: source / drain (S / D) features

[0106] 132: channel region

[0107] 132b: channel region

[0108] 132c: channel region

[0109] 134a to 134d: qubit regions

[0110] 138: interlayer dielectric (ILD) layer

[0111] 140: plug gate structure

[0112] 140a to 140d: plug gate structure

[0113] 142: plug gate dielectric layer

[0114] 144: plug gate electrode

[0115] 146: patterned mask layer

[0116] 148a to 148c: openings

[0117] 150a to 150c: barrier gate structures

[0118] 160: source / drain (S / D) contacts

[0119] 164: doped well contacts

[0120] 170: second doped well

[0121] 174: through-substrate via (TSV)

[0122] 180a to 180d: carriers

[0123] 200: bottom die

[0124] 202: substrate

[0125] 202a: front side

[0126] 202b: back side

[0127] 204: fin

[0128] 204a-c: fins

[0129] 206: isolation region

[0130] 220: gate spacer

[0131] 224: dielectric layer

[0132] 230: source / drain (S / D) member

[0133] 230a-c: source / drain (S / D) member

[0134] 232: channel region

[0135] 232b: channel region

[0136] 234a-d: qubit region

[0137] 238: interlayer dielectric (ILD) layer

[0138] 240: plunger gate structure

[0139] 240a-d: plunger gate structure

[0140] 242: plunger gate dielectric layer

[0141] 244: plunger gate electrode

[0142] 250a-c: barrier gate structure

[0143] 260: source / drain (S / D) contact

[0144] 270: third doped well

[0145] 274: through-substrate via (TSV)

[0146] 280a-d: carrier

[0147] 300: method

[0148] 302: operation

[0149] 304: operation

[0150] 306: operation

[0151] 308: operation

[0152] 310: operation

[0153] 312: operation

[0154] 314: operation

[0155] 316: operation

[0156] 318: operation

[0157] 320: operation

[0158] 322: operation

[0159] 324: operation

[0160] 326: operation

[0161] 328: operation

[0162] 330: operation

[0163] DW: common doped well

[0164] FW: fin width

[0165] FBH: fin base height

[0166] FH: fin height

[0167] FRH: fin root height

[0168] FP: fin pitch

[0169] L1: first gate length

[0170] L2: second gate length

[0171] L3: third gate length

Claims

1. A semiconductor device, characterized by It includes: a first substrate having a first front side and a first back side separated along a first direction; first source / drain members over the first front side; first barrier gates between the first source / drain members over the first front side; a first plunger gate adjacent to the first barrier gates along a second direction perpendicular to the first direction, the first plunger gate defining a first qubit region over the first front side; a second substrate having a second front side and a second back side separated along the first direction; second source / drain members over the second front side; second barrier gates between the second source / drain members over the second front side; a second plunger gate adjacent to the second barrier gates, the second plunger gate defining a second qubit region over the second front side, the second qubit region aligned with the first qubit region along the first direction; and a doped well extending between the first back side and the second back side along the first direction.

2. The semiconductor device according to claim 1, wherein The doped well is a first doped well, the semiconductor device further including a second doped well spaced from one of the first source / drain members along the second direction, the second doped well coupled to the first doped well along the first direction.

3. The semiconductor device according to claim 2, wherein The second doped well and the first doped well have a same conductivity type.

4. The semiconductor device according to claim 1, wherein It further includes: a first dielectric layer between the first barrier gates and the first substrate; a second dielectric layer between the first plunger gate and the first substrate; a third dielectric layer between the second barrier gates and the second substrate; and a fourth dielectric layer between the second plunger gate and the second substrate.

5. The semiconductor device according to claim 1, wherein It further includes: a first through-substrate via extending from the first front side to the doped well along the first direction; and a second through-substrate via extending from the second front side to the doped well along the first direction, the second through-substrate via coupled to the first through-substrate via.

6. A semiconductor device, characterized by It includes: a first substrate having a first side and a second side opposite the first side; a second substrate having a third side and a fourth side opposite the third side; a first doped well merging the second side and the fourth side; a first channel region extending along a first direction over the first side; first plunger gate structures and first barrier gate structures alternately arranged in the first channel region along the first direction, the first plunger gate structures each defining a first qubit region; a second channel region extending along the first direction over the third side; second plunger gate structures and second barrier gate structures alternately arranged in the second channel region along the first direction, the second plunger gate structures each defining a second qubit region; and a second doped well placed in the first substrate and adjacent to one of the first plunger gate structures along the first direction, the second doped well coupled to the first doped well.

7. The semiconductor device according to claim 6, wherein The first doped well and the second doped well include a dopant having a same conductivity.

8. The semiconductor device according to claim 6, wherein It further includes: a pair of first source / drain members over the first side, the first channel region interposed between the first source / drain members; and a pair of second source / drain members over the third side, the second channel region interposed between the second source / drain members.

9. The semiconductor device according to claim 6, wherein The first plug gate structures each include a first gate electrode over a first gate dielectric layer, and wherein the second plug gate structures each include a second gate electrode over a second gate dielectric layer.

10. The semiconductor device according to claim 6, wherein It further includes: a pair of first gate spacers along sidewalls of each of the first plug gate structures, each of the first gate spacers interposed between each of the first plug gate structures and each of the first barrier gate structures; and a pair of second gate spacers along sidewalls of each of the second plug gate structures, each of the second gate spacers interposed between each of the second plug gate structures and each of the second barrier gate structures.

Images