Semiconductor structure

Abstract

A semiconductor structure includes a first semiconductor chip, a second semiconductor chip, a first high dielectric constant dielectric layer, a second high dielectric constant dielectric layer, a first metal gate, a plurality of first epitaxial structures and a plurality of second epitaxial structures. The second semiconductor sheet is over the first semiconductor sheet. The first high dielectric constant dielectric layer surrounds the first semiconductor sheet, wherein the first high dielectric constant dielectric layer has a dipole dopant. The second high dielectric constant dielectric layer surrounds the second semiconductor sheet, wherein the second high dielectric constant dielectric layer is free of dipole dopants. The first metal gate surrounds the first high dielectric constant dielectric layer and the second high dielectric constant dielectric layer. The plurality of first epitaxial structures are located on multiple opposite sides of the first semiconductor wafer, and the plurality of second epitaxial structures are located on multiple opposite sides of the second semiconductor wafer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor structure. BACKGROUND

[0002] As the semiconductor industry further advances to technology nodes less than 10 nanometers (nm) in pursuit of higher device densities, higher performance, and lower costs, challenges from manufacturing and design issues have led to stacked device structure configurations, such as complementary field effect transistors (C-FETs), in which an n-type multi-gate transistor and a p-type multi-gate transistor are vertically stacked, one on top of the other. While existing complementary field effect transistor structures are generally adequate for their intended purposes, they are not entirely satisfactory in all respects. SUMMARY

[0003] In some embodiments, a semiconductor structure includes a first semiconductor sheet, a second semiconductor sheet, a first high dielectric constant dielectric layer, a second high dielectric constant dielectric layer, a first metal gate, a plurality of first epitaxial structures, and a plurality of second epitaxial structures. The second semiconductor sheet is above the first semiconductor sheet. The first high dielectric constant dielectric layer surrounds the first semiconductor sheet, wherein the first high dielectric constant dielectric layer has a dipole dopant. The second high dielectric constant dielectric layer surrounds the second semiconductor sheet, wherein the second high dielectric constant dielectric layer is free of the dipole dopant. The first metal gate surrounds the first high dielectric constant dielectric layer and the second high dielectric constant dielectric layer. The plurality of first epitaxial structures are on opposite sides of the first semiconductor sheet, wherein the first semiconductor sheet, the first high dielectric constant dielectric layer, the plurality of first epitaxial structures, and a first portion of the first metal gate form a first bottom transistor. The plurality of second epitaxial structures are on opposite sides of the second semiconductor sheet, wherein the second semiconductor sheet, the second high dielectric constant dielectric layer, the plurality of second epitaxial structures, and a second portion of the first metal gate form a first top transistor.

[0004] In some embodiments, a semiconductor structure includes a first channel layer, a second channel layer, a first gate dielectric layer, a second gate dielectric layer, a first gate electrode layer, a plurality of first source / drain regions, and a plurality of second source / drain regions. The second channel layer is above a channel layer. The first gate dielectric layer surrounds a first semiconductor sheet, wherein the first gate dielectric layer is free of dipole dopants. The second gate dielectric layer surrounds a second semiconductor sheet, wherein the second gate dielectric layer has the aforementioned dipole dopants. The first gate electrode layer surrounds the first gate dielectric layer and the second gate dielectric layer. The plurality of first source / drain regions are on opposite sides of the first channel layer, wherein the first channel layer, the first gate dielectric layer, the first source / drain regions, and a first portion of the first gate electrode layer form a first bottom transistor. The plurality of second source / drain regions are on opposite sides of the second channel layer, wherein the second channel layer, the second gate dielectric layer, the second source / drain regions, and a second portion of the first gate electrode layer form a first top transistor.

[0005] In some embodiments, a semiconductor structure includes a first semiconductor nanostructure, a second semiconductor nanostructure, a third semiconductor nanostructure, a fourth semiconductor nanostructure, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, a fourth high-k dielectric layer, a first gate electrode layer, and a second gate electrode layer. The second semiconductor nanostructure is laterally adjacent to the first semiconductor nanostructure. The third semiconductor nanostructure is above the first semiconductor nanostructure. The fourth semiconductor nanostructure is above the second semiconductor nanostructure. The first high-k dielectric layer surrounds the first semiconductor nanostructure, wherein the first high-k dielectric layer has dipole dopants. The second high-k dielectric layer surrounds the second semiconductor nanostructure, wherein the second high-k dielectric layer is free of the aforementioned dipole dopants. The third high-k dielectric layer surrounds the third semiconductor nanostructure, wherein the third high-k dielectric layer is free of the aforementioned dipole dopants. The fourth high-k dielectric layer surrounds the fourth semiconductor nanostructure, wherein the fourth high-k dielectric layer has the aforementioned dipole dopants. The first gate electrode layer surrounds the first high-k dielectric layer and the third high-k dielectric layer. The second gate electrode layer surrounds the second high-k dielectric layer and the fourth high-k dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the disclosure are best understood from the following detailed description read in light of the accompanying drawings. It should be noted that the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0007] FIG. 1 A three-dimensional view illustration of a complementary field effect transistor (CFET) is depicted in accordance with some embodiments;

[0008] FIGS. 2A-8B schematic views of intermediate stages of manufacturing a complementary field effect transistor according to some embodiments are depicted;

[0009] FIGS. 9-16B schematic views of intermediate stages of manufacturing a complementary field effect transistor according to some embodiments are depicted;

[0010] FIGS. 17-21C schematic views of intermediate stages of manufacturing a complementary field effect transistor according to some embodiments are depicted;

[0011] FIGS. 22-33C schematic views of intermediate stages of manufacturing a complementary field effect transistor according to some embodiments are depicted.

[0012]

Symbolic Description

[0013] 100, 200, 300, 400: semiconductor structure

[0014] 110, 210, 310, 410: substrate

[0015] 112, 212, 312, 412: raised portions

[0016] 120: multilayer stack structure

[0017] 121, 221, 321, 421: isolation layer

[0018] 122a, 122b, 124a, 124b, 224a, 224b, 324a, 324b, 424a, 424b: epitaxial layer

[0019] 125: fin structure

[0020] 130, 170, 175, 230, 270, 275, 330, 370, 375, 430, 470, 475: isolation structure

[0021] 150: dummy gate structure

[0022] 152: dummy gate dielectric layer

[0023] 154: dummy gate electrode layer

[0024] 156: hard mask layer

[0025] 158, 258, 358, 458: gate spacers

[0026] 159, 259, 359, 459: inner dielectric spacer

[0027] 160, 165, 260, 265, 360, 365, 460, 165: source / drain epitaxial structure

[0028] 172, 176: contact etch stop layer

[0029] 174, 178: dielectric layer

[0030] 180, 280, 380, 480: gate structure

[0031] 181, 281, 381, 481: interface layer

[0032] 182, 182', 282, 282', 382, 382', 482, 482': high-k dielectric layer

[0033] 184, 484: barrier layer

[0034] 185a, 185b, 285a, 285b, 285d, 385a, 485a, 485b, 485d, 485f, 485g

[0035] : passivation layer

[0036] 185c, 285c, 285e, 385c, 485c, 485e, 485h: precursor

[0037] 186, 286, 386, 486: dipole layer

[0038] 188, 288, 388, 488: metal gate electrode

[0039] 190, 290a, 290b, 390, 490a, 490b, 490c: dummy material

[0040] 190r: remaining portion

[0041] 192, 292a, 292b, 392, 492a, 492b, 492c: mask layer

[0042] 196a, 296a, 396a, 496a: bottom layer transistor

[0043] 196b, 296b, 396b, 496b: top layer transistor

[0044] A-A', B1-B1', B2-B2', B4-B4', B8-B8', B9-B9', B10-B10', B11-B11':

[0045] line

[0046] GT, GT2, GT3, GT4: gate trench

[0047] O1, O2, O3, O4, O5, O6, O7, O8: opening

[0048] P1, P3, P4, P6, P8, P9, P10: etch back process

[0049] P2, P5, P7, P11: anneal process

[0050] R1, R2, R3, R4, R5, R6, R7, R8, R9, R10: recess

[0051] S1, S2, S3, S4: space

[0052] T1: thickness

[0053] T2, T4, T8, T11: depth DETAILED DESCRIPTION

[0054] The following detailed description is presented to provide a description of various embodiments or examples of the provided technology. The description is not intended to limit the technology to the described embodiments or examples. The described embodiments and examples are merely illustrative of the technology and should not be construed as limiting the scope of the technology. For example, the description of one embodiment or example in the following description does not mean that the same feature is not included in another embodiment or example. In addition, the description of the features in the following description does not mean that the features are not combined in a single embodiment or example. In addition, the following description can repeatedly use the same or similar reference numerals for the same or similar elements. Such repetition is for the purpose of simplicity and clarity and does not indicate a relationship between the various embodiments and / or configurations.

[0055] In addition, spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As used herein, “about”, “approximately”, “roughly”, or “substantially” generally means within 20%, 10%, or 5% of a given value or range. Numerical values given herein are approximate, meaning that “about”, “approximately”, “roughly”, or “substantially” can be inferred if not explicitly stated. However, the skilled artisan will recognize that the values or ranges cited throughout the description are merely examples and can be reduced or varied as integrated circuits are scaled down.

[0056] Various embodiments of the present disclosure provide a method for selectively diffusing a dopant into a high-k dielectric layer of a complementary field effect transistor (C-FET) to adjust the electrical characteristics of either the top or bottom transistors. This method applies an etch back process that effectively improves the performance of the C-FET, regardless of gate width or location on the wafer, ensuring uniform and high quality performance of various C-FET configurations. Specifically, the etch back process can control the direct current (DC power) and radio frequency power (RF power) during the etch back process, particularly the periodic switching of the bias power and DC power, to ensure uniform distribution of etching gas in the gate trench of different widths, resulting in balanced etching rates and uniform recess depth of the dummy material in the gate trench for subsequent selective diffusion processes of different devices. In addition, the etch back process can be performed in at least two stages. The first stage can be directed to etching down through the dummy material. At the same time, a protective passivation layer can be formed on the sidewalls of the recess to prevent unintended lateral etching. The second stage can form another protective passivation layer at the bottom of the recess. This layer acts as a barrier to stop further etching down of the dummy material, and the second stage can include removing residual dummy material on the gate spacers.

[0057] Specifically, FIGS. 2A-8B A selective diffusion process for the top transistors of a C-FET is illustrated. FIGS. 9-16B A selective diffusion process for the bottom transistors of a C-FET is illustrated. This method can provide flexibility in adjusting transistor characteristics depending on their location within the C-FET structure. In some embodiments, multiple C-FETs within a semiconductor structure can undergo different diffusion processes (see FIGS. 22-33C ). For example, one C-FET can have a dopant diffused into the high-k dielectric layer of its top transistors, while another C-FET in the same structure can have a diffusion in its bottom transistors. In addition, FIGS. 17-21C An embodiment is illustrated in which a dopant is diffused into both the top and bottom transistors of a C-FET.

[0058] Reference is made to FIG. 1 . FIG. 1According to some embodiments, a three-dimensional view schematic of a complementary field effect transistor is illustrated. The complementary field effect transistor includes a plurality of vertically stacked nanosheet field effect transistors. For example, a complementary field effect transistor can include a lower nanosheet field effect transistor of a first device type (e.g., n-type / p-type) and an upper nanosheet field effect transistor of a second device type (e.g., p-type / n-type) opposite (or the same as) the first device type. Specifically, the complementary field effect transistor can include a lower p-type metal-oxide-semiconductor field-effect transistor (PMOS) and an upper n-type metal-oxide-semiconductor field-effect transistor (NMOS), or the complementary field effect transistor can include a lower n-type metal-oxide-semiconductor field-effect transistor and an upper p-type metal-oxide-semiconductor field-effect transistor. Each nanosheet field effect transistor includes epitaxial layer 124a and epitaxial layer 124b as channel regions. Epitaxial layer 124a and epitaxial layer 124b can be nanosheets, nanowires, etc. Isolation layer 121 can be formed to separate and electrically isolate the upper epitaxial layer 124b from the lower epitaxial layer 124a. High-k dielectric layer 182 is formed along the top surface, sidewalls, and bottom surface of epitaxial layer 124a / 124b. Metal gate electrode 188 is formed over high-k dielectric layer 182 and around epitaxial layer 124a / 124b. Source / drain epitaxial structures 160 and 165 are disposed on opposite sides of metal gate electrode 188. Source / drain epitaxial structures 160 / 165 can be referred to individually or collectively as source or drain, depending on the context.

[0059] Reference is made to FIGS. 2A-8B . FIGS. 2A-8B Schematic views of intermediate stages of fabricating a complementary field effect transistor are illustrated, according to some embodiments. FIG. 2A 、 FIG. 3 、 FIG. 4 、 FIG. 5A 、 FIG. 6 、 FIG. 7 and FIG. 8A Cross-sectional views of similar cross-sections along FIG. 1 Reference is made to FIG. 2B and FIG. 8B Cross-sectional views taken along lines B1-B1’ (as indicated by FIG. 2A and FIG. 8A ). FIG. 5B Cross-sectional views taken along lines B2-B2’ (as indicated byFIG. 5A a cross-sectional view taken along line 10-10 (shown in FIG. 1).

[0060] Referring to FIG. 2A and FIG. 2B A multilayer stack structure 120 is formed on the substrate 110. In some embodiments, the substrate 110 can include germanium (Ge), silicon germanium (SiGe), III-V materials, the like, or a combination thereof. The multilayer stack structure 120 includes epitaxial layers (or sacrificial layers) 122a and 122b of a first composition, separated by epitaxial layers (or sacrificial layers) 124a and 124b of a second composition (different from the first composition). The multilayer stack structure 120 further includes an isolation layer 121. The isolation layer 121 can be made of an insulating material such as SiO2, SiN, SiOCN, etc. In some embodiments, the carbon atom concentration of the isolation layer 121 can be less than about 6%. The isolation layer 121 can be deposited by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The epitaxial layers 124a and 124b can also be referred to as channel regions, channel layers, channel patterns, semiconductor sheets, or semiconductor nanostructures. In some embodiments, the epitaxial layers 122a and 122b can be epitaxially grown silicon germanium layers, and the epitaxial layers 124a and 124b can be epitaxially grown silicon layers.

[0061] A fin structure 125 extending from the substrate 110 is formed. In various embodiments, the fin structure 125 includes a raised portion 112 formed from the substrate 110 and the multilayer stack structure 120 (including the epitaxial layers 122a, 122b, 124a, 124b, and the isolation layer 121). An isolation structure 130 can be formed to surround the raised portion 112. The isolation structure 130 can include a dielectric material such as silicon dioxide (SiO2), and can be formed using a method such as flowable chemical vapor deposition (FCVD), spin coating, etc.

[0062] A dummy gate structure 150 can be formed on the substrate 110 and partially covering the fin structures 125. The dummy gate structure 150 can include a dummy gate dielectric layer 152, a dummy gate electrode layer 154, and a hard mask layer 156. In some embodiments, the dummy gate dielectric layer 152 can be made of a dielectric material such as silicon dioxide (Si02), silicon nitride (SiN), etc. In some embodiments, the dummy gate electrode layer 154 can include polycrystalline-silicon (poly-Si), etc. The portion of the fin structures 125 underneath the dummy gate structure 150 can be referred to as the channel region. The dummy gate structure 150 can also define the source / drain regions of the fin structures 125.

[0063] A gate spacer 158 can be formed on the sidewalls of the dummy gate structure 150. The gate spacer 158 can include a dielectric material such as silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, etc., and / or combinations thereof. The exposed portions of the fin structures 125 (e.g., in the source / drain regions of the fin structures 125) can be etched using, for example, an anisotropic etching process (using the dummy gate structure 150 and the gate spacer 158 as etching masks) to form a recess Rl. Subsequently, lateral or horizontal recessing of the epitaxial layers 122a and 122b can be performed using appropriate etching techniques to form a lateral recess R2. The recess R2 can be filled with an inner dielectric spacer 159. The spacer material can include, for example, Si02, SiN, SiC, SiON, SiCN, or SiOCN, etc., and can be formed by appropriate deposition methods such as atomic layer deposition.

[0064] Subsequently, a first source / drain epitaxial structure 160 can be formed at the bottom of the recess Rl and connected to the epitaxial layer 124a. An interlayer dielectric (ILD) layer 174 can be formed on the substrate 110. In some embodiments, a contact etch stop layer (CESL) 172 can also be formed prior to the formation of the ILD layer 174. In some examples, the CESL 172 can be made of a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, etc., and can have a different etching selectivity than the ILD layer 174. In some embodiments, the CESL 172 and the ILD layer 174 can be collectively referred to as an isolation structure 170.

[0065] A second source / drain epitaxial structure 165 is formed on the isolation structure 170. The second (and / or first) source / drain epitaxial structure 165 can be formed by performing an epitaxial growth process of an epitaxial material provided on the isolation structure 170. In some embodiments, the second (and / or first) source / drain epitaxial structure 165 (and / or 160) can include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The second (and / or first) source / drain epitaxial structure 165 (and / or 160) can be doped by introducing a dopant species including a p-type dopant (such as boron or BF2), an n-type dopant (such as phosphorus or arsenic), and / or other suitable dopants including combinations thereof. In some embodiments, the first source / drain epitaxial structure 160 and / or the second source / drain epitaxial structure 165 can be interchangeably referred to as a source / drain pattern or an epitaxial pattern. A dielectric layer 178 is formed on the substrate 110. In some embodiments, a contact etch stop layer 176 is formed prior to forming the dielectric layer 178. In some embodiments, the contact etch stop layer 176 and the dielectric layer 178 are substantially similar to the contact etch stop layer 172 and the dielectric layer 174 in terms of materials and fabrication methods.

[0066] Referring to FIG. 3 First, dummy gate dielectric layer 152, dummy gate electrode layer 154, and hard mask layer 156 are removed, and then epitaxial layer (i.e., sacrificial layer) 122a and epitaxial layer (i.e., sacrificial layer) 122b are removed. The resulting structure is as shown in FIG. 3

[0067] Referring to FIG. 4 An interfacial layer 181 is formed around epitaxial layer 124a and epitaxial layer 124b, and a high-k dielectric layer 182 is formed on the interfacial layer 181. Specifically, the interfacial layer 181 can include an oxide layer such as a silicon dioxide layer, which is formed by a thermal oxidation process or a chemical oxidation process to oxidize surface portions of epitaxial layer 124a and epitaxial layer 124b as well as the raised portions 112. Subsequently, the high-k dielectric layer 182 is deposited on the interfacial layer 181. The high-k dielectric layer 182 can be formed of a high-k material such as hafnium oxide (Hf02), zirconium oxide (Zr02), titanium oxide (Ti02), and the like. In some embodiments, the high-k dielectric layer 182 can be formed using an atomic layer deposition process or a chemical vapor deposition process.

[0068] ​Subsequently, a barrier layer 184 is conformally formed on the high-k dielectric layer 182 and fills into the space S1. After the barrier layer 184 is formed, a dipole layer 186 (see FIG. 7 ) can be deposited on the barrier layer 184. The function of the barrier layer 184 is to prevent the dipole dopants in the dipole layer 186 from diffusing into the underlying high-k dielectric layer 182 (see FIG. 7 ). In some embodiments, the barrier layer 184 is made of a different material than the high-k dielectric layer 182 and the dipole layer 186 (see FIG. 7 ). For example and without limitation, the barrier layer 184 can include AI2O3, HfO2, ZrO2, La2O3, other suitable materials, or combinations thereof. In some embodiments, the barrier layer 184 can include TiN, TaN, TaC, combinations thereof, or multiple layers. In some embodiments, the barrier layer 184 is formed using an atomic layer deposition process or a chemical vapor deposition process.

[0069] Subsequently, a dummy material 190 is deposited on the substrate 110 and fills into the gate trench GT. For example and without limitation, the dummy material 190 can be formed of a bottom antireflective coating (BARC). In some embodiments, the dummy material 190 can be a low-k material, such as SiO2, SiN, SiC, SiON, SiCN, or SiOCN, and can be formed by a suitable deposition method, such as an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process. In some embodiments, the carbon atom concentration of the dummy material 190 can be greater than about 3%. In some embodiments, the dummy material 190 can be alternatively referred to as a sacrificial layer.

[0070] Subsequently, a patterned mask layer 192 is formed on the dummy material 190 and has an opening O1 to expose the barrier layer 184 located under the dummy material 190 to be patterned. In some embodiments, the mask layer 192 is formed by spin-coating a resist material (e.g., the mask layer 192 can also be referred to as a photoresist layer). For example and without limitation, the thickness T1 of the mask layer 192 ranges from about 2 to 15 nm. After the mask layer 192 is formed on the dummy material 190, the mask layer 192 is patterned as shown in FIG. 4 .

[0071] Reference is made to FIG. 4 , FIG. 5A , and FIG. 5B . FIG. 4 , FIG. 5A , and FIG. 5BA stage of performing an etch-back process P1 of dummy material 190 to form a recess R3 is illustrated. The etch-back process P1 is performed to expose the barrier layer 184 overlying the epitaxial layer 124b. Once exposed, the barrier layer 184 is then removed (see FIG. 6 ) to expose the high-k dielectric layer 182 located over the epitaxial layer 124b. This step is to facilitate the subsequent driving of the dipole dopant into the high-k dielectric layer 182 (see FIG. 7 ).

[0072] The etch-back process P1 can be performed in two different stages. The first stage of the etch-back process P1 can be seen in FIG. 4 . In this stage, the etch-back process P1 etches down against the dummy material 190. At the same time, a passivation layer 185a (see FIG. 4 ) can be selectively formed on the sidewall of the recess R3. The passivation layer 185a can prevent the etch-back process P1 from accidentally etching into the structure underneath the patterned mask layer 192.

[0073] The second stage of the etch-back process P1 can be seen in FIG. 5A and FIG. 5B . In this subsequent stage, the etch-back process P1 continues and focuses on forming another passivation layer 185b at the bottom of the recess R3. The passivation layer 185b can act as a stop layer to prevent the etching down of the dummy material 190. At the same time, this stage also involves removing the remaining portion 190r (see FIG. 5B ) of the dummy material 190 formed over the barrier layer 184. Removing these residual dummy material 190 can ensure that the subsequent barrier layer removal process (see FIG. 6 ) can be performed unobstructed, thereby avoiding interference with the removal of the barrier layer 184.

[0074] Referring to FIG. 4 . The etch-back process P1 against the dummy material 190 can be managed by controlling the duration of the process. This control is to ensure that the etching can be stopped at a predetermined level, such that the top surface of the dummy material 190 after etching back can be aligned with the isolation layer 121 (see FIG. 2BAlignment. In some embodiments, the etch-back process P1 can be performed using plasma processing equipment. In some embodiments, the first stage of the etch-back process P1 can be an anisotropic dry etching process (e.g., reactive-ion etching (RIE) or atomic layer etching (ALE)) that removes more material in one direction (e.g., the vertical direction) than in other directions. For example, but not limited to, the etch-back process P1 can use etching gases such as oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, CH3F and / or C4F8), chlorine-containing gases (e.g., Cl2 and / or BCl3), bromine-containing gases (e.g., HBr), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof.

[0075] The etch-back process P1 may include adjusting the relative power levels of a DC power supply and a bias power supply, which are supplied by the DC source power supply and the RF power supply of the plasma processing apparatus and applied to the substrate 110 during the etch-back process P1 to achieve the desired etch profile. By controlling the DC power supply and the bias power supply, the etch-back process P1 can allow selective etching on the substrate 110, resulting in anisotropic etching behavior. In the etch-back process P1, plasma is used to remove material from the substrate 110 by bombardment with ions or radicals. In some embodiments, the plasma processing apparatus 10 may include an inductively coupled plasma (ICP) as the plasma source and the RF power supply as the bias power supply. An inductively coupled plasma coil located above the substrate 110 is connected to the DC source power supply 26. A base assembly located below the substrate 110 is connected to the RF power supply providing the bottom bias power supply.

[0076] During the etch-back process P1, there is a potential risk of etch damage to the structure beneath the patterned mask layer 192. This risk may occur when the dummy material 190 is etched in the Y direction. To address this issue, a passivation layer 185a can be selectively formed on the sidewalls of the groove R3 as a protective barrier during the etching of the dummy material 190. The formation of the passivation layer 185a may include the introduction of a precursor 185c (see...). FIG. 4). In some embodiments, the precursor 185c can include a carbon-containing precursor, such as a hydrocarbon (CH4). This precursor 185c can readily adsorb onto the dummy material 190 (and / or the masking layer 192), facilitating the formation of the passivation layer 185a. This precursor 185c can deposit or adhere less (or not) to the barrier layer 184. In some embodiments, the precursor 185c can decompose into reactive species (e.g., radicals) and adsorb onto the dummy material 190 (and / or the patterned masking layer 192). The precursors 185c have an affinity for other carbon-containing materials. When the precursors 185c encounter a carbon-rich surface, they tend to adhere due to this affinity, thereby minimizing the overall energy of the system. In some embodiments, the recess R3 can have a depth T2, measured from the top surface of the masking layer 192 to the bottom of the recess R3. For example and without limitation, the depth can be in the range of about 100 to 160 nm, such as about 100, 110, 120, 130, 140, 150, or 160 nm.

[0077] In the etch-back process PI, the passivation layer 185a can form at the bottom of the recess R3 before reaching the predetermined depth. If this occurs, it can hinder the etching process, preventing the dummy material 190 from further descending to the predetermined depth. To address this issue, the method can include adjusting the radio frequency (RF) bias intensity during the first phase thereof. By increasing the RF bias intensity, the bombardment capability of the ion plasma can be enhanced compared to the settings used later in the etch-back process PI (see FIG. 5A and FIG. 5B ). This enhanced ion bombardment can be directed downward, effectively removing the unintended passivation layer that can form at the bottom of the recess R3. Thus, during the first phase of the etch-back process PI, the passivation layer 185a can form on the sidewalls of the recess R3, rather than at the bottom thereof, allowing the etching process to proceed unimpeded to the predetermined depth. Along with the RF bias, increasing the RF bias can require decreasing the plasma power (e.g., direct current power) to prevent over-etching or damage to the substrate 110. The RF bias can control the energy and directionality of the ions in the plasma. The direct current power can control the generation and maintenance of the plasma itself, affecting the density and characteristics of the plasma.

[0078] Further, during the first phase of the etch-back process PI, the concentration of the precursor 185c can be higher near the top surface of the patterned masking layer 192 than at lower locations. This higher concentration can result in more of the precursor 185c being deposited and adsorbed on the top surface of the patterned masking layer 192. This can help maintain the integrity of the masking layer 192. In some embodiments, the thickness of the passivation layer 185a remaining on the patterned masking layer 192 can tend to be thicker than on the sidewalls of the recess R3.

[0079] In some embodiments, for devices with wider gate trenches GT, a faster etch rate can result in unintended exposure of epitaxial layer 124a. Conversely, for devices with narrower gate trenches GT, a slower etch rate can mean that epitaxial layer 124b is not exposed after the same etch duration. Thus, FIG. 4 The method disclosed herein can be implemented by controlling the DC power and RF power during the first phase of the etch-back process P1 by periodically turning on and off the bias power and the DC power simultaneously. Specifically, during the period when both the bias power and the DC power are turned off, the etching gas in the etch-back process P1 can be more evenly distributed across the wide and narrow gate trenches GT. This even distribution can allow a more uniform interaction between the etching gas and the dummy material 190, regardless of the gate width size and different areas on the wafer. Subsequently, when the bias power and the DC power are reactivated, the etch-back process P1 can resume a more balanced etch rate across all the gate trenches GT, regardless of their gate width and different areas on the wafer. This method can ensure that the etch rate of the dummy material 190 in the wide and narrow gate trenches GT is closer, resulting in uniform recess R3 depth across different devices, and thus ensuring the consistency of device performance and reliability across the semiconductor wafer.

[0080] During the etch-back process P1, the processing parameters can be adjusted to achieve etch control. In some embodiments, the source power of the etch-back process P1 can be set in the range of about 600 to 1000 W, such as about 600, 650, 700, 750, 800, 850, 900, 950, or 1000 W. This source power is coupled with a pulse frequency of about 80 to 120 Hz, such as about 80, 85, 90, 95, 100, 105, 110, 115, or 120 Hz, and a duty cycle of about 40-60%, such as about 40, 45, 50, or 60%. Such source power setting can ensure sufficient energy to generate plasma, while the pulse frequency and duty cycle can help manage plasma density and energy distribution to achieve controlled etching. In some embodiments, the bias power of the etch-back process P1 can be set in the range of about 20 to 60 W, such as about 20, 25, 30, 35, 40, 45, or 60 W. This bias power is also coupled with a pulse frequency of about 80 to 120 Hz, such as about 80, 85, 90, 95, 100, 105, 110, 115, or 120 Hz, and a duty cycle of about 40-60%, such as about 40, 45, 50, or 60%. Such bias power setting can ensure sufficient ion energy and directionality for etching, and can help fine-tune the etch profile.

[0081] In some embodiments, the etch-back process P1 can be performed at a pressure range of about 5-30 mTorr (mT), such as about 5, 10, 15, 20, 25, or 30 mT. The gas composition of the etch-back process P1 can include argon (Ar), nitrogen (N2), and hydrogen (H2). For example and without limitation, argon can be provided at a flow rate range of about 20 to 70 mL / min, such as about 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, or 70 mL / min. Nitrogen can be provided at a flow rate range of about 100 to 300 mL / min, such as about 100, 120, 140, 160, 180, 200, 220, 240, 260, 280, or 300 mL / min. Hydrogen can be provided at a flow rate range of about 500 to 1000 mL / min, such as about 500, 600, 700, 800, 900, or 1000 mL / min. These settings in the first stage of the etch-back process P1 ensure precise etching, minimizing damage to the underlying structure, while achieving the desired etch depth and profile.

[0082] As shown in FIG. 1C, in the second stage of the etch-back process P1, the remaining dummy material 190 over the barrier layer 184 can be removed. In addition, in the second stage of the etch-back process P1, the passivation layer 185b can be selectively formed at the bottom of the recess R3, while facilitating etching of the remaining dummy material over the barrier layer 184. This process can involve reducing the strength of the RF bias, or turning off the bias power completely, thereby allowing the downward bombardment capability of the ion plasma to be reduced. As a result, the passivation layer 185b can be formed at the bottom of the recess R3 without being etched completely by the ion plasma. After the passivation layer 185b is formed at the bottom of the recess R3, the ion plasma can hit the passivation layer 185b at an oblique angle, effectively bouncing upward. FIG. 5A FIG. 5B Referring to FIG. 1D, an etch process can be performed to remove the barrier layer 184 exposed from the passivation layer 185a and the passivation layer 185b, to expose the underlying high-k dielectric layer 182. In some embodiments, the etch process is performed by wet etching. For example, the wet etching chemistry can include an acid, such as HC1, H2SO4, H2CO3, HF, etc. Subsequently, the dummy material 190, the mask layer 192, the passivation layer 185a, and the passivation layer 185b can be removed.

[0083] Referring to FIG. 1D, an etch process can be performed to remove the barrier layer 184 exposed from the passivation layer 185a and the passivation layer 185b, to expose the underlying high-k dielectric layer 182. In some embodiments, the etch process is performed by wet etching. For example, the wet etching chemistry can include an acid, such as HC1, H2SO4, H2CO3, HF, etc. Subsequently, the dummy material 190, the mask layer 192, the passivation layer 185a, and the passivation layer 185b can be removed. FIG. 6 Referring to FIG. 1D, an etch process can be performed to remove the barrier layer 184 exposed from the passivation layer 185a and the passivation layer 185b, to expose the underlying high-k dielectric layer 182. In some embodiments, the etch process is performed by wet etching. For example, the wet etching chemistry can include an acid, such as HC1, H2SO4, H2CO3, HF, etc. Subsequently, the dummy material 190, the mask layer 192, the passivation layer 185a, and the passivation layer 185b can be removed.

[0084] FIG. 7 ​​The dipole layer 186 can be deposited on the substrate 110 by a deposition process. The dipole layer 186 can be formed by a conformal deposition process such as an atomic layer deposition process or a chemical vapor deposition process. The dipole layer 186 can include a dipole dopant such as lanthanum, aluminum, yttrium, titanium, magnesium, niobium, gallium, indium, etc. These elements, when diffused into the high-k dielectric layer 182, can increase the number of dipoles and cause a corresponding change in threshold voltage (Vt) of the complementary field effect transistor. The dipole layer 186 can be an oxide and / or nitride of the dipole dopant. For example, a lanthanum-containing dipole layer 186 can be in the form of lanthanum oxide (La203), lanthanum nitride (LaN), etc., or a combination thereof. An aluminum-containing dipole layer 186 can be in the form of aluminum oxide (Al203), aluminum nitride (AIN), etc., or a combination thereof.

[0085] A drive-in anneal process P2 is performed. The anneal temperature of the anneal process P2 can be between about 500 and 950 °C. The result of the anneal can cause the dipole dopant to be driven into the high-k dielectric layer 182. The high-k dielectric layer 182 has a portion doped with the dipole dopant and this portion can be referred to as the high-k dielectric layer 182’ (containing the dipole dopant). Thus, selective diffusion of the dipole dopant into the high-k dielectric layer 182 of the complementary field effect transistor can be achieved. The high-k dielectric layer 182’ can be located in the top transistor 196b (see FIG. 8A ) of the complementary field effect transistor. At the same time, the high-k dielectric layer 182 of the bottom transistor 196a in the same complementary field effect transistor can not be doped with the dipole dopant (or doped with a different dopant). In other words, the high-k dielectric layer 182 of the bottom transistor 196a in the same complementary field effect transistor can be free of the dipole dopant. In some embodiments, the high-k dielectric layer 182’ in the top transistor 196b can have a higher atomic concentration of the dipole dopant than the high-k dielectric layer 182 in the bottom transistor 196a. This selective doping can change the threshold voltage of the top transistor 196b to be different from that of the bottom transistor 196a.

[0086] In addition, the partial diffusion of the dipole dopant into the high-k dielectric layer 182 can make the threshold voltage of the transistor tunable, thereby facilitating the formation of a transistor with a particular electrical property, such as p-type or n-type. In some embodiments, the metal gate electrode 188 of the top transistor 196b (see FIG. 8A ) and the bottom transistor 196a (see FIG. 8A ) in the same complementary field effect transistor can be made of the same material. In some embodiments, the metal gate electrode 188 of the top transistor 196b and the bottom transistor 196a in the same complementary field effect transistor can use different materials.

[0087] refer to FIG. 8A and FIG. 8B After the drive-in annealing process P2, the dipole layer 186 is removed in the etching process. In some embodiments, the etching process is performed by wet etching. In some embodiments, such as FIG. 6 As shown, the exposed barrier layer 184 can be removed by an etching process, which can be referred to in the preceding figures and related descriptions. Subsequently, a metal gate electrode 188 is deposited on the high-dielectric-constant dielectric layer 182 and the high-dielectric-constant dielectric layer 182', filling the gate trench GT and the space S1. The metal gate electrode 188 may include a working function metal layer and / or fill metal formed around the epitaxial layers 124a and 124b. In some embodiments, the metal gate electrode 188 may include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials. Thus, a gate structure 180 can be formed. The gate structure 180 may include an interface layer 181, high-dielectric-constant dielectric layers 182 / 182', and a metal gate electrode 188. In some embodiments, the gate structure 180 may be alternately referred to as a metal gate, a gate pattern, or a gate stripe.

[0088] Therefore, a semiconductor structure 100 can be formed, including a bottom transistor 196a and a top transistor 196b located above the bottom transistor 196a. The bottom transistor 196a may include an epitaxial layer 124a, a first source / drain epitaxial structure 160 located opposite to the epitaxial layer 124a and connected to the epitaxial layer 124a, and a gate structure 180 surrounding the epitaxial layer 124a. The top transistor 196b may include an epitaxial layer 124b, a first source / drain epitaxial structure 165 located opposite to the epitaxial layer 124b and connected to the epitaxial layer 124b, and a gate structure 180 surrounding the epitaxial layer 124b.

[0089] refer to FIGS. 9-16B picture. FIGS. 9-16B The figure illustrates a cross-sectional view of an intermediate stage in the fabrication of a complementary field-effect transistor according to some embodiments. FIG. 9 The previous steps can correspond to FIGS. 2A-3 The steps are illustrated in the diagram. FIG. 9 In this context, the substrate 210, the protrusion 212, the isolation layer 221, the epitaxial layers 224a and 224b, the isolation structure 230, the gate spacer 258, the internal dielectric spacer 259, the source / drain epitaxial structure 260 and 265, and the isolation structure 270 and 275 can correspond to... FIGS. 2A-3substrate 110, raised regions 112, isolation layer 121, epitaxial layers 124a and 124b, isolation structure 130, gate spacers 158, inner dielectric spacers 159, source / drain epitaxial structures 160 and 165, and isolation structures 170 and 175.

[0090] FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 , FIG. 14 , FIG. 15 and FIG. 16A illustrate cross-sectional views taken along lines B4-B4’ as indicated in FIG. 1 . FIG. 16B illustrate cross-sectional views taken along lines B4-B4’ as indicated in FIG. 16A .

[0091] Referring to FIG. 9 . An interface layer 281 is formed around epitaxial layer 224a and epitaxial layer 224b, and a high-k dielectric layer 282 is formed on interface layer 281. Subsequently, a dipole layer 286 is conformally formed on high-k dielectric layer 282 and fills into space S2 between adjacent epitaxial layers 224a and 224b. In some embodiments, interface layer 281, high-k dielectric layer 282 and dipole layer 286 can correspond to interface layer 181, high-k dielectric layer 182 and dipole layer 186 in FIG. 4 and FIG. 7 .

[0092] Referring to FIG. 10 . A dummy material 290a is deposited on substrate 210 and fills into gate trench GT2. A patterned mask layer 292a with openings O2 is formed on dummy material 290a to expose dipole layer 286 to be patterned under dummy material 290a. In some embodiments, dummy material 290a and mask layer 292a can correspond to dummy material 190 and mask layer 192 in FIG. 4 .

[0093] Referring to FIG. 10 and FIG. 11 . FIG. 10 and FIG. 11 illustrate stages of performing a re-etch process P3 on dummy material 290a to form a recess R4, thereby exposing dipole layer 286. Re-etch process P3 can be performed in two different stages similar to re-etch process P1 (see FIGS. 4-5B ). That is, re-etch process P3 can correspond to re-etch process P1 and can refer to the previous figures and related descriptions. In particular, the first stage of re-etch process P3 can be performed in a manner similar to the first stage of re-etch process P1. That is, the first stage of re-etch process P3 can be performed to remove a portion of dipole layer 286 and a portion of high-k dielectric layer 282, thereby forming a recess R4 in dipole layer 286 and a portion of high-k dielectric layer 282. FIG. 10The second phase of the etch-back process P3 can be illustrated in FIG. 10 ). The formation of the passivation layer 285a can include the introduction of a precursor 285c (see FIG. 10 ) during the etch-back process P3. The precursor 285c is less (or not) deposited or adhered to the dipole layer 286. In some embodiments, the precursor 285c can correspond to the previous precursor 185c.

[0094] The second phase of the etch-back process P3 can be illustrated in FIG. 11 . In this subsequent phase, the etch-back process P3 continues and focuses on forming another passivation layer 285b at the bottom of the recess R4. The passivation layer 285b can act as a stop layer to prevent the down-etching of the dummy material 290a. Meanwhile, this phase also includes removing the remaining dummy material 290a formed on the dipole layer 286. The removal of these residual dummy material 290a can ensure that the subsequent dipole layer removal process (see FIG. 12 ) can be performed without hindrance. In some embodiments, the depth T4 of the recess R4 can be measured from the top surface of the mask layer 292a to the bottom of the recess R4, as shown in the depth T2. FIG. 4

[0095] Referring to FIG. 12 , an etching process is performed to remove the dipole layer 286 exposed from the passivation layer 285a and the passivation layer 285b to expose the high-k dielectric layer 282. In some embodiments, the etching process is performed by wet etching. Subsequently, the dummy material 290a, the mask layer 292a, the passivation layer 285a, and the passivation layer 285b can be removed.

[0096] Referring to FIG. 13 . A dummy material 290b is deposited on the substrate 210 and filled into the gate trench GT2. A patterned mask layer 292b with an opening O3 is formed on the dummy material 290b to expose the dipole layer 286 located underneath the dummy material 290b to be patterned. In some embodiments, the dummy material 290b and the mask layer 292b can correspond to the dummy material 190 and the mask layer 192 in FIG. 4 .

[0097] An etch-back process P4 is performed on the dummy material 290b to form a recess R5 to expose the dipole layer 286. The etch-back process P4 can be similar to the etch-back process P1 (see FIGS. 4-5B ​) are performed in two different stages. That is, the etch back process P4 can correspond to the etch back process P1 and can refer to the previous figures and related descriptions. Specifically, the first stage of the etch back process P4 is directed to the dummy material 290b for etching down. Meanwhile, a passivation layer 285d (see FIG. 13 ) can be selectively formed on the sidewalls of the recess R5. The passivation layer 285d can prevent the etch back process P4 from accidentally etching to the structure underneath the patterned hardmask layer 292b. The formation of the passivation layer 285d can include introducing a precursor 285e (see FIG. 13 ) during the etch back process P4. In some embodiments, the precursor 285e can correspond to the previous precursor 185c. The second stage of the etch back process P4 can include removing the remaining dummy material 290b formed on the dipole layer 286. Removing these residual dummy material 290b can ensure that the subsequent dipole layer removal process (see FIG. 14 ) can be performed without hindrance. As shown in FIG. 13 , after the etch back process P4, the exposed dipole layer 286 can be removed by an etching process as shown in FIG. 12 , which can refer to the previous figures and related descriptions.

[0098] Referring to FIG. 14 , an etching process is performed to remove the dipole layer 286 exposed from the passivation layer 285d to expose the high-k dielectric layer 282. In some embodiments, the etching process is performed by wet etching. Subsequently, the dummy material 290b, the mask layer 292b, and the passivation layer 285d can be removed.

[0099] Referring to FIG. 15 , a drive-in anneal process P5 is performed. In some embodiments, the anneal process P5 can correspond to the drive-in anneal process P2 and can refer to the previous figures and related descriptions. The anneal results in the dipole dopant being driven into the high-k dielectric layer 282. The high-k dielectric layer 282 has a portion doped with the dipole dopant, and this portion can be referred to as the high-k dielectric layer 282’ (containing the dipole dopant).

[0100] Thus, the selective diffusion of the dipole dopant in the high-k dielectric layer 282 of the complementary field effect transistor can be achieved. The high-k dielectric layer 282’ can be located in the bottom transistor 296a (see FIG. 16A ) of the complementary field effect transistor. Meanwhile, the high-k dielectric layer 182 of the top transistor 296b in the same complementary field effect transistor can not be doped with the dipole dopant (or doped with a different dopant). In some embodiments, the dipole dopant atomic concentration of the high-k dielectric layer 282’ in the bottom transistor 296a can be higher than the high-k dielectric layer 282 in the top transistor 296b. As shown in FIG. 16A andFIG. 16B As shown, after the drive-in anneal process P5, the exposed dipole layer 286 can be removed by an etch process, which can be referenced to the previous figures and related descriptions. FIG. 12 As shown, the exposed dipole layer 286 can be removed by an etch process, which can be referenced to the previous figures and related descriptions.

[0101] Referring to FIG. 16A and FIG. 16B A metal gate electrode 288 is deposited on the high-k dielectric layer 282 and the high-k dielectric layer 282' and fills into the gate trench GT2 and the space S2. In some embodiments, the metal gate electrode 288 can correspond to the metal gate electrode 188 as shown in FIG. 1C. As such, a gate structure 280 can be formed. The gate structure 280 can include the interface layer 281, the high-k dielectric layer 282 / 282', and the metal gate electrode 288. Accordingly, the semiconductor structure 200 can be formed, including the bottom layer transistor 296a and the top layer transistor 296b located above the bottom layer transistor 296a. FIG. 8A and FIG. 8B As such, a gate structure 280 can be formed. The gate structure 280 can include the interface layer 281, the high-k dielectric layer 282 / 282', and the metal gate electrode 288. Accordingly, the semiconductor structure 200 can be formed, including the bottom layer transistor 296a and the top layer transistor 296b located above the bottom layer transistor 296a.

[0102] Referring to FIGS. 17-21C . FIGS. 17-21C Cross-sectional views of manufacturing intermediate stages of a complementary field effect transistor according to some embodiments are illustrated. FIG. 17 The previous steps can correspond to the steps illustrated in FIGS. 2A-3 In FIG. 17 , the substrate 310, the raised regions 312, the isolation layers 321, the epitaxial layers 324a and 324b, the isolation structures 330, the gate spacers 358, the inner dielectric spacers 359, the source / drain epitaxial structures 360, the source / drain epitaxial structures 365, the isolation structures 370, and the isolation structures 375 can correspond to the substrate 110, the raised regions 112, the isolation layers 121, the epitaxial layers 124a and 124b, the isolation structures 130, the gate spacers 158, the inner dielectric spacers 159, the source / drain epitaxial structures 160, the source / drain epitaxial structures 165, the isolation structures 170, and the isolation structures 175 in FIGS. 2A-3

[0103] FIG. 17 , FIG. 18 , FIG. 19 , FIG. 20 , FIG. 21A Cross-sectional views along similar cross-sectional views along the reference section A-A' in FIG. 1 FIG. 21B Cross-sectional views along the line B8-B8' as indicated in FIG. 21A FIG. 21C Cross-sectional views along the line B9-B9' as indicated in FIG. 21A

[0104] ​​​​Reference is made to FIG. 1 1 A, which shows a cross-sectional view of a substrate 310 after a deposition process P5. In some embodiments, the substrate 310 can correspond to the substrate 10 of FIG. 1, and the deposition process P5 can correspond to the deposition process P1 of FIG. 1. The deposition process P5 is performed to fill the gate trench GT3 with a dummy material 390. In some embodiments, the dummy material 390 can correspond to the dummy material 190 of FIG. 1, and can be formed of a material that is later removed, such as a photoresist material. FIG. 17 An interface layer 381 is formed around the epitaxial layer 324a and the epitaxial layer 324b, and a high-k dielectric layer 382 is formed on the interface layer 381. Subsequently, a dipole layer 386 is conformally formed on the high-k dielectric layer 382 and fills into the space S3 between the adjacent epitaxial layer 324a and the epitaxial layer 324b. In some embodiments, the interface layer 381, the high-k dielectric layer 382, and the dipole layer 386 can correspond to the interface layer 181, the high-k dielectric layer 182, and the dipole layer 186 of FIG. 1, respectively. FIG. 4 and FIG. 7 of FIG. 1.

[0105] Reference is made to FIG. 1 1 A, which shows a cross-sectional view of a substrate 310 after a deposition process P5. In some embodiments, the substrate 310 can correspond to the substrate 10 of FIG. 1, and the deposition process P5 can correspond to the deposition process P1 of FIG. 1. The deposition process P5 is performed to fill the gate trench GT3 with a dummy material 390. In some embodiments, the dummy material 390 can correspond to the dummy material 190 of FIG. 1, and can be formed of a material that is later removed, such as a photoresist material. FIG. 18 In some embodiments, the dummy material 390 and the mask layer 392 can correspond to the dummy material 190 and the mask layer 192 of FIG. 1, respectively. FIG. 4

[0106] An etch-back process P6 is performed on the dummy material 390 to form a recess R6 and a recess R7 to expose the dipole layer 386. The etch-back process P6 is performed to expose the dipole layer 386 that is covered by the epitaxial layer 324a and the epitaxial layer 324b. Once exposed, this dipole layer 386 is subsequently removed (see FIG. 1 1 B), exposing the high-k dielectric layer 382 on the epitaxial layer 324a and the epitaxial layer 324b. FIG. 19

[0107] In some embodiments, the etch-back process P6 can correspond to the etch-back process P1, and reference can be made to the previous figures and related descriptions. The first stage of the etch-back process P6 is directed at the dummy material 390 to etch down. At the same time, a passivation layer 385a can be selectively formed on the sidewalls of the recess R6 and the recess R7. The passivation layer 385a can prevent the etch-back process P6 from accidentally etching into the structures under the patterned mask layer 392. Forming the passivation layer 385a can include introducing a precursor 385c during the etch-back process P6. In some embodiments, the precursor 385c can correspond to the precursor 185c previously described. The second stage of the etch-back process P6 can include removing the remaining dummy material 390 formed on the dipole layer 386. Removing these remaining dummy material 390 can ensure that the subsequent dipole removal process (see FIG. 1 1 B) can be performed without hindrance. FIG. 19

[0108] As shown in FIG. 1 1 B, after the etch-back process P6, the exposed dipole layer 386 can be removed by a dipole removal process P7. In some embodiments, the dipole removal process P7 can correspond to the dipole removal process P2 of FIG. 1, and reference can be made to the previous figures and related descriptions. FIG. 19 FIG. 12 ​​​​The illustrated etching process can be removed, which can be referred to the previous figures and related descriptions. Subsequently, dummy material 390, mask layer 392, and passivation layer 385a can be removed.

[0109] Referring to FIG. 20 , a drive-in anneal process P7 is performed. In some embodiments, anneal process P7 can correspond to drive-in anneal process P2, and can be referred to the previous figures and related descriptions. As a result of the anneal, dipole dopants can be driven into high-k dielectric layer 382. High-k dielectric layer 382 is doped with dipole dopants, and can be referred to as high-k dielectric layer 382' (containing dipole dopants). High-k dielectric layer 382' can be located in bottom transistor 396a and top transistor 396b of the CMOSFET (see FIG. 21A ). After drive-in anneal process P7, exposed dipole layer 386 can be removed by FIG. 12 the illustrated etching process, which can be referred to the previous figures and related descriptions.

[0110] Referring to FIGS. 21A-21C , metal gate electrode 388 is deposited on high-k dielectric layers 382 and 382', and fills gate trench GT3 and space S3. In some embodiments, metal gate electrode 388 can correspond to metal gate electrode 188 illustrated in FIG. 8A and FIG. 8B . In this way, gate structure 380 can be formed. Gate structure 380 can include interface layer 381, high-k dielectric layers 382 / 382', and metal gate electrode 388. Accordingly, semiconductor structure 300 can be formed, including bottom transistor 396a and top transistor 396b located above bottom transistor 396a.

[0111] Referring to FIGS. 22-33C . FIGS. 22-33C Cross-sectional views of intermediate stages of a CMOSFET fabricated according to some embodiments are illustrated. FIG. 22 The previous steps can correspond to the steps illustrated in FIGS. 2A-3 . In FIG. 22 , substrate 410, raised regions 412, isolation layer 421, epitaxial layer 424a, epitaxial layer 424b, isolation structure 430, gate spacers 458, inner dielectric spacer 459, source / drain epitaxial structure 460, source / drain epitaxial structure, isolation structure 470, and isolation structure 475 can correspond to substrate 10, raised regions 12, isolation layer 21, epitaxial layer 24a, epitaxial layer 24b, isolation structure 30, gate spacers 58, inner dielectric spacer 59, source / drain epitaxial structure 60, source / drain epitaxial structure, isolation structure 70, and isolation structure 75, respectively. FIGS. 2A-3substrate 110, raised regions 112, isolation layer 121, epitaxial layer 124a, epitaxial layer 124b, isolation structure 130, gate spacers 158, inner dielectric spacer 159, source / drain epitaxial structure 160, source / drain epitaxial structure 165, isolation structure 170, and isolation structure 175.

[0112] FIG. 22 , FIG. 23 , FIG. 24 , FIG. 25 , FIG. 26 , FIG. 27 , FIG. 28 , FIG. 29 , FIG. 30 , FIG. 31 , FIG. 32 and FIG. 33A illustrate similar cross-sectional views along FIG. 1 reference to cross-sectional line A-A'. FIG. 33B illustrate cross-sectional views taken along lines B10-B10' as indicated in FIG. 33A . FIG. 33C illustrate cross-sectional views taken along lines B11-B11' as indicated in FIG. 33A .

[0113] Referring to FIG. 22 An interface layer 481 is formed around epitaxial layer 424a and epitaxial layer 424b, and a high-k dielectric layer 482 is formed on interface layer 481. Subsequently, a barrier layer 484 is conformally formed on high-k dielectric layer 482 and fills into space S4 between adjacent epitaxial layer 424a and epitaxial layer 424b. In some embodiments, interface layer 481, high-k dielectric layer 482, and barrier layer 484 can correspond to interface layer 181, high-k dielectric layer 182, and barrier layer 184 in FIG. 4 .

[0114] Referring to FIG. 23 A dummy material 490a is deposited on substrate 410 and fills into gate trench GT4. A patterned mask layer 492a with openings O6 is formed on dummy material 490a to expose barrier layer 484 located under dummy material 490a to be patterned. In some embodiments, dummy material 490a and mask layer 492a can correspond to dummy material 190 and mask layer 192 in FIG. 4 .

[0115] Referring to FIG. 23 and FIG. 24 . FIG. 23 and FIG. 24The illustration depicts the stages of performing a back-etching process P8 on the dummy material 490a to form a groove R8 to expose the barrier layer 484. The back-etching process P8 can be performed according to a process similar to back-etching process P1 (see...). FIGS. 4-5B The etching process P8 is performed in two different stages. That is, the etching process P8 can correspond to the etching process P1, as shown in the preceding figures and related descriptions. Specifically, the first stage of the etching process P8 can be performed in two different stages. FIG. 23 The diagram is shown in the image. At this stage, the etch-back process P8 etches downwards onto the dummy material 490a. Simultaneously, a passivation layer 485a can be selectively formed on the sidewalls of the groove R8 (see diagram). FIG. 23 The passivation layer 485a prevents accidental etching of the structure beneath the patterned hard mask layer 492a during the etch-back process P8. Forming the passivation layer 485a may include introducing a precursor 485c during the etch-back process P8 (see...). FIG. 23 Precursor 485c is deposited (or not) deposited or adhered to barrier layer 484. In some embodiments, precursor 485c may correspond to the preceding precursor 185c.

[0116] The second stage of the P8 etch-back process can be performed in... FIG. 24 The diagram is shown in the image. In this subsequent stage, the etch-back process P8 continues, focusing on forming another passivation layer 485b at the bottom of the groove R8. The passivation layer 485b acts as a stop layer to prevent the dummy material 490a from being etched downwards. Simultaneously, this stage also includes removing the remaining dummy material 490a formed on the barrier layer 484. Removing these residual dummy materials 490a ensures the subsequent barrier layer 484 removal process (see diagram). FIG. 25 This can be done without hindrance. In some embodiments, the depth T8 of the groove R8 can be measured from the top surface of the masking layer 492a to the bottom of the groove R8, such as... FIG. 4 The depth T2 is shown.

[0117] like FIG. 25 As shown, after the etch-back process P8, the exposed barrier layer 484 can be... FIG. 6 The etching process shown is removed; this etching process can be referred to in the preceding figures and related descriptions. Subsequently, the dummy material 490a, mask layer 492a, passivation layer 485a, and passivation layer 485b can be removed.

[0118] refer to FIG. 26 A dummy material 490b is deposited on the substrate 410 and filled into the gate trench GT4. A patterned mask layer 492b with openings O7 is formed on the dummy material 490b to expose the barrier layer 484 to be patterned beneath the dummy material 490b. In some embodiments, the dummy material 490b and the mask layer 492b may correspond to... FIG. 4 The virtual material 190 and the masking layer 192 in the middle.

[0119] An etch back process P9 is performed on dummy material 290b to form a recess R9 to expose barrier layer 484. In some embodiments, etch back process P9 can correspond to etch back process P1 and can refer to the previous figures and related descriptions. A first stage of etch back process P9 is directed at dummy material 490b to etch down. At the same time, a passivation layer 485d can be selectively formed on the sidewalls of recess R9 (see FIG. 27 ). Passivation layer 485d can prevent etch back process P9 from accidentally etching into structures under patterned hardmask layer 492b. Forming passivation layer 485d can include introducing a precursor 485e during etch back process P6. In some embodiments, precursor 485e can correspond to previous precursor 185c. A second stage of etch back process P9 can include removing remaining dummy material 490b formed on barrier layer 484. Removing these remaining dummy material 490b can ensure that a subsequent barrier layer 484 removal process (see FIG. 27 ) can be performed without hindrance.

[0120] As shown in FIG. 27 , after etch back process P9, exposed barrier layer 484 can be removed by an etch process as shown in FIG. 6 , which can refer to the previous figures and related descriptions. Subsequently, dummy material 490b, mask layer 492b, and passivation layer 485d can be removed.

[0121] Referring to FIG. 28 , a dipole layer 486 can be deposited on substrate 410 by a deposition process. In some embodiments, dipole layer 486 can correspond to dipole layer 186 in FIG. 7 in terms of its material and fabrication method. This means that dipole layer 486 can correspond to dipole layer 186 in the previous figures.

[0122] Referring to FIG. 29 , a dummy material 490c is deposited on substrate 410 and filled into gate trench GT4. A patterned mask layer 492c with openings O8 is formed on dummy material 490c to expose dipole layer 486 located under dummy material 490c to be patterned. In some embodiments, dummy material 490c and mask layer 492c can correspond to dummy material 190 and mask layer 192 in FIG. 4 .

[0123] Referring to FIG. 29 and FIG. 30 . FIG. 29 and FIG. 30 depicts a stage of performing an etch back process P10 on dummy material 490c to form a recess R10 to expose dipole layer 486. Etch back process P10 can be performed according to a similar manner as etch back process P1 (see FIGS. 4-5B) are performed in two different stages. That is, the etch back process P10 can correspond to the etch back process P1, and can refer to the previous figures and related descriptions. Specifically, the first stage of the etch back process P10 can be illustrated in FIG. 29 . In this stage, the etch back process P10 targets the dummy material 490c for etching down. Meanwhile, a passivation layer 485f (see FIG. 29 ) can be selectively formed on the sidewall of the recess R10. The formation of the passivation layer 485f can include introducing a precursor 485h (see FIG. 29 ) during the etch back process P10. This precursor 485h is less (or not) deposited or adhered to the dipole layer 486. In some embodiments, the precursor 485h can correspond to the previous precursor 185c.

[0124] The second stage of the etch back process P10 can be illustrated in FIG. 30 . In this subsequent stage, the etch back process P10 continues and focuses on forming another passivation layer 485g at the bottom of the recess R10. The passivation layer 485g can act as a stop layer to prevent the etching down of the dummy material 490c. Meanwhile, this stage also includes removing the remaining dummy material 490c formed on the dipole layer 486. Removing these residual dummy material 490c can ensure that the subsequent dipole layer 486 removal process (see FIG. 31 ) can proceed unimpeded. In some embodiments, the depth T11 of the recess R10 can be measured from the top surface of the mask layer 492c to the bottom of the recess R10, as the depth T2 illustrated in FIG. 4 .

[0125] As illustrated in FIG. 31 , after the etch back process P10, the exposed dipole layer 486 can be removed by an etching process as illustrated in FIG. 12 , which can refer to the previous figures and related descriptions. Subsequently, the dummy material 490c, the mask layer 492c, the passivation layers 485f and 485g can be removed.

[0126] Referring to FIG. 32 , an implantation anneal process P11 is performed. In some embodiments, the anneal process P11 can correspond to the implantation anneal process P2, and can refer to the previous figures and related descriptions. The result of the anneal causes the dipole dopants to be implanted into the high-k dielectric layer 482. The high-k dielectric layer 482 is doped with the dipole dopants, and can be referred to as the high-k dielectric layer 482' (containing dipole dopants). The high-k dielectric layer 482' can be located in the bottom transistor 496a and the top transistor 496b (see FIG. 33A ) of the complementary field effect transistor. After the implantation anneal process P11, the exposed dipole layer 486 can be removed by an etching process as illustrated in FIG. 12The etch processes shown are removed, and the exposed barrier layer 484 can be removed by FIG. 6 The etch processes shown are removed, and the exposed barrier layer 484 can be removed by

[0127] Referring to FIGS. 33A-33C A metal gate electrode 488 is deposited on the high-k dielectric layers 482 and 482' and fills the gate trench GT4 and the space S4. In some embodiments, the metal gate electrode 488 can correspond to the metal gate electrode 188. Thus, a gate structure 480 can be formed. The gate structure 480 can include the interface layer 481, the high-k dielectric layers 482 / 482', and the metal gate electrode 488. Accordingly, a semiconductor structure 400 can be formed, including a bottom layer transistor 496a and a top layer transistor 496b located above the bottom layer transistor 496a. FIG. 8A and FIG. 8B The etch processes shown are removed, and the exposed barrier layer 484 can be removed by

[0128] In some embodiments, a method of fabricating a semiconductor structure includes forming a first semiconductor nanostructure over a substrate, and forming a second semiconductor nanostructure over the first semiconductor nanostructure; forming a plurality of first source / drain regions on opposite sides of the first semiconductor nanostructure, and forming a plurality of second source / drain regions on opposite sides of the second semiconductor nanostructure; forming a first high-k dielectric layer around the first semiconductor nanostructure, and forming a second high-k dielectric layer around the second semiconductor nanostructure; forming a barrier layer over the first high-k dielectric layer and the second high-k dielectric layer; depositing a dummy material over the barrier layer; performing an etching process on the dummy material to form a recess, the recess exposing a first portion of the barrier layer over the second high-k dielectric layer, while a second portion of the barrier layer over the first high-k dielectric layer is still covered by the etched dummy material; removing the first portion of the barrier layer to expose the second high-k dielectric layer; removing the dummy material; after removing the dummy material, doping a dipole dopant into the second high-k dielectric layer; and forming a gate electrode over the first high-k dielectric layer and the second high-k dielectric layer. In some embodiments, the etching process includes introducing carbon-containing radicals on the dummy material. In some embodiments, the carbon atom concentration of the dummy material is greater than about 3%. In some embodiments, performing the etching process includes selectively forming a first passivation layer on sidewalls of the recess in the dummy material when forming the recess. In some embodiments, performing the etching process includes selectively forming a second passivation layer on a bottom of the recess in the dummy material when the first portion of the barrier layer over the second high-k dielectric layer is exposed. In some embodiments, the etching process is performed using a bias power, and after forming the second passivation layer, the power level of the bias power is lower than the power level before forming the second passivation layer. In some embodiments, during the etching process, the bias power and a DC power are periodically switched, and the periodic switching of the bias power is synchronized with the periodic switching of the DC power. In some embodiments, the DC power is performed using a pulse frequency of about 80-120 Hz, and during a pulse period, the on-time of the pulse frequency of the DC power occupies 40% to 60% of the pulse period. In some embodiments, the bias power is performed using a pulse frequency of about 80-120 Hz, and during a pulse period, the on-time of the pulse frequency of the bias power occupies 40% to 60% of the pulse period. In some embodiments, doping the dipole dopant into the second high-k dielectric layer includes forming a dipole layer over the second high-k dielectric layer, the dipole layer contacting the second high-k dielectric layer; and performing an annealing process to drive the dipole dopant in the dipole layer into the second high-k dielectric layer.

[0129] In some embodiments, a method of fabricating a semiconductor structure includes forming a first channel layer and a second channel layer vertically aligned with each other over a substrate; forming a first gate dielectric layer around the first channel layer and a second gate dielectric layer around the second channel layer; forming a dipole layer over the first gate dielectric layer and the second gate dielectric layer; forming a carbon-containing material over the dipole layer; etching the carbon-containing material to form a recess that exposes a first portion of the dipole layer over the second gate dielectric layer while a second portion of the dipole layer over the first gate dielectric layer remains covered by the carbon-containing material; removing the first portion of the dipole layer to expose the second gate dielectric layer; removing the carbon-containing material; performing an anneal process to diffuse dipole dopants in the dipole layer into the first gate dielectric layer; and forming a gate electrode over the first gate dielectric layer and the second gate dielectric layer. In some embodiments, the method of fabricating a semiconductor structure further includes introducing carbon-containing hydrogen radicals onto the carbon-containing material while etching the carbon-containing material. In some embodiments, the carbon-containing material includes a bottom anti-reflective coating, silicon oxycarbonitride, or a combination thereof. In some embodiments, a bias power and a direct current power are periodically switched while etching the carbon-containing material, and the periodic switching of the bias power is synchronized with the periodic switching of the direct current power. In some embodiments, the direct current power has a power level ranging from about 600 W to about 1000 W. In some embodiments, the bias power has a power level ranging from about 20 W to about 60 W. In some embodiments, etching the carbon-containing material is performed at a pressure ranging from about 5 mT to about 30 mT.

[0130] In some embodiments, a semiconductor structure includes a first semiconductor sheet, a second semiconductor sheet, a first high-k dielectric layer, a second high-k dielectric layer, a first metal gate, a plurality of first epitaxial structures, and a plurality of second epitaxial structures. The second semiconductor sheet is above the first semiconductor sheet. The first high-k dielectric layer surrounds the first semiconductor sheet, wherein the first high-k dielectric layer has a dipole dopant. The second high-k dielectric layer surrounds the second semiconductor sheet, wherein the second high-k dielectric layer is free of the dipole dopant. The first metal gate surrounds the first high-k dielectric layer and the second high-k dielectric layer. The plurality of first epitaxial structures are on opposite sides of the first semiconductor sheet, wherein the first semiconductor sheet, the first high-k dielectric layer, the plurality of first epitaxial structures, and a first portion of the first metal gate form a first bottom transistor. The plurality of second epitaxial structures are on opposite sides of the second semiconductor sheet, wherein the second semiconductor sheet, the second high-k dielectric layer, the plurality of second epitaxial structures, and a second portion of the first metal gate form a first top transistor. In some embodiments, the semiconductor structure further includes a third semiconductor sheet, a third high-k dielectric layer, and a second metal gate. The third semiconductor sheet is laterally adjacent to the first semiconductor sheet. The third high-k dielectric layer surrounds the third semiconductor sheet, wherein the third high-k dielectric layer is free of the dipole dopant. The second metal gate surrounds the third high-k dielectric layer. In some embodiments, the semiconductor structure further includes a fourth semiconductor sheet and a fourth high-k dielectric layer. The fourth semiconductor sheet is above the third semiconductor sheet and laterally adjacent to the second semiconductor sheet. The fourth high-k dielectric layer surrounds the fourth semiconductor sheet, wherein the fourth high-k dielectric layer has the dipole dopant, and the second metal gate further surrounds the fourth high-k dielectric layer. In some embodiments, the semiconductor structure further includes a third semiconductor sheet, a third high-k dielectric layer, and a second metal gate. The third semiconductor sheet is laterally adjacent to the first semiconductor sheet. The third high-k dielectric layer surrounds the third semiconductor sheet, wherein the third high-k dielectric layer has the dipole dopant. The second metal gate surrounds the third high-k dielectric layer. In some embodiments, the semiconductor structure further includes a third semiconductor sheet, a third high-k dielectric layer, and a second metal gate. The third semiconductor sheet is laterally adjacent to the second semiconductor sheet. The third high-k dielectric layer surrounds the third semiconductor sheet, wherein the third high-k dielectric layer has the dipole dopant. The second metal gate surrounds the third high-k dielectric layer.

[0131] In some embodiments, a semiconductor structure includes a first channel layer, a second channel layer, a first gate dielectric layer, a second gate dielectric layer, a first gate electrode layer, a plurality of first source / drain regions, and a plurality of second source / drain regions. The second channel layer is above a channel layer. The first gate dielectric layer surrounds a first semiconductor sheet, wherein the first gate dielectric layer is free of dipole dopants. The second gate dielectric layer surrounds a second semiconductor sheet, wherein the second gate dielectric layer has the aforementioned dipole dopants. The first gate electrode layer surrounds the first gate dielectric layer and the second gate dielectric layer. The plurality of first source / drain regions are on opposite sides of the first channel layer, wherein the first channel layer, the first gate dielectric layer, the first source / drain regions, and a first portion of the first gate electrode layer form a first bottom transistor. The plurality of second source / drain regions are on opposite sides of the second channel layer, wherein the second channel layer, the second gate dielectric layer, the second source / drain regions, and a second portion of the first gate electrode layer form a first top transistor. In some embodiments, the semiconductor structure further includes a third channel layer, a third gate dielectric layer, a second metal gate, and a plurality of third source / drain regions. The third channel layer is laterally adjacent to the second semiconductor sheet. The third gate dielectric layer surrounds the third channel layer, wherein the third gate dielectric layer is free of dipole dopants. The second metal gate surrounds the third gate dielectric layer. The plurality of third source / drain regions are on opposite sides of the third channel layer, wherein the third channel layer, the third gate dielectric layer, the plurality of third source / drain regions, and a portion of the second gate electrode layer form a second top transistor. In some embodiments, the semiconductor structure further includes a fourth channel layer, a fourth gate dielectric layer, a third metal gate, and a plurality of fourth source / drain regions. The fourth channel layer is laterally adjacent to the first semiconductor sheet. The fourth gate dielectric layer surrounds the fourth channel layer, wherein the fourth gate dielectric layer has dipole dopants. The third metal gate surrounds the fourth gate dielectric layer. The plurality of fourth source / drain regions are on opposite sides of the fourth channel layer, wherein the fourth channel layer, the fourth gate dielectric layer, the plurality of fourth source / drain regions, and a portion of the third gate electrode layer form a second bottom transistor.

[0132] In some embodiments, a semiconductor structure includes a first semiconductor nanostructure, a second semiconductor nanostructure, a third semiconductor nanostructure, a fourth semiconductor nanostructure, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, a fourth high-k dielectric layer, a first gate electrode layer, and a second gate electrode layer. The second semiconductor nanostructure is laterally adjacent to the first semiconductor nanostructure. The third semiconductor nanostructure is above the first semiconductor nanostructure. The fourth semiconductor nanostructure is above the second semiconductor nanostructure. The first high-k dielectric layer surrounds the first semiconductor nanostructure, wherein the first high-k dielectric layer contains a dipole dopant. The second high-k dielectric layer surrounds the second semiconductor nanostructure, wherein the second high-k dielectric layer does not contain the aforementioned dipole dopant. The third high-k dielectric layer surrounds the third semiconductor nanostructure, wherein the third high-k dielectric layer does not contain the aforementioned dipole dopant. The fourth high-k dielectric layer surrounds the fourth semiconductor nanostructure, wherein the fourth high-k dielectric layer contains the aforementioned dipole dopant. The first gate electrode layer surrounds the first high-k dielectric layer and the third high-k dielectric layer. The second gate electrode layer surrounds the second high-k dielectric layer and the fourth high-k dielectric layer. In some embodiments, the semiconductor structure further includes a plurality of first epitaxial structures, a plurality of second epitaxial structures, a plurality of third epitaxial structures, and a plurality of fourth epitaxial structures. The plurality of first epitaxial structures are on opposite sides of the first semiconductor nanostructure, wherein the first semiconductor nanostructure, the first high-k dielectric layer, the plurality of first epitaxial structures, and a first portion of the first gate electrode layer form a first bottom transistor. The plurality of second epitaxial structures are on opposite sides of the second semiconductor nanostructure, wherein the second semiconductor nanostructure, the second high-k dielectric layer, the plurality of second epitaxial structures, and a first portion of the second gate electrode layer form a second bottom transistor. The plurality of third epitaxial structures are on opposite sides of the third semiconductor nanostructure, wherein the third semiconductor nanostructure, the third high-k dielectric layer, the plurality of third epitaxial structures, and a second portion of the first gate electrode layer form a first top transistor. The plurality of fourth epitaxial structures are on opposite sides of the fourth semiconductor nanostructure, wherein the fourth semiconductor nanostructure, the fourth high-k dielectric layer, the plurality of fourth epitaxial structures, and a second portion of the second gate electrode layer form a second top transistor.

[0133] The foregoing outlines features of several embodiments so that a thorough comprehension of the various aspects of the disclosure can be attained. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that changes can be made in the process and structures disclosed herein without departing from the scope of the disclosure.

Claims

1. A semiconductor structure, characterized by, comprising: a first semiconductor sheet; a second semiconductor sheet over the first semiconductor sheet; a first high-k dielectric layer surrounding the first semiconductor sheet, wherein the first high-k dielectric layer has a dipole dopant; a second high-k dielectric layer surrounding the second semiconductor sheet, wherein the second high-k dielectric layer is free of the dipole dopant; a first metal gate surrounding the first high-k dielectric layer and the second high-k dielectric layer; a plurality of first epitaxial structures on opposite sides of the first semiconductor sheet, wherein the first semiconductor sheet, the first high-k dielectric layer, the plurality of first epitaxial structures, and a first portion of the first metal gate form a bottom layer transistor; and a plurality of second epitaxial structures on opposite sides of the second semiconductor sheet, wherein the second semiconductor sheet, the second high-k dielectric layer, the plurality of second epitaxial structures, and a second portion of the first metal gate form a top layer transistor. further comprising:

2. The semiconductor structure of claim 1, wherein, a third semiconductor sheet laterally adjacent to the first semiconductor sheet; a third high-k dielectric layer surrounding the third semiconductor sheet, wherein the third high-k dielectric layer is free of the dipole dopant; and a second metal gate surrounding the third high-k dielectric layer. further comprising:

3. The semiconductor structure of claim 2, wherein, a fourth semiconductor sheet over the third semiconductor sheet and laterally adjacent to the second semiconductor sheet; and a fourth high-k dielectric layer surrounding the fourth semiconductor sheet, wherein the fourth high-k dielectric layer has the dipole dopant, and the second metal gate further surrounds the fourth high-k dielectric layer. further comprising:

4. The semiconductor structure of claim 1, wherein, a third semiconductor sheet laterally adjacent to the first semiconductor sheet; a third high-k dielectric layer surrounding the third semiconductor sheet, wherein the third high-k dielectric layer has the dipole dopant; and a second metal gate surrounding the third high-k dielectric layer. further comprising:

5. The semiconductor structure of claim 1, wherein, a third semiconductor sheet laterally adjacent to the second semiconductor sheet; and a third high-k dielectric layer surrounding the third semiconductor sheet, wherein the third high-k dielectric layer has the dipole dopant; and a second metal gate surrounding the third high-k dielectric layer. comprising:

6. A semiconductor structure, characterized by a first channel layer; a second channel layer over the first channel layer; a first gate dielectric layer surrounding the first channel layer, wherein the first gate dielectric layer is free of a dipole dopant; a second gate dielectric layer surrounding the second channel layer, wherein the second gate dielectric layer has the dipole dopant; a first gate electrode layer surrounding the first gate dielectric layer and the second gate dielectric layer; a plurality of first source / drain regions on opposite sides of the first channel layer, wherein the first channel layer, the first gate dielectric layer, the plurality of first source / drain regions, and a first portion of the first gate electrode layer form a first bottom layer transistor; and a plurality of second source / drain regions on opposite sides of the second channel layer, wherein the second channel layer, the second gate dielectric layer, the plurality of second source / drain regions, and a second portion of the first gate electrode layer form a second bottom layer transistor. ​ a plurality of second source / drain regions on opposite sides of the second channel layer, wherein the second channel layer, the second gate dielectric layer, the plurality of second source / drain regions, and a second portion of the first gate electrode layer form a first top transistor.

7. The semiconductor structure of claim 6, wherein, further comprising: a third channel layer laterally adjacent to the second channel layer; a third gate dielectric layer surrounding the third channel layer, wherein the third gate dielectric layer does not contain the dipole dopant; a second gate electrode layer surrounding the third gate dielectric layer; and a plurality of third source / drain regions on opposite sides of the third channel layer, wherein the third channel layer, the third gate dielectric layer, the plurality of third source / drain regions, and a portion of the second gate electrode layer form a second top transistor.

8. The semiconductor structure of claim 7, wherein, further comprising: a fourth channel layer laterally adjacent to the first channel layer; a fourth gate dielectric layer surrounding the fourth channel layer, wherein the fourth gate dielectric layer contains the dipole dopant; a third gate electrode layer surrounding the fourth gate dielectric layer; and a plurality of fourth source / drain regions on opposite sides of the fourth channel layer, wherein the fourth channel layer, the fourth gate dielectric layer, the plurality of fourth source / drain regions, and a portion of the third gate electrode layer form a second bottom transistor.

9. A semiconductor structure, characterized by comprising: a first semiconductor nanostructure; a second semiconductor nanostructure laterally adjacent to the first semiconductor nanostructure; a third semiconductor nanostructure over the first semiconductor nanostructure; a fourth semiconductor nanostructure over the second semiconductor nanostructure; a first high-k dielectric layer surrounding the first semiconductor nanostructure, wherein the first high-k dielectric layer contains a dipole dopant; a second high-k dielectric layer surrounding the second semiconductor nanostructure, wherein the second high-k dielectric layer does not contain the dipole dopant; a third high-k dielectric layer surrounding the third semiconductor nanostructure, wherein the third high-k dielectric layer does not contain the dipole dopant; a fourth high-k dielectric layer surrounding the fourth semiconductor nanostructure, wherein the fourth high-k dielectric layer contains the dipole dopant; a first gate electrode layer surrounding the first high-k dielectric layer and the third high-k dielectric layer; and a second gate electrode layer surrounding the second high-k dielectric layer and the fourth high-k dielectric layer.

10. The semiconductor structure of claim 9, wherein a plurality of first epitaxial structures on opposite sides of the first semiconductor nanostructure, wherein the first semiconductor nanostructure, the first high-k dielectric layer, the plurality of first epitaxial structures, and a first portion of the first gate electrode layer form a first bottom transistor; a plurality of second epitaxial structures on opposite sides of the second semiconductor nanostructure, wherein the second semiconductor nanostructure, the second high-k dielectric layer, the plurality of second epitaxial structures, and a first portion of the second gate electrode layer form a second bottom transistor; a plurality of third epitaxial structures located on opposite sides of the third semiconductor nanostructure, wherein the third semiconductor nanostructure, the third high dielectric constant dielectric layer, the plurality of third epitaxial structures, and a second portion of the first gate electrode layer form a first top transistor; and a plurality of fourth epitaxial structures located on opposite sides of the fourth semiconductor nanostructure, wherein the fourth semiconductor nanostructure, the fourth high dielectric constant dielectric layer, the plurality of fourth epitaxial structures, and a second portion of the second gate electrode layer form a second top transistor.

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