Semiconductor device

Abstract

A semiconductor device includes a substrate having a front side and a back side, a first P-I-N diode located on the front side of the substrate, a first terminal located under the back side of the substrate, a plurality of front side conductive layers, and a plurality of back side conductive layers. A plurality of front side conductive layers are located on the first P-I-N diodes and electrically connected with the first P-I-N diodes. A plurality of backside conductive layers is located under the backside of the substrate and electrically connected to a first terminal that is electrically connected to the first P-I-N diode through the plurality of backside conductive layers and the at least one via.

Description

TECHNICAL FIELD

[0001] The utility model embodiment relates to electrostatic discharge protection circuit, especially electrostatic discharge protection circuit including P -essence -N diode. BACKGROUND

[0002] Electrostatic discharge (ESD) can sometimes cause errors in electronic devices, such as integrated circuits (ICs). ESD is a sudden and short burst of current between two objects with different charges that can damage electronic components in the device. Generally, manufacturers create ESD protection circuits to protect electronic components from ESD. ESD protection circuits typically include diodes and clamping circuits to prevent or mitigate damage to electronic devices. SUMMARY

[0003] The utility model discloses a semiconductor device to solve at least one of the above problems.

[0004] The utility model embodiment provides a semiconductor device, including the substrate with the front side and the back side, the first P-I-N diode on the front side of the substrate, the first terminal under the back side of the substrate, a plurality of front side conductive layers and a plurality of back side conductive layers. A plurality of front side conductive layers are on the first P-I-N diode and electrically connected to the first P-I-N diode. A plurality of back side conductive layers are on the back side of the substrate and electrically connected to the first terminal, and the first terminal is electrically connected to the first P-I-N diode through at least one via hole in the plurality of back side conductive layers and the substrate.

[0005] According to one embodiment of the utility model, it further includes a feed-through hole extending through the substrate from the back side of the substrate to the front side of the substrate, wherein a plurality of the back side conductive layers are electrically connected to a plurality of the front side conductive layers through the feed-through hole.

[0006] According to one embodiment of the utility model, it further includes a back side through hole extending through the substrate from the back side of the substrate to a side of the first P-I-N diode, wherein a plurality of the back side conductive layers are electrically connected to the side of the first P-I-N diode through the back side through hole.

[0007] Wherein a plurality of the front side conductive layers are electrically connected to the side of the first P-I-N diode, so that a plurality of the back side conductive layers are electrically connected to a plurality of the front side conductive layers through the back side through hole and the side of the first P-I-N diode.

[0008] According to one of the embodiments of the present application, the first terminal is one of a power terminal, a reference terminal, and an input / output terminal.

[0009] According to one of the embodiments of the present application, the semiconductor device further comprises a power rail clamp circuit electrically connected to the plurality of front-side conductive layers.

[0010] According to one of the embodiments of the present application, the semiconductor device further comprises a second P-I-N diode and a second terminal, the second P-I-N diode is located on the front side of the substrate, and the second terminal is located under the back side of the substrate, wherein the plurality of front-side conductive layers are electrically connected to the second P-I-N diode, and the plurality of back-side conductive layers are electrically connected to the second terminal; wherein the second terminal is electrically connected to the second P-I-N diode through the plurality of back-side conductive layers electrically connected to the plurality of front-side conductive layers; wherein the semiconductor device further comprises a capacitor having one end connected to the first terminal and the other end connected to the second terminal.

[0011] The embodiment of the present application further provides a semiconductor device, which comprises a substrate having a front side and a back side, a first P-I-N diode located on the front side of the substrate, a first terminal located under the back side of the substrate, a second terminal located under the back side of the substrate, a first front-side conductive path, a second front-side conductive path, a first back-side conductive path, and a second back-side conductive path. The first front-side conductive path is located on a first side of the first P-I-N diode and is electrically connected to the first side of the first P-I-N diode. The second front-side conductive path is located on a second side of the first P-I-N diode and is electrically connected to the second side of the first P-I-N diode. The first back-side conductive path is located under the back side of the substrate and is electrically connected to the first terminal, and the second back-side conductive path is located under the back side of the substrate and is electrically connected to the second terminal. The device further comprises an FTV and a first VB, the FTV extends through the substrate from the back side of the substrate to the front side of the substrate, wherein the first back-side conductive path is electrically connected to the first front-side conductive path through the FTV. The first VB extends through the substrate from the back side of the substrate to the second side of the first P-I-N diode, wherein the second back-side conductive path is electrically connected to the second side of the first P-I-N diode through the first VB.

[0012] According to one of the embodiments of the present application, the second back-side conductive path is electrically connected to the second front-side conductive path through the first back-side via hole and the second side of the first P-I-N diode.

[0013] According to one of the embodiments of the present application, a second P-I-N diode and a third backside conductive path are further included, the second P-I-N diode is located on the front side of the substrate, wherein the second front side conductive path is electrically connected to a first side of the second P-I-N diode, and the third backside conductive path is electrically connected to the second terminal or a third terminal located on the back side of the substrate; wherein the second terminal or the third terminal is electrically connected to the first side of the second P-I-N diode through the third backside conductive path, and the third backside conductive path is electrically connected to the second front side conductive path through a second backside via and the first side of the second P-I-N diode. BRIEF DESCRIPTION OF DRAWINGS

[0014] The embodiments of the present application can be best understood by reading the following detailed description together with the accompanying drawings, in which:

[0015] Figure 1 A device of the embodiments of the present application is illustrated.

[0016] Figure 2 A cross-section of a P-I-N diode of the embodiments of the present application is illustrated.

[0017] Figure 3 A top view of a P-I-N diode of the embodiments of the present application is illustrated.

[0018] Figure 4 A device of the embodiments of the present application including a substrate and feed-through-vias (FTVs) is illustrated.

[0019] Figure 5 A circuit diagram of the embodiments of the present application is illustrated, showing a device of Figure 4 with a power-rail clamp circuit.

[0020] Figure 6 A device of the embodiments of the present application including a substrate and bottom vias (also referred to as backside vias (VBs)) is illustrated.

[0021] Figure 7 A top view of a first P-I-N diode of the embodiments of the present application is illustrated.

[0022] Figure 8 A circuit diagram of the embodiments of the present application is illustrated, showing a device of Figure 6 with a power-rail clamp circuit.

[0023] Figure 9 The device of the embodiment of the present application includes a substrate, an FTV, and a VB.

[0024] Figure 10 The circuit diagram of the embodiment of the present application shows the device with a power rail clamping circuit. Figure 9

[0025] Figure 11 The circuit diagram of the embodiment of the present application shows the device including an IO signal channel impedance matching network.

[0026] Figure 12 The flowchart of the embodiment of the present application shows a method for manufacturing an ESD protection circuit.

[0027] Figure 13 The block diagram of the embodiment of the present application shows an example of a computer system for providing electronic devices, semiconductor devices, and methods of the embodiment of the present application.

[0028] Figure 14 The block diagram of the embodiment of the present application shows a semiconductor device manufacturing system and a semiconductor device manufacturing process related to the semiconductor device manufacturing system.

[0029] The following are the reference signs:

[0030] 20, 100, 200, 300, 300': device

[0031] 22, 102, 202, 302: substrate

[0032] 24, 110, 212, 312: front side

[0033] 26, 112, 214, 314: back side

[0034] 28: P-I-N diode

[0035] 30: terminal

[0036] 32, 124, 228, 328: front side conductive layer

[0037] 34, 126, 230, 330: back side conductive layer

[0038] 36, 128, 134, 232, 238, 332, 338: P+ region

[0039] 38, 130, 136, 234, 240, 334, 340: N+ region

[0040] 40, 132, 138, 236, 242, 336, 342: intrinsic region​

[0041] 42, 46: Conductive layer

[0042] 44, 48, 50, 142, 146, 150, 158, 164, 168, 174, 178, 184, 188, 246, 250, 254, 258, 266, 272, 284, 346, 350, 354, 358, 362, 368, 372, 378, 382, 388: Via

[0043] 60: Shallow trench isolation region

[0044] 62: Buried oxide layer

[0045] 64, 66, 292, 294: Diffusion upper metal layer (MD layer)

[0046] 68, 296: Polysilicon layer (PO layer)

[0047] 70, 290: Active region

[0048] 104, 304: FTV / First FTV

[0049] 106, 306: FTV / Second FTV

[0050] 108: FTV / Third FTV

[0051] 114, 216, 316: First P-I-N diode

[0052] 116, 218, 318: Second P-I-N diode

[0053] 118, 220, 320: External VDD power terminal (VDD_ext.)

[0054] 120, 222, 322: External VSS reference terminal (VSS_ext.)

[0055] 122, 224, 226, 324, 326: External IO terminal (IOPAD)

[0056] 140, 144, 148, 244, 248, 252, 256, 344, 348, 352, 356: Backside conductive path

[0057] 152, 260: First capacitor (C1)

[0058] 154, 262: Second capacitor (C2)

[0059] 156, 162, 166, 172, 176, 182, 186, 264, 270, 276, 278, 282, 360, 366, 370, 376, 380, 386: front-side conductive path

[0060] 160, 268, 364: internal VDD power terminal (VDD int.)

[0061] 170, 280, 374: internal VSS reference terminal (VSS int.)

[0062] 180, 274, 384: internal IO terminal (PAD int.)

[0063] 190, 192, 286, 288, 390, 392: internal disturbed circuit

[0064] 194, 298, 394: power rail clamping circuit

[0065] 204, 308: bottom via (VB) / first VB

[0066] 206, 310: bottom via (VB) / second VB

[0067] 208: bottom via (VB) / third VB

[0068] 210: bottom via (VB) / fourth VB

[0069] 396, 398a, 398b: IO signal channel impedance matching network / impedance matching network

[0070] 400, 402, 404, 406, 408, 410: computer system / system

[0071] 502: processor

[0072] 504: computer readable storage medium

[0073] 506: instructions

[0074] 508: manufacturing tool

[0075] 510: bus

[0076] 512: I / O interface

[0077] 514: network interface

[0078] 516: network

[0079] 518: database

[0080] 520: user interface (UI)

[0081] 522: Semiconductor device manufacturing system / system

[0082] 524: Design house

[0083] 526: Mask house

[0084] 528: Semiconductor device manufacturing house / foundry

[0085] 530: Semiconductor device design layout

[0086] 532: Mask data preparation / data preparation

[0087] 534: Mask manufacturing

[0088] 536: Mask

[0089] 538: Semiconductor wafer

[0090] 540: Wafer manufacturing

[0091] 542: Semiconductor structure or semiconductor device

[0092] R1, R2, R2', R3, R4, R5: resistance DETAILED DESCRIPTION

[0093] A number of different embodiments or examples are provided below to implement different features of the provided subject matter. The specific examples of elements and arrangements are intended to be examples only and are not intended to be limiting. For example, the description below of a first feature forming over a second feature can include embodiments where the first feature and the second feature are directly in contact with each other, and can also include embodiments where additional features form between the first feature and the second feature such that the first feature and the second feature are not directly in contact with each other. Further, the present disclosure will repeatedly refer to reference numbers and / or letters in multiple examples. Such repetition is for the sake of brevity and clarity and is not intended to connote a relationship between the different embodiments and / or configurations.

[0094] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0095] Embodiments of the present application provide an ESD protection circuit and architecture including at least one P-Intrinsic-N (P-I-N) diode. The P-I-N diode includes a P+ region, an N+ region, and an intrinsic region between the P+ region and the N+ region. The P-I-N diode can be fabricated in a bulk-less process, such as a silicon-on-insulator (SOI) process and / or a super power rail (SPR) process. In some embodiments, the intrinsic region is a lightly doped p-type substrate. In some embodiments, the ESD protection circuit and architecture includes at least one ESD power rail clamp circuit.

[0096] Embodiments of the present application provide an apparatus including a substrate having a front side and a back side, a P-I-N diode on the front side of the substrate, and a terminal below the back side of the substrate. A plurality of frontside conductive layers are on the P-I-N diode and electrically connected to the P-I-N diode, and a plurality of backside conductive layers are below the back side of the substrate and electrically connected to the terminal. The terminal is electrically connected to the P-I-N diode and at least one via through the plurality of backside conductive layers.

[0097] In some embodiments, the at least one via includes a feed-through-via (FTV) extending through the substrate from the back side of the substrate to the front side of the substrate, wherein the plurality of backside conductive layers are electrically connected to the plurality of frontside conductive layers through the FTV. In some embodiments, the at least one via includes a bottom via (also referred to as a backside via (VB)) extending through the substrate from the back side of the substrate to a side of the P-I-N diode, wherein the plurality of backside conductive layers are electrically connected to the side of the P-I-N diode through the VB. The plurality of frontside conductive layers are electrically connected to the side of the P-I-N diode, such that the plurality of backside conductive layers are electrically connected to the plurality of frontside conductive layers through the VB and the side of the P-I-N diode.

[0098] In some embodiments, the device does not have or include a capacitance between a power / reference terminal and an input / output (IO) terminal, e.g., between a VDD power terminal and an IO terminal, and / or between an IO terminal and a VSS reference terminal. In some embodiments, the lack of a capacitance between the power / reference terminal and the IO terminal is due to a large distance between the power / reference terminal and the IO terminal. In addition, in some embodiments, a matching network is included between the power / reference terminal and the IO terminal, the matching network to match an impedance of an IO signal path to the device, where the matching network includes a capacitance, an inductance, and / or a resistance in a space between the terminals.

[0099] Figure 1 A device 20 is illustrated in accordance with an embodiment of the present application. The device 20 includes a substrate 22 having a front side 24 and a back side 26. In some embodiments, the substrate 22 is a bulk-less process substrate. In some embodiments, the substrate 22 is an SOI substrate. In some embodiments, the substrate 22 is a silicon-insulator-silicon substrate. In some embodiments, the substrate 22 is a SPR process substrate. In some embodiments, the device 20 is a semiconductor device, an IC device, and / or an electronic device. In some embodiments, the device 20 including the substrate 22 is part of a wafer.

[0100] The device 20 includes a P-I-N diode 28, a terminal 30, a plurality of front side conductive layers 32, and a plurality of back side conductive layers 34. The P-I-N diode 28 includes a P+ region 36, an N+ region 38, and an intrinsic region 40. The P-I-N diode 28 is on the front side 24 of the substrate 22. The terminal 30 is under the back side 26 of the substrate 22. In some embodiments, the terminal 30 is one of a power terminal (e.g., a VDD power terminal), a reference terminal (e.g., a VSS reference terminal and / or a ground terminal), and an IO terminal.

[0101] The plurality of front side conductive layers 32 includes a stack of conductive layers 42 (e.g., metal layers) and vias 44. The plurality of front side conductive layers 32 is on and electrically connected to the P-I-N diode. The plurality of back side conductive layers 34 includes a stack of conductive layers 46 (e.g., metal layers) and vias 48. The plurality of back side conductive layers 34 is under the back side of the substrate 22 and electrically connected to the terminal 30.

[0102] The terminal 30 is electrically connected to the P-I-N diode 28 through the plurality of back side conductive layers 34 and at least one via 50 in the substrate 22. The via 50 is indicated by a connection between the plurality of back side conductive layers 34 and one side of the P-I-N diode 28.

[0103] In some embodiments, the at least one via 50 includes an FTV extending through the substrate 22 from the backside 26 of the substrate 22 to the frontside 24 of the substrate 22, where the plurality of backside conductive layers 34 are electrically connected to the plurality of frontside conductive layers 32 through the FTV. In some embodiments, the at least one via 50 includes a VB extending through the substrate 22 from the backside 26 of the substrate 22 to a side of the P-I-N diode 28, where the plurality of backside conductive layers 34 are electrically connected to the side of the P-I-N diode 28 through the VB. The plurality of frontside conductive layers 32 are electrically connected to the side of the P-I-N diode 28, such that the plurality of backside conductive layers 34 are electrically connected to the plurality of frontside conductive layers 32 through the VB and the side of the P-I-N diode 28.

[0104] Figure 2 A cross-section of a P-I-N diode 28 of an embodiment of the present application is shown. The P-I-N diode 28 includes a P+ region 36, an N+ region 38, and an intrinsic region 40 surrounded by a shallow trench isolation (STI) region 60. A buried oxide (BOX) layer 62 is located under the intrinsic region 40. A metal over diffusion (MD) layer 64 is formed on the N+ region 38, and a MD layer 66 is formed on the P+ region 36. A polycrystalline silicon (PO) (polysilicon or poly) layer is formed on the intrinsic region 40.

[0105] Figure 3 A top view of a P-I-N diode 28 of an embodiment of the present application is shown. The P-I-N diode 28 includes a P+ region 36, an N+ region 38, and an intrinsic region 40. A MD layer 66 is formed on the P+ region 36, and a MD layer 64 is formed on the N+ region 38. A polycrystalline silicon layer (PO layer) 68 is formed on the intrinsic region 40. The P-I-N diode 28 includes an active region 70 (also referred to as an oxide diffusion region) that includes the P+ region 36, the N+ region 38, and the intrinsic region 40.

[0106] Figure 4An embodiment of the present application includes a device 100 including a substrate 102 and FTVs 104, 106, 108. Each of the FTVs 104, 106, 108 is a conductive path through the substrate 102. In some embodiments, the device 100 is a semiconductor device, an IC device, and / or an electronic device. In some embodiments, the device 100 is part of a wafer. In some embodiments, the device 100 is similar to the device 20 in Figure 1

[0107] The device 100 includes a substrate 102 having a front side 110 and a back side 112. The FTVs 104, 106, 108 extend through the substrate 102 from the front side 110 to the back side 112. In some embodiments, the substrate 102 is a bulk process substrate. In some embodiments, the substrate 102 is an SOI substrate. In some embodiments, the substrate 102 is a silicon-insulator-silicon substrate. In some embodiments, the substrate 102 is a SPR process substrate.

[0108] The device 100 includes a first P-I-N diode 114, a second P-I-N diode 116, an external VDD power terminal (VDD_ext.) 118, an external VSS reference terminal (VSS_ext.) 120, an external IO terminal (IOPAD) 122, a plurality of front side conductive layers 124, and a plurality of back side conductive layers 126. The first P-I-N diode 114 and the second P-I-N diode 116 are located on the front side 110 of the substrate 102. The first P-I-N diode 114 includes a P+ region 128, an N+ region 130, and an intrinsic region 132. The second P-I-N diode 116 includes a P+ region 134, an N+ region 136, and an intrinsic region 138. The external VDD power terminal (VDD_ext.) 118, the external VSS reference terminal (VSS_ext.) 120, and the external IO terminal (IOPAD) 122 are located on the back side 112 of the substrate 102.

[0109] ​The external VDD supply terminal (VDD ext.) 118, the external VSS reference terminal (VSS ext.) 120, and the external IO terminal (IOPAD) 122 are electrically connected to the plurality of backside conductive layers 126. The external VDD supply terminal (VDD ext.) 118 is electrically connected to a backside conductive path 140 and a via 142 (resistor R3), which are electrically connected to the first FTV 104. The external VSS reference terminal (VSS ext.) 120 is electrically connected to a backside conductive path 144 and a via 146 (resistor R3), which are electrically connected to the second FTV 106. The external IO terminal (IOPAD) 122 is electrically connected to a backside conductive path 148 and a via 150 (resistor Rl), which are electrically connected to the third FTV 108.

[0110] In some embodiments, a first capacitance (Cl) 152 is positioned between the external VDD supply terminal (VDD ext.) 118 and the external IO terminal (IOPAD) 122, one side of the first capacitance (Cl) 152 is positioned at the external VDD supply terminal (VDD ext.) 118, and the other side of the first capacitance (Cl) 152 is positioned at the external IO terminal (IOPAD) 122. In some embodiments, a second capacitance C2 (154) is positioned between the external VSS reference terminal (VSS ext.) 120 and the external IO terminal (IOPAD) 122, one side of the second capacitance C2 (154) is positioned at the external VSS reference terminal (VSS ext.) 120, and the other side of the second capacitance C2 (154) is positioned at the external IO terminal (IOPAD) 122.

[0111] The first P-I-N diode 114 and the second P-I-N diode 116 are electrically connected to the plurality of frontside conductive layers 124. The first FTV 104 is electrically connected to the N+ region 130 of the first P-I-N diode 114 through a frontside conductive path 156 and a via 158 (resistor R5), an internal VDD supply terminal (VDD int.) 160, and a frontside conductive path 162 and a via 164 (resistor R4). The second FTV 106 is electrically connected to the P+ region 134 of the second P-I-N diode 116 through a frontside conductive path 166 and a via 168 (resistor R5), an internal VSS reference terminal (VSS int.) 170, and a frontside conductive path 172 and a via 174 (resistor R4).

[0112] The third FTV 108 is electrically connected to the P+ region 128 of the first P-I-N diode 114 through the front-side conductive path 176 and the via 178 (resistance R2), the internal IO terminal (PAD_int.) 180, and the front-side conductive path 182 and the via 184 (resistance R2’), and is electrically connected to the N+ region 136 of the second P-I-N diode 116 through the front-side conductive path 176 and the via 178 (resistance R2), the internal IO terminal (PAD_int.) 180, and the front-side conductive path 186 and the via 188 (resistance R2’).

[0113] The internal VDD power terminal (VDD_int.) 160 is electrically connected to an internal circuit victim 190, and the internal circuit victim 190 is electrically connected to the internal IO terminal (PAD_int.) 180. In addition, the internal VSS reference terminal (VSS_int.) 170 is electrically connected to an internal circuit victim 192, and the internal circuit victim 192 is electrically connected to the internal IO terminal (PAD_int.) 180.

[0114] In operation, the first P-I-N diode 114 bypasses the internal circuit victim 190 by shunting ESD current from the external IO terminal (IOPAD) 122 through the third FTV 108, the first P-I-N diode 114, and the first FTV 104 to the external VDD power terminal (VDD_ext.) 118 to protect the internal circuit victim 190 from ESD. The second P-I-N diode 116 bypasses the internal circuit victim 192 by shunting ESD current from the external VSS reference terminal (VSS_ext.) 120 through the second FTV 106, the second P-I-N diode 116, and the third FTV 108 to the external IO terminal (IOPAD) 122 to protect the internal circuit victim 192 from ESD.

[0115] Figure 5 is a circuit diagram of an embodiment of the present application, showing a power-rail clamp circuit 194 Figure 4Figure 1 illustrates a device 100 according to an embodiment. The device 100 comprises a substrate 102 having a front side 110 and a back side 112. The device 100 comprises a first P-I-N diode 114, a second P-I-N diode 116, an external VDD power terminal (VDD_ext.) 118, an external VSS reference terminal (VSS_ext.) 120, and an external IO terminal (IOPAD) 122. The first P-I-N diode 114 and the second P-I-N diode 116 are located on the front side 110 of the substrate 102. The external VDD power terminal (VDD_ext.) 118, the external VSS reference terminal (VSS_ext.) 120, and the external IO terminal (IOPAD) 122 are located on the back side 112 of the substrate 102.

[0116] On the back side 112, the external VDD power terminal (VDD_ext.) 118 is electrically connected to a resistor R3, the external VSS reference terminal (VSS_ext.) 120 is electrically connected to a resistor R3, and the external IO terminal (IOPAD) 122 is electrically connected to a resistor R1. One side of a first capacitor (C1) 152 is electrically connected to the external VDD power terminal (VDD_ext.) 118, and the other side of the first capacitor (C1) 152 is electrically connected to the external IO terminal (IOPAD) 122. One side of a second capacitor C2 (154) is electrically connected to the external VSS reference terminal (VSS_ext.) 120, and the other side of the second capacitor C2 (154) is electrically connected to the external IO terminal (IOPAD) 122.

[0117] The first P-I-N diode 114 is electrically connected to a resistor R4, which is electrically connected to an internal VDD power terminal (VDD_int.) 160. A resistor R5 is electrically connected to the internal VDD power terminal (VDD_int.) 160 and to the resistor R3, e.g. via a first FTV 104. Further, the second P-I-N diode 116 is electrically connected to the resistor R4, which is electrically connected to an internal VSS reference terminal (VSS_int.) 170. A resistor R5 is electrically connected to the internal VSS reference terminal (VSS_int.) 170 and to the resistor R3, e.g. via a second FTV 106.

[0118] The first P-I-N diode 114 and the second P-I-N diode 116 are electrically connected to a resistor R2’, which is electrically connected to an internal IO terminal (PAD_int.) 180 and to a resistor R2. The resistor R2 is electrically connected to the resistor R1 and to the external IO terminal (IOPAD) 122 via a third FTV 108

[0119] The internal VDD power terminal (VDD int.) 160 is electrically connected to the internal victim circuit 190, which is electrically connected to the internal IO terminal (PAD int.) 180. In addition, the internal VSS reference terminal (VSS int.) 170 is electrically connected to the internal victim circuit 192, which is electrically connected to the internal IO terminal (PAD int.) 180.

[0120] The power rail clamp circuit 194 is electrically connected to the internal VDD power terminal (VDD int.) 160 and the internal VSS reference terminal (VSS int.) 170. The internal VDD power terminal (VDD int.) 160 is electrically connected to the external VDD power terminal (VDD ext.) 118 through resistors R5 and R3 (and, in some embodiments, another FTV). In addition, the internal VSS reference terminal (VSS int.) 170 is electrically connected to the external VSS reference terminal (VSS ext.) 120 through resistors R5 and R3 (and, in some embodiments, another FTV).

[0121] In operation, the first P-I-N diode 114 shunts ESD current from the external IO terminal (IOPAD) 122 through resistors R1, R2, R2', the first P-I-N diode 114, and resistors R4, R5, R3 to the external VDD power terminal (VDD ext.) 118, bypassing the internal victim circuit 190 to protect the internal victim circuit 190 from ESD. The second P-I-N diode 116 shunts ESD current from the external VSS reference terminal (VSS ext.) 120 through resistors R3, R5, R4, the second P-I-N diode 116, and resistors R2', R2, R1 to the external IO terminal (IOPAD) 122, bypassing the internal victim circuit 192 to protect the internal victim circuit 192 from ESD.

[0122] Figure 6 An embodiment of the present application includes a device 200 that includes a substrate 202 and bottom vias (VBs) 204, 206, 208, 210. The VBs 204, 206, 208, 210 are conductive paths through at least a portion of the substrate 202. In some embodiments, the device 200 is a semiconductor device, an IC device, and / or an electronic device. In some embodiments, the device 200 is part of a wafer. In some embodiments, the device 200 is similar to the device 20 of Figure 1

[0123] ​Device 200 includes a substrate 202 having a front side 212 and a back side 214, a first P-I-N diode 216, and a second P-I-N diode 218. VBs 204, 206, 208, and 210 extend through substrate 202 from back side 214 to one of first P-I-N diode 216 and second P-I-N diode 218. In some embodiments, substrate 202 is a bulk process substrate. In some embodiments, substrate 202 is an SOI substrate. In some embodiments, substrate 202 is a silicon-on-insulator substrate. In some embodiments, substrate 202 is a SPR process substrate.

[0124] Device 200 includes first P-I-N diode 216, second P-I-N diode 218, an external VDD power terminal (VDD ext.) 220, an external VSS reference terminal (VSS ext.) 222, an external IO terminal (IOPAD) 224, an external IO terminal IOPAD 226, a plurality of front side conductive layers 228, and a plurality of back side conductive layers 230. First P-I-N diode 216 and second P-I-N diode 218 are located on front side 212 of substrate 202. First P-I-N diode 216 includes a P+ region 232, an N+ region 234, and an intrinsic region 236. Second P-I-N diode 218 includes a P+ region 238, an N+ region 240, and an intrinsic region 242. External VDD power terminal (VDD ext.) 220, external VSS reference terminal (VSS ext.) 222, external IO terminals (IOPAD) 224 and 226 are located on back side 214 of substrate 202.

[0125] External VDD power terminal (VDD ext.) 220, external VSS reference terminal (VSS ext.) 222, and external IO terminals (IOPAD) 224 and 226 are electrically connected to plurality of back side conductive layers 230. External VDD power terminal (VDD ext.) 220 is electrically connected to back side conductive path 244 and via 246 (resistor R3), which are electrically connected to first VB 204. External VSS reference terminal (VSS ext.) 222 is electrically connected to back side conductive path 248 and via 250 (resistor R3), which are electrically connected to fourth VB 210. External IO terminal (IOPAD) 224 is electrically connected to back side conductive path 252 and via 254 (resistor Rl), which are electrically connected to second VB 206. External IO terminal IOPAD 226 is electrically connected to back side conductive path 256 and via 258 (resistor Rl), which are electrically connected to third VB 208.

[0126] In some embodiments, the first capacitor (C1) 260 is positioned between the external VDD power terminal (VDD_ext.) 220 and the external IO terminal (IOPAD) 224, one side of the first capacitor (C1) 260 is positioned at the external VDD power terminal (VDD_ext.) 220, and the other side of the first capacitor (C1) 260 is positioned at the external IO terminal (IOPAD) 224. In some embodiments, the second capacitor (C2) 262 is positioned between the external VSS reference terminal (VSS_ext.) 222 and the external IO terminal IOPAD 226, one side of the second capacitor (C2) 262 is positioned at the external VSS reference terminal (VSS_ext.) 222, and the other side of the second capacitor (C2) 262 is positioned at the external IO terminal IOPAD 226.

[0127] The first P-I-N diode 216 and the second P-I-N diode 218 are electrically connected to the plurality of front-side conductive layers 228. The first VB 204 is electrically connected to the N+ region 234 of the first P-I-N diode 216, which is electrically connected to a front-side conductive path 264 and a via 266 (resistor R4), which is electrically connected to the internal VDD power terminal (VDD_int.) 268. The second VB 206 is electrically connected to the P+ region 232 of the first P-I-N diode 216, which is electrically connected to a front-side conductive path 270 and a via 272 (resistor R2’), which is electrically connected to the internal IO terminal (PAD_int.) 274.

[0128] The fourth VB 210 is electrically connected to the P+ region 238 of the second P-I-N diode 218, which is electrically connected to a front-side conductive path 276 and a via 278 (resistor R4), which is electrically connected to the internal VSS reference terminal (VSS_int.) 280. The third VB 208 is electrically connected to the N+ region 240 of the second P-I-N diode 218, which is electrically connected to a front-side conductive path 282 and a via 284 (resistor R2’), which is electrically connected to the internal IO terminal (PAD_int.) 274.

[0129] The internal VDD power terminal (VDD int.) 268 is electrically connected to an internal victim circuit 286, which is electrically connected to the internal IO terminal (PAD int.) 274. In addition, the internal VSS reference terminal (VSS int.) 280 is electrically connected to an internal victim circuit 288, which is electrically connected to the internal IO terminal (PAD int.) 274.

[0130] In operation, the first P-I-N diode 216 bypasses the internal victim circuit 286 by shunting ESD current from the external IO terminals (IOPAD) 224 and 226 through the second VB 206, the third VB 208, the first P-I-N diode 261, and the first VB 204 to the external VDD power terminal (VDD ext.) 220 to protect the internal victim circuit 286 from ESD. The second P-I-N diode 218 bypasses the internal victim circuit 288 by shunting ESD current from the external VSS reference terminal (VSS ext.) 222 through the fourth VB 210, the second P-I-N diode 218, and the second VB 206 and the third VB 208 to the external IO terminals (IOPAD) 224 and 226 to protect the internal victim circuit 288 from ESD.

[0131] Figure 7 A top view of the first P-I-N diode 216 of the present embodiment is shown. The first P-I-N diode 216 includes an active region 290 (also referred to as an oxide diffusion region), which includes a P+ region 232, an N+ region 234, and an intrinsic region 236. The first VB 204 is formed on the N+ region 234, and the second VB 206 is formed on the P+ region 232. A diffusion over metal layer (MD layer) 292 is formed on the N+ region 234, and a diffusion over metal layer (MD layer) 294 is formed on the P+ region 232. A polysilicon layer (PO layer) 296 is formed on the intrinsic region 236.

[0132] Figure 8 A circuit diagram of the present embodiment is shown, which illustrates a power rail clamping circuit 298 having a first P-I-N diode 216 and a second P-I-N diode 218. Figure 6Figure 2 illustrates a device 200 according to an embodiment of the application. The device 200 includes a substrate 202 having a front side 212 and a back side 214. The device 200 includes a first P-I-N diode 216, a second P-I-N diode 218, an external VDD power terminal (VDD_ext.) 220, an external VSS reference terminal (VSS_ext.) 222, and external IO terminals (IOPAD) 224 and 226. The first P-I-N diode 216 and the second P-I-N diode 218 are located on the front side 212 of the substrate 202. The external VDD power terminal (VDD_ext.) 220, the external VSS reference terminal (VSS_ext.) 222, and the external IO terminals (IOPAD) 224 and 226 are located on the back side 214 of the substrate 202.

[0133] On the back side 214, the external VDD power terminal (VDD_ext.) 220 is electrically connected to a resistor R3, the external VSS reference terminal (VSS_ext.) 222 is electrically connected to the resistor R3, and the external IO terminals (IOPAD) 224 and 226 are electrically connected to a resistor Rl. One side of a first capacitor (Cl) 260 is electrically connected to the external VDD power terminal (VDD_ext.) 220, and the other side of the first capacitor (Cl) 260 is electrically connected to the external IO terminals (IOPAD) 224 and 226. One side of a second capacitor (C2) 262 is electrically connected to the external VSS reference terminal (VSS_ext.) 222, and the other side of the second capacitor (C2) 262 is electrically connected to the external IO terminals (IOPAD) 224 and 226.

[0134] The first P-I-N diode 216 is electrically connected to the resistor R3 by the first VB 204, and the resistor R3 is electrically connected to the external VDD power terminal (VDD_ext.) 220. In addition, the first P-I-N diode 216 is electrically connected to a resistor R4, and the resistor R4 is electrically connected to an internal VDD power terminal (VDD_int.) 268. The second P-I-N diode 218 is electrically connected to the resistor R3 by the fourth VB 210, and the resistor R3 is electrically connected to the external VSS reference terminal (VSS_ext.) 222. In addition, the second P-I-N diode 218 is electrically connected to the resistor R4, and the resistor R4 is electrically connected to an internal VSS reference terminal (VSS_int.) 280.

[0135] The first P-I-N diode 216 and the second P-I-N diode 218 are electrically connected to a resistor R2', and the resistor R2' is electrically connected to an internal IO terminal (PAD_int.) 274. In addition, the first P-I-N diode 216 and the second P-I-N diode 218 are electrically connected to the resistor Rl and the external IO terminals (IOPAD) 224 and 226 by the second VB 206 and the third VB 208.

[0136] The internal VDD power terminal (VDD int.) 268 is electrically connected to an internal victim circuit 286, which is electrically connected to an internal IO terminal (PAD int.) 274. In addition, the internal VSS reference terminal (VSS int.) 280 is electrically connected to an internal victim circuit 288, which is electrically connected to the internal IO terminal (PAD int.) 274.

[0137] The power rail clamp circuit 298 is electrically connected to the internal VDD power terminal (VDD int.) 268 and the internal VSS reference terminal (VSS int.) 280. The internal VDD power terminal (VDD int.) 268 is electrically connected to the external VDD power terminal (VDD ext.) 220 through a resistor R3 (and, in some embodiments, other VBs or FTVs). In addition, the internal VSS reference terminal (VSS int.) 280 is electrically connected to the external VSS reference terminal (VSS ext.) 222 through a resistor R3 (and, in some embodiments, other VBs or FTVs).

[0138] In operation, the first P-I-N diode 216 bypasses the internal victim circuit 286 by shunting ESD current from the external IO terminals (IOPAD) 224 and 226 through the second VB 206, the third VB 208, the first P-I-N diode 261, and the first VB 204 to the external VDD power terminal (VDD ext.) 220 to protect the internal victim circuit 286 from ESD. The second P-I-N diode 218 bypasses the internal victim circuit 288 by shunting ESD current from the external VSS reference terminal (VSS ext.) 222 through the fourth VB 210, the second P-I-N diode 218, and the second VB 206 and the third VB 208 to the external IO terminals (IOPAD) 224 and 226 to protect the internal victim circuit 288 from ESD.

[0139] Figure 9 An embodiment of the present application includes a device having a substrate 302, FTVs 304, 306, and via bottom (VB) 308, 310. The FTVs 304 and 306 are conductive paths through the substrate 302, and the VBs 308 and 310 are conductive paths through at least a portion of the substrate 302. In some embodiments, the device 300 is a semiconductor device, an IC device, and / or an electronic device. In some embodiments, the device 300 is part of a wafer. In some embodiments, the device 300 is similar to the device 20 of Figure 1

[0140] ​Device 300 includes a substrate 302 having a front side 312 and a back side 314, a first P-I-N diode 316, and a second P-I-N diode 318. FTVs 304, 306 extend through substrate 302 from front side 312 to back side 314. VBs 308, 310 extend through substrate 302 from back side 314 to one of first P-I-N diode 316 and second P-I-N diode 318. In some embodiments, substrate 302 is a bulk process substrate. In some embodiments, substrate 302 is an SOI substrate. In some embodiments, substrate 302 is a silicon- insulator-silicon substrate. In some embodiments, substrate 302 is an SPR process substrate.

[0141] Device 300 includes first P-I-N diode 316, second P-I-N diode 318, external VDD power terminal (VDD ext.) 320, external VSS reference terminal (VSS ext.) 322, external IO terminals (IOPAD) 324, 326, a plurality of front side conductive layers 328, and a plurality of back side conductive layers 330. First P-I-N diode 316 and second P-I-N diode 318 are located on front side 312 of substrate 302. First P-I-N diode 316 includes a P+ region 332, an N+ region 334, and an intrinsic region 336. Second P-I-N diode 318 includes a P+ region 338, an N+ region 340, and an intrinsic region 342. External VDD power terminal (VDD ext.) 320, external VSS reference terminal (VSS ext.) 322, and external IO terminals (IOPAD) 324, 326 are located on back side 314 of substrate 302.

[0142] External VDD power terminal (VDD ext.) 320, external VSS reference terminal (VSS ext.) 322, and external IO terminals (IOPAD) 324, 326 are electrically connected to plurality of back side conductive layers 330. External VDD power terminal (VDD ext.) 320 is electrically connected to back side conductive path 344 and via 346 (resistor R3), which are electrically connected to first FTV 304. External VSS reference terminal (VSS ext.) 322 is electrically connected to back side conductive path 348 and via 350 (resistor R3), which are electrically connected to second FTV 306. External IO terminal (IOPAD) 324 is electrically connected to back side conductive path 352 and via 354 (resistor Rl), which are electrically connected to first VB 308. External IO terminal (IOPAD) 326 is electrically connected to back side conductive path 356 and via 358 (resistor Rl), which are electrically connected to second VB 310.

[0143] The first P-I-N diode 316 and the second P-I-N diode 318 are electrically connected to the plurality of front-side conductive layers 328. The first FTV 304 is electrically connected to the N+ region 334 of the first P-I-N diode 316 through a front-side conductive path 360 and a via 362 (resistance R5), an internal VDD power terminal (VDD int.) 364, and a front-side conductive path 366 and a via 368 (resistance R4). The second FTV 306 is electrically connected to the P+ region 338 of the second P-I-N diode 318 through a front-side conductive path 370 and a via 372 (resistance R5), an internal VSS reference terminal (VSS int.) 374, and a front-side conductive path 376 and a via 378 (resistance R4).

[0144] The first VB 308 is electrically connected to the P+ region 332 of the first P-I-N diode 316, which is electrically connected to a front-side conductive path 380 and a via 382 (resistance R2’), which is electrically connected to an internal IO terminal (PAD int.) 384. The second VB 310 is electrically connected to the N+ region 340 of the second P-I-N diode 318, which is electrically connected to a front-side conductive path 386 and a via 388 (resistance R2’), which is electrically connected to the internal IO terminal (PAD int.) 384.

[0145] The internal VDD power terminal (VDD int.) 364 is electrically connected to an internal disturbed circuit 390, which is electrically connected to the internal IO terminal (PAD int.) 384. Further, the internal VSS reference terminal (VSS int.) 374 is electrically connected to an internal disturbed circuit 392, which is electrically connected to the internal IO terminal (PAD int.) 384.

[0146] In operation, the first P-I-N diode 316 shunts ESD current from the external IO terminals (IOPAD) 324 and 326 through the first VB 308, the second VB 310, the first P-I-N diode 316, and the first FTV 304 to the external VDD power supply terminal (VDD_ext.) 320 to bypass the internal disturbed circuit 390 to protect the internal disturbed circuit 390 from ESD. The second P-I-N diode 318 shunts ESD current from the external VSS reference terminal (VSS_ext.) 322 through the second FTV 306, the second P-I-N diode 318, and the first VB 308 and the second VB 310 to the external IO terminals (IOPAD) 324 and 326 to bypass the internal disturbed circuit 392 to protect the internal disturbed circuit 392 from ESD.

[0147] Figure 10 is a circuit diagram of an embodiment of the present application showing a device 300 having a power rail clamping circuit 394. The device 300 includes a substrate 302 having a front side 312 and a back side 314. The device 300 includes a first P-I-N diode 316, a second P-I-N diode 318, an external VDD power supply terminal (VDD_ext.) 320, an external VSS reference terminal (VSS_ext.) 322, and external IO terminals (IOPAD) 324, 326. The first P-I-N diode 316 and the second P-I-N diode 318 are located on the front side 312 of the substrate 302. The external VDD power supply terminal (VDD_ext.) 320, the external VSS reference terminal (VSS_ext.) 322, and the external IO terminals (IOPAD) 324, 326 are located on the back side 314 of the substrate 302. Figure 9

[0148] On the back side 314, the external VDD power supply terminal (VDD_ext.) 320 is electrically connected to a resistor R3, the external VSS reference terminal (VSS_ext.) 322 is electrically connected to a resistor R3, and the external IO terminals (IOPAD) 324, 326 are electrically connected to a resistor Rl. The distance between the external power / reference terminals and the external IO terminals is large so that the device 300 has no or includes no capacitance between the external terminals.

[0149] ​The first P-I-N diode 316 is electrically connected to the resistor R4, which is electrically connected to the internal VDD supply terminal (VDD int.) 364, which is electrically connected to the resistor R5, the first FTV 304, and the resistor R3, which is electrically connected to the external VDD supply terminal (VDD ext.) 320. The second P-I-N diode 318 is electrically connected to the resistor R4, which is electrically connected to the internal VSS reference terminal (VSS int.) 374, which is electrically connected to the resistor R5, the second FTV 306, and the resistor R3, which is electrically connected to the external VSS reference terminal (VSS ext.) 322.

[0150] The first P-I-N diode 316 and the second P-I-N diode 318 are electrically connected to the resistor R2', which is electrically connected to the internal IO terminal (PAD int.) 384. In addition, the first P-I-N diode 316 and the second P-I-N diode 318 are electrically connected to the resistors Rl and the external IO terminals (IOPAD) 324, 326 through the first VB 308 and the second VB 310.

[0151] The internal VDD supply terminal (VDD int.) 364 is electrically connected to the internal disturbed circuit 390, which is electrically connected to the internal IO terminal (PAD int.) 384. In addition, the internal VSS reference terminal (VSS int.) 374 is electrically connected to the internal disturbed circuit 392, which is electrically connected to the internal IO terminal (PAD int.) 384.

[0152] The supply rail clamping circuit 394 is electrically connected to the internal VDD supply terminal (VDD int.) 364 and the internal VSS reference terminal (VSS int.) 374. The internal VDD supply terminal (VDD int.) 364 is electrically connected to the external VDD supply terminal (VDD ext.) 320 through the resistor R5 and the resistor R3 (and, in some embodiments, other VBs or FTVs). In addition, the internal VSS reference terminal (VSS int.) 374 is electrically connected to the external VSS reference terminal (VSS ext.) 322 through the resistor R5 and the resistor R3 (and, in some embodiments, other VBs or FTVs).

[0153] In operation, the first P-I-N diode 316 shunts ESD current from the external IO terminals (IOPAD) 324, 326 through the first VB 308, the second VB 310, the first P-I-N diode 316, and the first FTV 304 to the external VDD power supply terminal (VDD ext.) 320 to bypass the internal disturbed circuit 390 to protect the internal disturbed circuit 390 from ESD. The second P-I-N diode 318 shunts ESD current from the external VSS reference terminal (VSS ext.) 322 through the second FTV 306, the second P-I-N diode 318, and the first VB 308 and the second VB 310 to the external IO terminals (IOPAD) 324, 326 to bypass the internal disturbed circuit 392 to protect the internal disturbed circuit 392 from ESD.

[0154] Figure 11 is a circuit diagram of an embodiment of the present application, illustrating a device 300' including IO signal channel impedance matching networks (IO signal channel impedance matching networks) 396, 398a, 398b. The device 300' is similar to the device 300 except for the IO signal channel impedance matching networks 396, 398a, 398b on the back side 314 of the device 300'. The IO signal channel impedance matching networks 396, 398a, 398b include at least one resistor, capacitor, and / or inductor for matching the impedance of the IO signal channel at the external IO terminals (IOPAD) 324, 326. In some embodiments, the IO signal channel impedance matching networks 396, 398a, 398b are used in analog circuits. In some embodiments, the IO signal channel impedance matching networks 396, 398a, 398b are used in radio frequency (RF) circuits. Figure 10

[0155] The device 300' includes a substrate 302 having a front side 312 and a back side 314, a first P-I-N diode 316, a second P-I-N diode 318, an external VDD power supply terminal (VDD ext.) 320, an external VSS reference terminal (VSS ext.) 322, and external IO terminals (IOPAD) 324, 326. The first P-I-N diode 316 and the second P-I-N diode 318 are on the front side 312 of the substrate 302. The external VDD power supply terminal (VDD ext.) 320, the external VSS reference terminal (VSS ext.) 322, and the external IO terminals (IOPAD) 324, 326 are on the back side 314 of the substrate 302.

[0156] ​Apart from the impedance matching networks 396, 398a, and 398b for the I / O signal channels, the electrical connection method and operation of device 300' are similar to those of other devices. Figure 10 Device 300' has a large distance between the external power supply / reference terminal and the external I / O terminal, so that device 300' has no or no capacitors between the external terminals. Instead, device 300' includes impedance matching networks 396, 398a, and 398b. One end of impedance matching network 396 is electrically connected to external I / O terminals (IOPADs) 324 and 326. The other end of impedance matching network 396 is electrically connected to one end of impedance matching network 398a and one end of impedance matching network 398b. The other end of impedance matching network 398a is electrically connected to external VDD power supply terminal (VDD_ext.) 320, and the other end of impedance matching network 398b is electrically connected to external VSS reference terminal (VSS_ext.) 322.

[0157] In operation, impedance matching networks 396, 398a, and 398b match the impedance of device 300' at external I / O terminals (IOPADs) 324 and 326 to the I / O signal path.

[0158] Figure 12 This is a flowchart illustrating a method for manufacturing an ESD protection circuit according to an embodiment of the present invention. In step 400, the method includes providing a substrate having a front side and a rear side. In some embodiments, the substrate is similar to... Figure 1 The substrate 22. In some embodiments, the front and rear sides are similar to the substrate 22. Figure 1 The front side 24 and the rear side 26 of the substrate 22.

[0159] In step 402, the method includes forming a PIN diode (e.g., PIN diode 28) on the front side of the substrate. Furthermore, in step 404, the method includes forming at least one through-hole through at least a portion of the substrate. In some embodiments, step 402 is performed before step 404; in some embodiments, step 402 is performed after step 404. In some embodiments, steps 402 and 404 are performed simultaneously.

[0160] In step 406, the method includes forming a plurality of front conductive layers (e.g., front conductive layer 32) electrically connected to the PIN diode on the PIN diode. In step 408, the method includes forming a plurality of rear conductive layers (e.g., rear conductive layer 34) electrically connected to at least one via on the rear side of the substrate. In some embodiments, step 406 is performed before step 408, and in some embodiments, step 406 is performed after step 408.

[0161] At step 410, the method includes forming a terminal electrically connecting the plurality of backside conductive layers at the backside of the substrate, wherein the terminal connects the P-I-N diode through the plurality of backside conductive layers and the at least one via.

[0162] In some embodiments, forming the at least one via includes forming a backside via through the substrate from the backside of the substrate to the frontside of the substrate (e.g., FTV 104 of FIG. 1), and forming the plurality of frontside conductive layers includes electrically connecting the plurality of frontside conductive layers to the FTV such that the plurality of backside conductive layers are electrically connected to the plurality of frontside conductive layers through the FTV. Figure 4

[0163] In some embodiments, forming the at least one via includes forming a backside via through the substrate from the backside of the substrate to a side of the P-I-N diode, and forming the plurality of backside conductive layers includes electrically connecting the plurality of backside conductive layers to the side of the P-I-N diode through the backside via. In some embodiments, forming the plurality of frontside conductive layers includes electrically connecting the plurality of frontside conductive layers to the side of the P-I-N diode such that the plurality of backside conductive layers are electrically connected to the plurality of frontside conductive layers through the backside via and the side of the P-I-N diode.

[0164] Figure 13 FIG. 1 is a block diagram of an example of a computer system 500 that provides a design, layout, and manufacturing of electronic devices, semiconductor devices, and methods according to embodiments of the present disclosure. The design, layout, and manufacturing of portions or all of a semiconductor device (also referred to as a semiconductor circuit) can be performed by or with the aid of the computer system 500. In addition, the design, layout, and manufacturing of portions or all of an electronic device can be performed by or with the aid of the computer system 500. In some embodiments, the computer system 500 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an IC.

[0165] ​In some embodiments, system 500 is a general purpose computing device that includes a processor 502 and a non-transitory computer readable storage medium 504. For example, computer readable storage medium 504 can be encoded with computer program code, e.g., executable instructions 506. The instructions 506 are executed by the processor 502 to provide, at least in part, a design tool that implements some or all of the functionality of system 500, e.g., pre-layout simulation, post-layout simulation, routing, re- routing, and final layout for manufacturing. In addition, manufacturing tools 508 are included to further layout and actually execute the design and manufacture of semiconductor devices. In some embodiments, the instructions 506 are executed by the processor 502 to provide, at least in part, a design tool that implements some or all of the functionality of system 500. In some embodiments, system 500 includes a commercial router. In some embodiments, system 500 includes an automatic place and route (APR) system.

[0166] The processor 502 is electrically coupled with the computer readable storage medium 504 and the I / O interface 512 through a bus 510. A network interface 514 is also connected to the processor 502 through the bus 510. The network interface 514 connects to a network 516, enabling the processor 502 and the computer readable storage medium 504 to connect to external elements using the network 516. The processor 502 is configured to execute computer program code or instructions 506 encoded in the computer readable storage medium 504 to cause system 500 to perform some or all of the functionality of system 500, e.g., to provide semiconductor devices and methods of the embodiments of the present application, as well as other functionality of system 500. In some embodiments, the processor 502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0167] In some embodiments, the computer-readable storage media 504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system or apparatus or device. For example, the computer-readable storage media 504 can include a semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In some embodiments using an optical disk, the computer-readable storage media 504 can include a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0168] In some embodiments, the computer-readable storage media 504 stores computer programs code or instructions 506 to cause the system 500 to perform some or all of the functions of the system 500. In some embodiments, the computer-readable storage media 504 also stores information to assist in performing some or all of the functions of the system 500. In some embodiments, the computer-readable storage media 504 stores a database 518 including at least one component library, a digital circuit cell library, and a database.

[0169] The system 500 includes an I / O interface 512 to couple external circuits. In some embodiments, the I / O interface 512 includes a keyboard, a keypad, a mouse, a trackball, a joy stick, a touch screen, and / or a cursor direction key to communicate information and commands to the processor 502.

[0170] The network interface 514 is coupled to the processor 502 and allows the system 500 to communicate with a network 516 that is connected to at least one other computer system. The network interface 514 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In some embodiments, some or all of the functions of the system 500 can be performed in two or more systems similar to the system 500.

[0171] System 500 is configured to receive information through I / O interface 512. Information received through I / O interface 512 includes at least one instruction, data, design rules, a library of components and cells, and / or other parameters to be processed by processor 502. The information is transferred by bus 510 to processor 502. In addition, system 500 is configured to receive information regarding a user interface (UI) through I / O interface 512. These UI information can be stored in computer-readable storage medium 504 as user interface (UI) 520.

[0172] In some embodiments, some or all of the functionality of system 500 can be implemented by a stand-alone software application executed by a processor. In some embodiments, some or all of the functionality of system 500 is implemented in a software application that is part of an additional software application. In some embodiments, some or all of the functionality of system 500 is implemented as a plug-in to a software application. In some embodiments, at least one function of system 500 is implemented in a software application that is part of an EDA tool. In some embodiments, some or all of the functionality of system 500 is implemented in a software application used by system 500. In some embodiments, a layout is generated using, for example, VIRTUOSO, available from CADENCE DESIGN SYSTEMS, Inc., or other suitable layout generation tool.

[0173] In some embodiments, wiring, layout, and other processes are implemented with the functionality of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as at least one optical disc, such as a digital versatile disc (DVD), a magnetic disc, such as a hard disc, a semiconductor memory, such as a ROM and a RAM, and a memory card, and the like.

[0174] As described above, embodiments of system 500 include manufacturing tools 508 to perform manufacturing processes of system 500. For example, based on a final layout, manufacturing optical photolithographic masks, manufacturing tools 508 use the optical photolithographic masks to manufacture semiconductor devices.

[0175] Detailed orientation of device manufacturing Figure 14 Disclosed, Figure 14is a block diagram of a semiconductor device manufacturing system 522 and a semiconductor device manufacturing flow related to the semiconductor device manufacturing system 522 according to embodiments of the present application. In some embodiments, the manufacturing system 522 is used to manufacture at least one semiconductor mask and / or at least one component in a layer of a semiconductor device based on a layout.

[0176] In Figure 14 In some embodiments, the semiconductor device manufacturing system 522 includes a plurality of entities, such as design houses 524, mask houses 526, and semiconductor device manufacturing houses / foundries 528 (also referred to as fabs), which interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacturing of semiconductor devices, such as the semiconductor devices described herein. The entities in the system 522 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a plurality of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with at least one other entity and provides services to and / or receives services from the other entity. In some embodiments, two or more of the design houses 524, mask houses 526, and semiconductor device manufacturing houses 528 are owned by a larger company. In some embodiments, two or more of the design houses 524, mask houses 526, and semiconductor device manufacturing houses 528 coexist in a common facility and use common resources.

[0177] A design house 524 (or design team) produces a semiconductor device design layout 530. The semiconductor device design layout 530 includes a plurality of geometric patterns or semiconductor device layout for a semiconductor device design. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up a plurality of elements of a semiconductor structure to be fabricated. Multiple layers are combined to form a plurality of semiconductor device features. For example, a portion of the semiconductor device design layout 530 includes openings for a plurality of semiconductor device features, such as diagonal vias, active regions, gate electrodes, sources, drains, metal lines, local vias, and bond pads, to be formed in a semiconductor substrate (e.g., a silicon wafer) and a plurality of material layers on the semiconductor substrate. The design house 524 performs a design flow to form the semiconductor device design layout 530. The semiconductor device design layout 530 is represented in at least one data file having geometric pattern information. For example, the semiconductor device design layout 530 can be represented in the form of a GDSII file or in the form of a DFII file. In some embodiments, the design flow includes at least one of analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design including power via design, supply voltage track design, reference voltage track design, placement and routing routines, and physical layout design.

[0178] A mask house 526 includes data preparation 523 and mask fabrication 534. The mask house 526 uses the semiconductor device design layout 530 to fabricate at least one mask 536 to be used to fabricate a plurality of layers of a semiconductor device or semiconductor structure. The mask 536 performs mask data preparation 532 in which the semiconductor device design layout 530 is translated into a representative data file (RDF). The mask data preparation 532 provides the RDF to the mask fabrication 534. The mask fabrication 534 includes a mask writer that converts the RDF into an image on a substrate, such as a mask (reticle) 536 or a semiconductor wafer 538. The semiconductor device design layout 530 is processed by the mask data preparation 532 to conform to characteristics of the mask writer and / or guidelines of the semiconductor foundry 528. In some embodiments, the mask data preparation 532 includes a plurality of steps, such as a pre- processing step, a mask data preparation step, and a post-processing step. The mask data preparation 532 can include a plurality of steps to convert the semiconductor device design layout 530 into a mask data file (MDF) that is used by the mask writer to form the mask 536. The mask data preparation 532 can include a plurality of steps to convert the semiconductor device design layout 530 into a wafer data file (WDF) that is used by the mask writer to form the semiconductor wafer 538. Figure 14In some embodiments, mask data preparation 532 and mask manufacturing 534 are represented as separate elements. In some embodiments, mask data preparation 532 and mask manufacturing 534 can be collectively referred to as mask data preparation

[0179] In some embodiments, mask data preparation 532 includes optical proximity correction (OPC), which compensates for image errors, such as those caused by refraction, interference, other process effects, etc., using lithography enhancement techniques. OPC adjusts the semiconductor device design layout 530. In some embodiments, mask data preparation 532 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is used, which treats OPC as an inverse imaging problem.

[0180] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC), which checks the semiconductor device design layout 530 for processes performed in OPC against a set of mask manufacturing rules that include specific geometric and / or connectivity restrictions to ensure adequate margins in light of variations in semiconductor processes, etc. In some embodiments, the MRC modifies the semiconductor device design layout 530 to compensate for restrictions during mask manufacturing 534, and the MRC can undo some of the modifications performed by OPC to comply with the mask manufacturing rules.

[0181] In some embodiments, mask data preparation 532 includes lithography process checking (LPC), which simulates a process to be performed by semiconductor device foundry 528. LPC simulates this process based on the semiconductor device design layout 530 to manufacture a simulated manufactured device. Process parameters in the LPC simulation can include parameters related to multiple processes of a semiconductor device manufacturing cycle, parameters related to tools used to manufacture the semiconductor device, and / or other aspects of the process. The LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc., or combinations thereof. In some embodiments, after the simulated manufactured device has been manufactured by the LPC, if the simulated device is not close enough in appearance to satisfy design rules, OPC and / or MRC are repeated to further improve the semiconductor device design layout 530.

[0182] The above description of mask data preparation 532 is simplified for clarity. In some embodiments, data preparation 532 includes additional features, such as logic operations (LOP), to modify the semiconductor device design layout 530 according to manufacturing rules. Furthermore, the processes applied to the semiconductor device design layout 530 during data preparation 532 can be performed in a variety of different orders.

[0183] After mask data preparation 532 and during mask manufacturing 534, a mask 536 or a set of masks 536 is manufactured based on the modified semiconductor device design layout 530. In some embodiments, mask manufacturing 534 includes performing at least one lithographic exposure based on the semiconductor device design layout 530. In some embodiments, an electron beam (e-beam) or multiple e-beam mechanism is used to form a pattern on a mask (photomask or reticle) based on the modified semiconductor device design layout 530. The mask 536 can be formed in various techniques. In some embodiments, the mask 536 is formed using binary technology. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation (e.g., an ultraviolet (UV) beam) used to expose a layer of image sensitive material (e.g., photoresist) coated on a wafer is blocked by the opaque regions and penetrates the transparent regions. In one example, a binary mask version of the mask 536 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 536 is formed using phase shift technology. In a phase shift mask (PSM) version of the mask 536, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to improve resolution and image quality. In various examples, the phase shift photomask can be an attenuated PSM or an alternating PSM. The mask produced by mask manufacturing 534 is used in various processes. For example, the photomask is used to form doped regions in a semiconductor wafer 538 in an ion implantation process, to form etched regions in the semiconductor wafer 538 in an etching process, and / or in other suitable processes.

[0184] A semiconductor device foundry includes wafer fabrication 540. The semiconductor device foundry 528 is a semiconductor manufacturer that includes at least one manufacturing facility to manufacture a plurality of different semiconductor device products. In some embodiments, the semiconductor device foundry 528 is a semiconductor fabrication plant. There can be manufacturing facilities for front end of line (FEOL) manufacturing of a plurality of semiconductor device products, second manufacturing facilities that provide back end of line (BEOL) manufacturing for connection and packaging of the semiconductor device products, and third manufacturing facilities that provide other services for the foundry.

[0185] A semiconductor device foundry 528 uses the mask 536 manufactured by the mask foundry 526 to manufacture a semiconductor structure or semiconductor device 542 of the embodiments of the present application. Thus, the semiconductor device foundry 528 uses the semiconductor device design layout 530, at least indirectly, to manufacture the semiconductor structure or semiconductor device 542 of the embodiments of the present application. Further, the semiconductor wafer 538 includes a silicon substrate or other suitable substrate having material layers formed thereon, and includes one or more of a variety of doped regions, dielectric features, multilevel interconnects, etc. (formed in later manufacturing steps). In some embodiments, the semiconductor wafer 538 is manufactured by the semiconductor device foundry 528 using the mask 536 to form the semiconductor structure or semiconductor device 542 of the embodiments of the present application. In some embodiments, the semiconductor device manufacturing includes performing at least one photolithographic exposure based, at least indirectly, on the semiconductor device design layout 530.

[0186] The embodiments of the present application thus provide an ESD protection circuit and structure including a device including a substrate having a front side and a back side, a P-I-N diode positioned on the front side of the substrate, and a termination positioned under the back side of the substrate. A plurality of front side conductive layers are positioned on the P-I-N diode and electrically connected to the first P-I-N diode, and a plurality of back side conductive layers are positioned under the back side of the substrate and electrically connected to the termination. The termination is electrically connected to the P-I-N diode through the plurality of back side conductive layers and at least one via (e.g., FTV or VB).

[0187] In some embodiments, the at least one via includes an FTV extending through the substrate from the back side of the substrate to the front side of the substrate, wherein the plurality of back side conductive layers are electrically connected to the plurality of front side conductive layers through the FTV. In some embodiments, the at least one via includes a VB extending through the substrate from the back side of the substrate to a side of the P-I-N diode, wherein the plurality of back side conductive layers are electrically connected to the side of the P-I-N diode through the VB. In some embodiments, the plurality of back side conductive layers are electrically connected to the plurality of front side conductive layers through the VB and the side of the P-I-N diode.

[0188] In some embodiments, the device has or includes no capacitance between the power / reference termination and the IO termination, e.g., between the VDD power termination and the IO termination and / or between the IO termination and the VSS reference termination. Further, in some embodiments, the device includes an impedance matching network to match the impedance of the device to the IO signal path, wherein the impedance matching network includes at least one capacitance, inductance, and / or resistance.

[0189] According to some embodiments, a semiconductor device includes a substrate having a front side and a back side, a first P-I-N diode on the front side of the substrate, a first terminal under the back side of the substrate, a plurality of front side conductive layers, and a plurality of back side conductive layers. The plurality of front side conductive layers are on and electrically connected to the first P-I-N diode. The plurality of back side conductive layers are under the back side of the substrate and electrically connected to the first terminal, the first terminal being electrically connected to the first P-I-N diode through at least one via hole in the plurality of back side conductive layers and the substrate.

[0190] In some embodiments, the semiconductor device further includes a feed-through via hole. The feed-through via hole extends through the substrate from the back side of the substrate to the front side of the substrate, wherein the plurality of back side conductive layers are electrically connected to the plurality of front side conductive layers through the feed-through via hole.

[0191] In some embodiments, the semiconductor device further includes a back side via hole. The back side via hole extends through the substrate from the back side of the substrate to a side of the first P-I-N diode, wherein the plurality of back side conductive layers are electrically connected to the side of the first P-I-N diode through the back side via hole.

[0192] In some embodiments, the plurality of front side conductive layers are electrically connected to the side of the first P-I-N diode, such that the plurality of back side conductive layers are electrically connected to the plurality of front side conductive layers through the back side via hole and the side of the first P-I-N diode.

[0193] In some embodiments, the first terminal is one of a power supply terminal, a reference terminal, and an input / output (IO) terminal.

[0194] In some embodiments, the semiconductor device further includes a power rail clamping circuit. The power rail clamping circuit is electrically connected to the plurality of front side conductive layers.

[0195] In some embodiments, the semiconductor device further includes a second P-I-N diode on the front side of the substrate and a second terminal under the back side of the substrate, wherein the plurality of front side conductive layers are electrically connected to the second P-I-N diode and the plurality of back side conductive layers are electrically connected to the second terminal.

[0196] In some embodiments, the second terminal is electrically connected to the second P-I-N diode through the plurality of back side conductive layers that are electrically connected to the plurality of front side conductive layers.

[0197] In some embodiments, the semiconductor device further includes a capacitor. The capacitor has one end connected to the first terminal and another end connected to the second terminal.

[0198] In some embodiments, the semiconductor device further includes a feedthrough via and a backside via. The feedthrough via extends through the substrate from the backside of the substrate to the frontside of the substrate, wherein the plurality of backside conductive layers electrically connect the plurality of frontside conductive layers through the feedthrough via. The backside via extends through the substrate from the backside of the substrate to a side of the first P-I-N diode, wherein the plurality of backside conductive layers electrically connect the side of the first P-I-N diode through the backside via.

[0199] According to other embodiments, a device includes a substrate having a frontside and a backside, a first P-I-N diode on the frontside of the substrate, a first terminal under the backside of the substrate, a second terminal under the backside of the substrate, a first frontside conductive path, a second frontside conductive path, a first backside conductive path, and a second backside conductive path. The first frontside conductive path is on and electrically connects a first side of the first P-I-N diode. The second frontside conductive path is on and electrically connects a second side of the first P-I-N diode. The first backside conductive path is under the backside of the substrate and electrically connects the first terminal. The second backside conductive path is under the backside of the substrate and electrically connects the second terminal. The device further includes an FTV and a first VB. The FTV extends through the substrate from the backside of the substrate to the frontside of the substrate, wherein the first backside conductive path electrically connects the first frontside conductive path through the FTV. The first VB extends through the substrate from the backside of the substrate to the second side of the first P-I-N diode, wherein the second backside conductive path electrically connects the second side of the first P-I-N diode through the first VB.

[0200] In some embodiments, the second backside conductive path electrically connects the second frontside conductive path through the first backside via and the second side of the first P-I-N diode.

[0201] In some embodiments, the first terminal is a power terminal or a reference terminal, and the second terminal is an input / output (IO) terminal.

[0202] In some embodiments, the semiconductor device further includes a power rail clamping circuit. The power rail clamping circuit electrically connects the plurality of frontside conductive layers.

[0203] In some embodiments, the semiconductor device further includes a second P-I-N diode and a third backside conductive path. The second P-I-N diode is on the frontside of the substrate, wherein the second frontside conductive path electrically connects a first side of the second P-I-N diode. The third backside conductive path electrically connects the second terminal or a third terminal under the backside of the substrate.

[0204] In some embodiments, the second terminal or the third terminal is electrically connected to the first side of the second P-I-N diode through a third backside conductive path, the third backside conductive path is electrically connected to the second frontside conductive path through the second backside via and the first side of the second P-I-N diode.

[0205] According to other embodiments, a method of fabricating an ESD protection circuit is provided. The method includes providing a substrate having a frontside and a backside; forming a P-I-N diode in the frontside of the substrate; forming at least one via through at least a portion of the substrate; forming a plurality of frontside conductive layers electrically connected to the P-I-N diode on the P-I-N diode; forming a plurality of backside conductive layers electrically connected to the at least one via under the backside of the substrate; and forming a terminal electrically connected to the plurality of backside conductive layers under the backside of the substrate, wherein the terminal connects the P-I-N diode through the plurality of backside conductive layers and the at least one via.

[0206] In some embodiments, the operation of forming the at least one via includes forming a feedthrough via. The feedthrough via passes through the substrate from the backside of the substrate to the frontside of the substrate. The operation of forming the plurality of frontside conductive layers includes electrically connecting the plurality of frontside conductive layers to the feedthrough via such that the plurality of backside conductive layers are electrically connected to the plurality of frontside conductive layers through the feedthrough via.

[0207] In some embodiments, the operation of forming the at least one via includes forming a backside via. The backside via passes through the substrate from the backside of the substrate to a side of the P-I-N diode. The operation of forming the plurality of backside conductive layers includes electrically connecting the plurality of backside conductive layers to the side of the P-I-N diode through the backside via.

[0208] In some embodiments, the operation of forming the plurality of frontside conductive layers includes electrically connecting the plurality of frontside conductive layers to the side of the P-I-N diode such that the plurality of backside conductive layers are electrically connected to the plurality of frontside conductive layers through the backside via and the side of the P-I-N diode.

[0209] The embodiments are generally described so that one of ordinary skill in the art can better understand the present application. One of ordinary skill in the art should appreciate that they can readily use the present application as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same benefits as the embodiments described above. One of ordinary skill in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present application, and that they should not be construed as limiting the present application.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a front side and a rear side; A first PIN diode is located on the front side of the substrate; A first terminal is located on the rear side of the substrate; Multiple front conductive layers are located on and electrically connected to the first PIN diode; and Multiple rear conductive layers are located on the rear side of the substrate and are electrically connected to the first terminal; The first terminal is electrically connected to the first PIN diode through multiple rear conductive layers and at least one through-hole in the substrate.

2. The semiconductor device as claimed in claim 1, characterized in that, It also includes a feed via that extends through the substrate from the rear side to the front side of the substrate, wherein a plurality of the rear conductive layers are electrically connected to a plurality of the front conductive layers through the feed via.

3. The semiconductor device as claimed in claim 1, characterized in that, It also includes a rear-side via that extends from the rear side of the substrate to one side of the first PIN diode through the substrate, wherein a plurality of the rear-side conductive layers are electrically connected to the side of the first PIN diode through the rear-side via. The plurality of the front conductive layers are electrically connected to the side of the first PIN diode, such that the plurality of rear conductive layers are electrically connected to the plurality of front conductive layers through the rear via and the side of the first PIN diode.

4. The semiconductor device as claimed in claim 1, characterized in that, The first terminal is one of a power terminal, a reference terminal, and an input / output terminal.

5. The apparatus as claimed in claim 1, characterized in that, It also includes a power rail clamping circuit that is electrically connected to the plurality of the front conductive layers.

6. The semiconductor device as claimed in claim 1, characterized in that, It also includes a second PIN diode and a second terminal, the second PIN diode being located on the front side of the substrate and the second terminal being located on the rear side of the substrate, wherein a plurality of the front conductive layers are electrically connected to the second PIN diode and a plurality of the rear conductive layers are electrically connected to the second terminal; The second terminal is electrically connected to the second PIN diode via multiple rear conductive layers connected to multiple front conductive layers; The semiconductor device also includes a capacitor having one end connected to the first terminal and the other end connected to the second terminal.

7. The semiconductor device as claimed in claim 1, characterized in that, It also includes a feed via and a rear via. The feed via extends through the substrate from the rear side to the front side of the substrate, wherein a plurality of rear conductive layers are electrically connected to a plurality of front conductive layers through the feed via. The rear via extends through the substrate from the rear side to one side of the first PIN diode, wherein a plurality of rear conductive layers are electrically connected to that side of the first PIN diode through the rear via.

8. A semiconductor device, characterized in that, include: A substrate having a front side and a rear side; A first PIN diode is located on the front side of the substrate; A first terminal is located on the rear side of the substrate; A second terminal is located on the rear side of the substrate; A first front conductive path is located on a first side of the first PIN diode and is electrically connected to the first side of the first PIN diode; A second front conductive path is located on a second side of the first PIN diode and is electrically connected to the second side of the first PIN diode; A first rear conductive path is located on the rear side of the substrate and electrically connected to the first terminal; A second rear-side conductive path is located on the rear side of the substrate and electrically connected to the second terminal; A feed via extends through the substrate from the rear side to the front side of the substrate, wherein the first rear conductive path is electrically connected to the first front conductive path through the feed via. as well as A first rear-side via extends through the substrate from the rear side of the substrate to the second side of the first PIN diode, wherein the second rear-side conductive path is electrically connected to the second side of the first PIN diode through the first rear-side via.

9. The semiconductor device as claimed in claim 8, characterized in that, The second rear conductive path is electrically connected to the second front conductive path through the first rear via and the second side of the first PIN diode.

10. The semiconductor device as claimed in claim 8, characterized in that, It also includes a second PIN diode and a third rear-side conductive path. The second PIN diode is located on the front side of the substrate, wherein the second front-side conductive path is electrically connected to a first side of the second PIN diode, and the third rear-side conductive path is electrically connected to the second terminal or a third terminal located on the rear side of the substrate. The second terminal or the third terminal is electrically connected to the first side of the second PIN diode through the third rear conductive path, and the third rear conductive path is electrically connected to the second front conductive path through a second rear via and the first side of the second PIN diode.

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