Semiconductor package

Abstract

The utility model provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device die and a second device die stacked over the first device die; a plurality of functional bumps disposed between the first device die and the second device die and electrically connected to the first device die and the second device die; and a first sealing ring including at least one dummy bump disposed along a plurality of edges of the first device die and disposed between the first device die and the second device die, and laterally surrounding the plurality of functional bumps.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor packages. BACKGROUND

[0002] The semiconductor industry is continually striving to reduce the feature size and power consumption of various electronic components, while increasing the device density, wiring density, and operating frequency of electronic components. These advanced electronic components also require smaller packages that occupy less area than past packages.

[0003] Three-dimensional integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple dies are stacked on top of one another. 3DICs provide higher integration density and other advantages, such as higher operating speeds and higher bandwidth, due to the reduced interconnect length between stacked dies. However, there are still challenges to overcome with 3DIC technology. For example, connections configured to connect multiple dies vertically separated in a 3DIC can be subject to damage from stress or intrusion of moisture and / or chemicals, and can have low reliability. SUMMARY

[0004] Embodiments of the present application provide a semiconductor package including a first device die and a second device die stacked on top of the first device die; a plurality of functional bumps disposed between the first device die and the second device die and electrically connected to the first device die and the second device die; and a first sealing ring including a plurality of dummy bumps disposed along edges of the first device die and between the first device die and the second device die, and laterally surrounding the plurality of functional bumps.

[0005] Embodiments of the present application provide a semiconductor package including a first device die and a second device die stacked on top of the first device die; a plurality of functional bumps disposed between the first device die and the second device die and electrically connected to the first device die and the second device die; and a first sealing ring including a plurality of dummy bumps disposed along edges of the first device die and between the first device die and the second device die, and laterally surrounding the plurality of functional bumps. BRIEF DESCRIPTION OF DRAWINGS

[0006] The various aspects of the present disclosure will be best understood with the aid of the following detailed description read in light of the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0007] FIG. 1A is a schematic cross-sectional view showing a semiconductor package according to some embodiments of the present disclosure.

[0008] FIG. 1B is a schematic plan view of a semiconductor package according to some embodiments of the present disclosure. FIG. 1A

[0009] FIG. 1C is a schematic cross-sectional view showing a dummy substrate via and surrounding features in the semiconductor package shown in FIG. 1A

[0010] FIG. 2A to FIG. 2C is a schematic cross-sectional view showing a process for joining a bottom device die to an intermediate re-routed structure in the semiconductor package shown in FIG. 1A

[0011] FIG. 3A to FIG. 3H is a schematic cross-sectional view showing an overall process for forming a semiconductor package according to some embodiments of the present disclosure. FIG. 1A

[0012] FIG. 4 is a schematic cross-sectional view showing a semiconductor package according to some embodiments of the present disclosure.

[0013] FIG. 5A to FIG. 5E is a schematic plan view showing a semiconductor package according to some embodiments of the present disclosure.

[0014] FIG. 6A is a schematic cross-sectional view showing a package seal ring in the semiconductor package shown in FIG. 5D

[0015] FIG. 6B is a schematic cross-sectional view showing a package seal ring in the semiconductor package shown in FIG. 5D

[0016] FIG. 6C is a schematic cross-sectional view showing a package seal ring in the semiconductor package shown in FIG. 5E

[0017] ​​​​​​​FIG. 7A is a schematic cross-sectional view showing a semiconductor package according to some embodiments of the present disclosure.

[0018] FIG. 7B is a schematic plan view of a semiconductor package according to some embodiments of the present disclosure. FIG. 7A is a schematic plan view of a semiconductor package shown in

[0019] FIG. 8 is a schematic cross-sectional view showing a semiconductor package according to some embodiments of the present disclosure.

[0020] FIG. 9A to FIG. 9E is a schematic cross-sectional view showing a process for forming a semiconductor package according to some embodiments of the present disclosure. FIG. 8 is a schematic cross-sectional view showing a process for forming a semiconductor package shown in

[0021] [Explanation of symbols]

[0022] 10, 40, 50a, 50b, 50c, 50d, 50e, 70, 80: semiconductor package

[0023] 102, 115: semiconductor substrate

[0024] 100a, 100b: device die

[0025] 104, 116: metallization layer

[0026] 104d: dummy conductive member

[0027] 106, 111, 118, 124, 146: dielectric layer

[0028] 108, 120: wiring element

[0029] 108d: dummy wiring element

[0030] 109: liner

[0031] 110: backside redistribution structure

[0032] 112: conductive pad

[0033] 112d, 128d: dummy conductive pad

[0034] 112f, 128f: functional conductive pad

[0035] 114: substrate via

[0036] 114f: functional substrate via

[0037] 114d: dummy substrate via

[0038] 122, 144: redistribution structure

[0039] 126, 148: redistribution line elements

[0040] 130: bump

[0041] 130d, 130dl, 130d2, 130d3, 130d4, 130d5, 130d6, 130d7, 130d8, 130d9: dummy bump

[0042] 130f: functional bump

[0043] 132: conductive pillar

[0044] 134: solder layer

[0045] 136, 138: bonding layer

[0046] 140, 142: encapsulation

[0047] 150: package input / output

[0048] 152: encapsulation via

[0049] 154: dummy die

[0050] 156, 158: region

[0051] 300: support substrate

[0052] 302, 312: tape

[0053] 304, 314: frame

[0054] 306, 308, 900: carrier substrate

[0055] 310: adhesive material

[0056] 400: underfill

[0057] DSR: die seal ring

[0058] PSR: package seal ring DETAILED DESCRIPTION

[0059] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features do not directly contact. In addition, the present disclosure can repeat reference numerals and / or letters in each example. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0060] In addition, for the purpose of convenience and brevity, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for describing the relationships between one element or feature and another element or feature as illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0061] The present disclosure provides a solution for enhancing the reliability of a plurality of connectors for establishing connections between a plurality of dies in a three-dimensional semiconductor package (or 3DIC) that are vertically separated.

[0062] FIG. 1A FIG. 1 is a schematic cross-sectional view illustrating a semiconductor package 10 according to some embodiments of the present disclosure.

[0063] The semiconductor package 10 is a three-dimensional semiconductor package, and device dies 100a and 100b in the semiconductor package 10 are arranged in a stacked manner. Specifically, the device die 100b is stacked on the device die 100a, and the device dies 100a and 100b are connected to each other through vertical and lateral conduction paths established therebetween. The device dies 100a and 100b can be the same or different in terms of functionality, size, and / or technology node.

[0064] Device die 100a includes a semiconductor substrate 102 having a front side and a back side facing away from the front side. A plurality of active devices (not shown) can be disposed on the front side of semiconductor substrate 102, and a plurality of metallization layers 104 (only a single one is shown) including a plurality of conductive features for interconnecting the plurality of active devices are stacked on top of the plurality of active devices. In addition, a plurality of dielectric layers 106 can be formed on top of the plurality of metallization layers 104, and a plurality of wiring elements 108 embedded in the plurality of dielectric layers 106 connect the plurality of conductive features in the plurality of metallization layers 104 to the front side of device die 100a

[0065] According to the face-to-back die stack configuration, when the active side of device die 100a faces away from overlying device die 100b, the back side of device die 100a then faces toward device die 100b. In some embodiments, the back side of device die 100a is defined by a back side redistribution layer structure 110 formed on a liner layer 109 covering the back side of semiconductor substrate 102. Back side redistribution layer structure 110 can include at least one dielectric layer 111 and a plurality of conductive patterns (e.g., a plurality of conductive pads 112) extending in dielectric layer 111. To establish connections from the front side to the back side of semiconductor substrate 102, a plurality of through substrate vias 114 are formed through semiconductor substrate 102. In those embodiments where liner layer 109 and plurality of conductive pads 112 are disposed on the back side of semiconductor substrate 102, plurality of through substrate vias 114 extend through liner layer 109 to contact plurality of conductive pads 112. Since some of the plurality of through substrate vias 112 are involved in signal transmission, these through substrate vias 114 are also referred to as functional through substrate vias 114f. In those embodiments where plurality of through substrate vias 114 extend to plurality of conductive pads 112, the conductive pads 112 in contact with functional through substrate vias 114f are referred to as functional conductive pads 112f. In addition to functional through substrate vias 114f, plurality of through substrate vias 114 can also include a plurality of dummy through substrate vias 114d, which can not be involved in signal transmission and are electrically floating or grounded. To protect plurality of functional through substrate vias 114f from possible damage during die singulation, plurality of dummy through substrate vias 114d are arranged separately along the edges of device die 100a and laterally surround plurality of functional through substrate vias 114f. In those embodiments where plurality of through substrate vias 114 extend to plurality of conductive pads 112, the plurality of conductive pads 112 in contact with plurality of dummy through substrate vias 114d are referred to as dummy conductive pads 112d. Since plurality of functional through substrate vias 114f are surrounded by plurality of dummy through substrate vias 114d, plurality of functional conductive pads 112f covering plurality of functional through substrate vias 114f are laterally surrounded by plurality of dummy conductive pads 112d covering plurality of dummy through substrate vias 114d.

[0066] Similar to the device die 100a, the device die 100b includes a semiconductor substrate 115 having a front side and a back side opposite the front side. A plurality of active devices (not shown) can be formed on the front side of the semiconductor substrate 115 and a plurality of metallization layers 116 (only a single one is shown) including a plurality of conductive features for interconnecting the plurality of active devices are stacked on top of the plurality of active devices. Also, a plurality of dielectric layers 118 can be formed on top of the plurality of metallization layers 116 and a plurality of wiring elements 120 embedded in the plurality of dielectric layers 118 connect the plurality of conductive features in the plurality of metallization layers 116 to the front side of the device die 100b. According to the face-to-back die stacking configuration, the front side of the device die 100b faces the back side of the device die 100a. On the other hand, the back side of the device die 100b faces away from the device die 100a. Unlike the device die 100a, the device die 100b can not include a substrate via and the back side of the device die 100b can be defined by the back side of the semiconductor substrate 115.

[0067] A redistribution line structure 122 is interposed between the device die 100a, the device die 100b for redistributing the plurality of terminals of the device die 100b and establishing connections between the device die 100a, the device die 100b. Specifically, the redistribution line structure 122 includes a stack of a plurality of dielectric layers 124 and a plurality of redistribution line elements 126 interspersed in the stack of the plurality of dielectric layers 124. According to some embodiments, the dielectric layers 124 are implemented by polymer layers. In addition, the redistribution line elements 126 include a combination of conductive patterns and conductive vias. Some of the redistribution line elements 126 connect the plurality of terminals of the device die 100b (e.g., provided by some of the wiring elements 120) to locations that are aligned with the plurality of terminals of the device die 100a (e.g., provided by the conductive pads 112). Specifically, a plurality of functional conductive pads 128f of the plurality of redistribution line elements 126 overlap a plurality of functional conductive pads 112f of the device die 100a, while a plurality of dummy conductive pads 128d of the plurality of redistribution line elements 126 overlap a plurality of dummy conductive pads 112d of the device die 100a. As mentioned above, the plurality of dummy conductive pads 112d are arranged around the plurality of functional conductive pads 112f, thus the plurality of dummy conductive pads 128f covering the plurality of dummy conductive pads 112d can be arranged around the plurality of functional conductive pads 128f covering the plurality of functional conductive pads 112f.

[0068] The plurality of bumps 130 are used to electrically connect the plurality of functional conductive pads 128f, the plurality of dummy conductive pads 128d in the redistribution line structure 122 to the plurality of functional conductive pads 112f, the plurality of dummy conductive pads 112d of the device die 100a. Specifically, the plurality of functional bumps 130f establish electrical connections between the plurality of functional conductive pads 128f, 112f, and the plurality of dummy bumps 130d establish electrical connections between the plurality of dummy conductive pads 128d, 112d. Since the plurality of functional conductive pads 112f are laterally surrounded by the plurality of dummy conductive pads 112d, the plurality of functional bumps 130f on the plurality of functional conductive pads 112f are laterally surrounded by the plurality of dummy bumps 130d on the plurality of dummy conductive pads 112d.

[0069] A package seal ring PSR is formed by the plurality of dummy substrate vias 114d and the plurality of dummy conductive pads 112d in the device die 100a, the plurality of dummy conductive pads 128d in the redistribution line structure 122, and the plurality of dummy bumps 130d between the device die 100a and the redistribution line structure 122 electrically connecting to each other. The plurality of functional substrate vias 114f and the plurality of functional conductive pads 112f in the device die 100a, the plurality of functional conductive pads 128f in the redistribution line structure 122, and the plurality of functional bumps 130f between the device die 100a and the redistribution line structure 122 are laterally surrounded by, and can be protected by, the package seal ring PSR from damage caused by stress and / or moisture / chemicals laterally entering the semiconductor package 10 during singulation of the semiconductor package 10. Thus, as an analogous effect to the functional substrate vias 114f and the functional conductive pads 112f, 128f, the reliability of the functional bumps 130f can be effectively improved.

[0070] In some embodiments, the bumps 130 are implemented by micro bumps. As an example, each bump 130 can include a pair of conductive pillars 132 and a solder layer 134 between the pair of conductive pillars 132. The plurality of conductive pillars 132 in each functional bump 130f can respectively contact one of the plurality of functional conductive pads 128f and one of the plurality of functional conductive pads 112f. On the other hand, the plurality of conductive pillars 132 in each dummy bump 130d can respectively contact one of the plurality of dummy conductive pads 128d and one of the plurality of dummy conductive pads 112d.

[0071] Further, according to some embodiments, the plurality of bumps 130 are confined in the plurality of openings of the bonding layer 136, the bonding layer 138. The bonding layer 136 extends along the backside of the semiconductor substrate 102 in the device die 100a, and can cover the backside redistribution line structure 110. On the other hand, the bonding layer 138 extends along the bottommost dielectric layer 124 of the redistribution line structure 122, and is bonded with the bonding layer 136. The plurality of conductive pillars 132 in each bump 130 are laterally surrounded by the bonding layer 136, the bonding layer 138, respectively. In addition, the solder layer 134 in each bump 130 can be embedded in one of the bonding layer 136, the bonding layer 138 (e.g., embedded in the bonding layer 136, as shown). According to some embodiments, the bonding layer 136, the bonding layer 138 are each implemented by a polymer layer. FIG. 1A

[0072] In some embodiments, the bonding layer 136 is monolithicized with the device die 100a, and thus the plurality of sidewalls of the bonding layer 136 can be substantially coplanar with the plurality of sidewalls of the device die 100a, which can be defined by the plurality of sidewalls of the backside redistribution line structure 110, the liner 109, the semiconductor substrate 102, the plurality of metallization layers 104, and the plurality of dielectric layers 106. Further, the monolithicized device die 100a and the bonding layer 136 can be laterally encapsulated by the encapsulant 140. The device die 100a and the bonding layer 136 are embedded in the encapsulant 140, while the redistribution line structure 122 on top of the bonding layer 138 extends above the encapsulant 140. Thus, in addition to being in lateral contact with the device die 100a and the bonding layer 136, the encapsulant 140 can also be in contact with the bonding layer 138 from below.

[0073] Similar to the device die 100a, the device die 100b is also encapsulated. The encapsulant 142 laterally encapsulating the device die 100b can be on the redistribution line structure 122, and vertically separated from the encapsulant 140 encapsulating the device die 100a and the bonding layer 136 by the redistribution line structure 122 and the bonding layer 138. That is, the device die 100a, the device die 100b can be encapsulated by respective encapsulants (e.g., the encapsulant 140, the encapsulant 142) vertically spaced apart from each other.

[0074] ​While the device die 100a and the overlying device die 100b are in communication through the redistribution line structure 122 therebetween, another redistribution line structure 144 can be configured beneath the device die 100a and the encapsulant 140 for routing the device dies 100a, 100b to another side of the redistribution line structure 144. Similar to the redistribution line structure 122, the redistribution line structure 144 can include a stack of a plurality of dielectric layers 146 and a plurality of redistribution line elements 148 interspersed in the stack of the plurality of dielectric layers 146. Depending on the face-to-back die stack configuration, the stack of the plurality of dielectric layers 146 can be disposed along the front side of the device die 100a and the bottom side of the encapsulant 140, and the plurality of redistribution line elements 148 can make contact with a plurality of front side terminals of the device die 100a (which can be provided by the plurality of wire elements 108). In some embodiments, the plurality of front side terminals can be routed by the plurality of redistribution line elements 148 to a plurality of package input / output (I / O) 150 configured along the bottom side of the redistribution line structure 144. As an example, the plurality of package I / O 150 can be implemented by C4 bumps.

[0075] According to some embodiments, the semiconductor package 10 is singulated through the cut through the encapsulant 140, the encapsulant 142, the redistribution line structure 122, the redistribution line structure 144, and the bonding layer 138. In these embodiments, the sidewalls of the encapsulant 140, the encapsulant 142, the redistribution line structure 122, the redistribution line structure 144, and the bonding layer 138 are substantially coplanar.

[0076] Further, in some embodiments, the device die 100b is laterally offset with respect to the device die 100a. In these embodiments, a first portion of the device die 100b overlaps the device die 100a, while a second portion of the device die 100b is outside the extent of the device die 100a. As such, the second portion of the device die 100b can be in contact with the redistribution line structure 144 through the redistribution line structure 122, the bonding layer 138, and the encapsulant 140, without the device die 100a in between. Additionally, a plurality of encapsulant vias 152 (only a single one shown) can be configured to make connections between the second portion of the device die 100b and the redistribution line structure 144. Specifically, the plurality of encapsulant vias 152 alongside the device die 100a can pass through the encapsulant 140 and the bonding layer 138, and engage with the redistribution line structure 122, the redistribution line structure 144 through opposite ends. The plurality of terminals of the device die 100b within the second portion of the device die 100b can be connected to the plurality of redistribution line elements 148 in the redistribution line structure 144 through the plurality of redistribution line elements 126 in the redistribution line structure 122 and the plurality of encapsulant vias 152, and can be further routed to the plurality of package I / O 150 via the plurality of redistribution line elements 148 in the redistribution line structure 144.

[0077] Further, in embodiments where the device die 100b is laterally offset from the device die 100a, dummy dies 154 (or more) can be further embedded in the encapsulant 142 to balance the non-uniformity of the coefficient of thermal expansion across the encapsulant 142. For example, when the device die 100b is offset to the right of the position directly above the device die 100a, a dummy die 154 can be disposed to the left of the offset device die 100b. The dummy die 154 can not be formed with circuitry. By way of example, the dummy die 154 can be implemented by a wafer of semiconductor material having a thickness substantially the same as the thickness of the encapsulant 142.

[0078] FIG. 1B is a schematic plan view of a semiconductor package 10 according to some embodiments of the present disclosure. It should be noted that, for the purpose of illustration, FIG. 1B only a few elements in the semiconductor package 10 are shown.

[0079] Referring to FIG. 1B , the device die 100a, the device die 100b, and the dummy die 154 are located within the boundary of the semiconductor package 10, which can be defined by the sidewalls of the encapsulant 140, the encapsulant 142, the redistribution line structure 122, the redistribution line structure 144, and the bonding layer 138. In addition, a plurality of dummy bumps 130d of the package sealing ring PSR are arranged apart along a plurality of edges of the device die 100a.

[0080] According to some embodiments, some of the dummy bumps 130d that extend along a single edge of the device die 100a are formed as a wall structure, which is shown as a plurality of line segments in the plan view of FIG. 1B Further, other portions of the dummy bumps 130d can extend along intersecting edges of the device die 100a, respectively, and are shown as a plurality of line segments in the plan view of FIG. 1BThe plurality of dummy bumps 130d on the bottom side and the top side of the package sealing ring PSR can have similar shapes in plan view. For example, the plurality of dummy conductive pads 112d, 128d on the bottom side and the top side of the plurality of dummy bumps 130d having segmented planar shapes can also be formed as line segments. As another example, the plurality of dummy conductive pads 112d, 128d on the bottom side and the top side of the plurality of dummy bumps 130d having "L" shaped planar shapes can also be formed as "L" shapes. On the other hand, the plurality of dummy substrate vias 114d of the package sealing ring PSR can not be formed according to the planar shapes of the dummy bumps 130d. For example, while the dummy bumps 130d are formed to have linear and "L" shaped planar shapes, the dummy substrate vias 114d can be formed as columnar structures having circular planar shapes. Further, the plurality of functional bumps 130f can be formed as columnar structures having circular planar shapes, respectively, as compared to the dummy bumps 130d having segmented or "L" shaped planar shapes.

[0081] As FIG. 1B Further shown, the die-to-die connections can be implemented at least in the plurality of regions 156 overlapping both of the device dies 100a, 100b. As described above, the device dies 100a, 100b can be connected to each other through the plurality of functional conductive pads 128f, 112f, the plurality of functional bumps 130f, and the plurality of functional substrate vias 114f, and these interconnection elements can be at least partially located in the plurality of regions 156.

[0082] Also as FIG. 1B shown, the connections between the device die 100b and the redistribution line structure 144 can be established in a region 158 overlapping a second portion of the device die 100b that is outside the range of the device die 100a. As described above, the connections between the device die 100b and the redistribution line structure 144 can be established through the redistribution line structure 122 and the plurality of encapsulant vias 152.

[0083] FIG. 1C is a magnified schematic cross-sectional view showing one of the plurality of dummy substrate vias 114d and surrounding features according to some embodiments of the present disclosure.

[0084] Referring to FIG. 1CSimilar to functional substrate vias 114f, dummy substrate vias 114d can extend through semiconductor substrate 102 of device die 100a. According to some embodiments, dummy substrate vias 114d and functional substrate vias 114f can also extend through multiple dielectric layers of multiple metallization layers 104 and land on some wiring elements 108 disposed in multiple dielectric layers 106. As described above, multiple dummy substrate vias 114d can be arranged in a peripheral region of device die 100a such that multiple functional substrate vias 114f can be laterally surrounded by multiple dummy substrate vias 114d. However, multiple dummy substrate vias 114d can still be laterally spaced apart from multiple edges of device die 100a. According to some embodiments, a die seal ring DSR can be configured between multiple dummy substrate vias 114d and multiple edges of device die 100a. In particular, a die seal ring DSR laterally surrounding multiple dummy substrate vias 114d can be formed through multiple dielectric layers of multiple metallization layers 104 and multiple dielectric layers 106 formed on multiple metallization layers 104 and can include multiple alternating layers of multiple conductive patterns and multiple conductive vias.

[0085] FIG. 2A to FIG. 2C FIG. 1 IB is a schematic cross-sectional view illustrating a process for bonding device die 100a with redistribution structure 122 according to some embodiments of the present disclosure.

[0086] Referring to FIG. 2A This process can start with forming multiple conductive pillars 132 and solder layer 134 on device die 100a and redistribution structure 122. In particular, one half of multiple conductive pillars 132 can be formed on device die 100a and the other half of multiple conductive pillars 132 can be formed on redistribution structure 122. In addition, solder layer 134 can be formed on multiple conductive pillars 132 standing on device die 100a or on multiple conductive pillars 132 standing on redistribution structure 122. For the purpose of illustration, this process will be described according to the example of forming multiple solder layers 134 on multiple conductive pillars 132 standing on device die 100a.

[0087] In particular, a seed layer (or more) is initially deposited on each of the device die 100a and the redistribution line structure 122. Subsequently, a mask layer (e.g., a photoresist layer) can be formed over each of the device die 100a and the redistribution line structure 122, and can be patterned to have openings that expose the underlying seed layer. Thereafter, one or a series of plating processes can be performed to deposit one or a stack of metal layers in each of the openings. Additionally, an additional plating process can be performed to provide a solder material on the plurality of metal layers over the device die 100a. The mask layer can then be removed, and portions of the plurality of seed layers that are not shielded by the plurality of metal layers can also be removed. The plurality of metal layers and the remaining portions of the plurality of seed layers form the plurality of conductive pillars 132, while the solder material forms the plurality of solder layers 134.

[0088] Referring to FIG. 2B The bonding layers 136, 138 are formed on the device die 100a and the redistribution line structure 122, respectively. According to some embodiments, the bonding layer 136 covering the device die 100a can be formed to be greater than the total thickness of the plurality of solder layers 134 and the plurality of conductive pillars 132 on the device die 100a, while the bonding layer 138 covering the redistribution line structure 122 can be formed to be less than the thickness of the plurality of conductive pillars 132 standing on the redistribution line structure 122. In these embodiments, the plurality of conductive pillars 132 and the plurality of solder layers 134 on the device die 100a can be recessed with respect to the bonding layer 136, while the plurality of conductive pillars 132 on the redistribution line structure 122 can be protruded with respect to the bonding layer 138.

[0089] Referring to FIG. 2C A bonding operation is performed to bond the bonding layers 136, 138 to each other, and to bond the plurality of conductive pillars 132 formed on the device die 100a through the plurality of solder layers 134 to the plurality of conductive pillars 132 formed on the redistribution line structure 122. In this way, the plurality of bumps 130 including the upper conductive pillars 132, the lower conductive pillars 132, and the solder layers 134 therebetween, respectively, are formed to have lateral confinement provided by the bonding layers 136, 138. Due to the confinement by the bonding layers 136, 138, the plurality of bumps 130 can be arranged in a fine pitch, while shorting caused by swelling during bonding can be effectively prevented. According to some embodiments, the bonding operation includes at least one thermal treatment.

[0090] FIG. 3A to FIG. 3H is a schematic cross-sectional view illustrating an overall process for forming the semiconductor package 10 according to some embodiments of the present disclosure.

[0091] Referring to FIG. 3AAfter front side processing, the device die 100a in wafer form is bonded to the support substrate 300 by the front side. The semiconductor substrate 102 of the device die 100a has not yet been thinned from the back side, or has not yet been thinned to the final thickness. As such, the plurality of substrate vias 114 are not exposed at the back side of the semiconductor substrate 102, but are embedded in the semiconductor substrate 102. Further, the liner 109 and the back side redistribution line structure 110 have not yet been formed.

[0092] Referring to FIG. 3B The semiconductor substrate 102 is then thinned from the back side to expose the plurality of substrate vias 114. Additionally, the device die 100a is back side processed such that the liner 109 and the back side redistribution line structure 110 are formed along the back side of the semiconductor substrate 100. Additionally, the plurality of conductive pillars 132 and the plurality of solder layers 134 are formed on the back side of the semiconductor substrate 100 along with the liner 109 and the back side redistribution line structure 110, as described with reference to FIG. 2A and FIG. 2B In the process described with reference to

[0093] Referring to FIG. 3C The device die 100a and the plurality of bonding components formed thereon (i.e., the bonding layer 136 and the plurality of conductive pillars 132 and the plurality of solder layers 134 enclosed by the bonding layer 136) are singulated while the device die 100b and the dummy die 154 (both in wafer form) supported by the carrier substrate 306 are encapsulated with the encapsulation 142. Additionally, the redistribution line structure 122 is formed along the front side of the device die 100b and the top side of the encapsulation 142 and the dummy die 154. Additionally, the other half of the plurality of conductive pillars 132 and the bonding layer 138 are formed on the redistribution line structure 122 in the process described with reference to FIG. 2A and FIG. 2B Further, the plurality of encapsulation vias 152 can be formed through the bonding layer 138 to make contact with the redistribution line structure 122.

[0094] Subsequently, in the process described with reference to FIG. 2C the structure on the tape 302 shown in FIG. 3B is flipped and attached to the structure shown in FIG. 3C As a result, the bonding layer 136, the bonding layer 138 are bonded to each other, and the plurality of bumps 130 are assembled while being enclosed by the bonding layer 136, the bonding layer 138, as shown in FIG. 3D

[0095] Referring to FIG. 3E ​In the next stage, the support substrate 300 is removed from the device die 100a, and an encapsulant 140 is formed on the bonding layer 138 to laterally encapsulate the device die 100a and the plurality of encapsulant vias 152. Alternatively, the encapsulant 140 can be formed first, and a grinding process can be performed to remove the support substrate 300 and to planarize the encapsulant 140.

[0096] Referring to FIG. 3F A redistribution line structure 144 is then formed on the exposed front side of the device die 100a and the top side of the encapsulant 140. Thereafter, the plurality of package I / Os 150 can be disposed on the redistribution line structure 144.

[0097] Referring to FIG. 3G The carrier substrate 306 is removed, and a grinding process can be performed to thin the exposed device die 100b, dummy die 154, and encapsulant 142. According to some embodiments, the plurality of package I / Os 150 are attached to another carrier substrate 308 when the carrier substrate 306 is separated from the encapsulant 142, device die 100b, and dummy die 154. An adhesive material 310 can be disposed between the redistribution line structure 144 and the carrier substrate 308 to enhance the adhesion of the existing package structure to the carrier substrate 308.

[0098] Referring to FIG. 3H When the thinning operation is completed, the resulting package structure can be flipped and attached to a tape 312 (supported by a frame 314) through the device die 100b, dummy die 154, and encapsulant 142, and the carrier substrate 308 and adhesive material 310 can be removed. Furthermore, the present package structure is singulated to form a semiconductor package 10 as described with reference to FIG. 1A to FIG. 1C

[0099] It should be appreciated that the semiconductor package 10 and its manufacturing method are provided as examples only. Many variations can be applied to the semiconductor package 10 and the related manufacturing process, and similar semiconductor packages and corresponding manufacturing processes can be obtained.

[0100] FIG. 4 is a schematic cross-sectional view showing a semiconductor package 40 according to some embodiments of the present disclosure.

[0101] The semiconductor package 40 is similar to the semiconductor package 10 described with reference to FIG. 1A to FIG. 1C ​The described semiconductor package 10 differs from the semiconductor package 10 described with reference to

[0102] Reference is made to FIG. 2A to FIG. 2C and FIG. 3A to FIG. 3H The described process can be used to form the semiconductor package 40, but with some modifications. Specifically, the joint layers 136, 138 should not be present in the stages shown in FIG. 2B , FIG. 2C , FIG. 3B , FIG. 3C and FIG. 3D After the plurality of upper conductive pillars 132, the plurality of lower conductive pillars 132 are joined by the plurality of solder layers 134 to form the plurality of bumps 130 at the stages shown in FIG. 2C and FIG. 3D A bottom underfill 400 can be disposed between the redistribution structure 122 and the device die 100a to laterally encapsulate the plurality of bumps 130 after the plurality of bumps 130 are formed. As shown in FIG. 4 The bottom underfill 400 can not completely cover the redistribution structure 122. Thus, the subsequently formed encapsulant 140 can be in contact with the redistribution structure 122 and laterally surround the bottom underfill 400.

[0103] The rest of the process of forming the semiconductor package 40 can be similar or even identical to the process described with reference to FIG. 2A to FIG. 2C and FIG. 3A to FIG. 3H and thus will not be repeated.

[0104] FIG. 5A to FIG. 5E are schematic plan views showing semiconductor packages 50a to semiconductor package 50e according to some embodiments of the present disclosure. Each of the semiconductor packages 50a to semiconductor package 50e is substantially identical to the semiconductor package 10 described with reference to FIG. 1A to FIG. 1C or the semiconductor package 40 described with reference to FIG. 4 It should be noted that only a few elements in each of the semiconductor packages 50a to semiconductor package 50e are shown for the purpose of illustration. The detailed structures of the rest of each of the semiconductor packages 50a to semiconductor package 50e can be referred to the description with reference to FIG. 1A to FIG. 1C .

[0105] As a difference from the semiconductor package 10 described with reference to FIG. 1A to FIG. 1C , FIG. 5AThe package seal ring PSR in the illustrated semiconductor package 50a includes a single dummy bump 130d1 formed as an annular wall and continuously extending along multiple edges of the device die 100a. In this way, multiple functional bumps 130f are laterally surrounded by the annular dummy bump 130d1 and can be more fully protected by the annular dummy bump 130d1. Although not illustrated, multiple dummy conductive pads 112d, 128d of the package seal ring PSR at the bottom and top sides of the annular dummy bump 130d1 have similar top-down shapes as the annular dummy bump 130d1 located therebetween. That is, the annular dummy bump 130d1 can be in contact with the annular dummy conductive pad 112d from above and can be in contact with the annular dummy conductive pad 128d from below. On the other hand, multiple dummy substrate vias 114d of the package seal ring PSR can not be formed according to the annular dummy bump 130d1. For example, when located below the annular dummy bump 130d1, the multiple dummy substrate vias 114d can be formed as a columnar structure having a circular top-down shape and are arranged apart along the annular dummy bump 130d1. Also, compared to the annular dummy bump 130d1, the multiple functional bumps 130f are formed as a columnar structure and can have a circular top-down shape.

[0106] Referring to FIG. 5B , the package seal ring PSR in the semiconductor package 50b can include multiple linear dummy bumps 130d2 and multiple segmented dummy bumps 130d3 instead of having a single annular dummy bump 130d1. The multiple linear dummy bumps 130d2 can each be formed as a wall structure that presents as a linear pattern in a top-down view and can continuously extend along the first and second edges of the device die 100a. On the other hand, the multiple segmented dummy bumps 130d3 are structurally identical to the multiple segmented dummy bumps 130d described with reference to FIG. 1A and FIG. 1B and can be arranged apart along the third and fourth edges of the device die 100a.

[0107] Although not shown, the plurality of dummy conductive pads 112d, 128d of the package sealing ring PSR at the bottom side and the top side of the plurality of dummy bumps 130d2, 130d3 can be formed according to the plurality of dummy bumps 130d2, 130d3. Specifically, the plurality of linear dummy bumps 130d2 can respectively contact the linear dummy conductive pads 112d from above and the linear dummy conductive pads 128d from below. In addition, the plurality of segmented dummy bumps 130d3 can be disposed between and connected to the plurality of segmented dummy conductive pads 112d and the plurality of segmented dummy conductive pads 128d. On the other hand, the plurality of dummy substrate vias 114d of the package sealing ring PSR can not be formed according to the dummy bumps 130d2, 130d3. For example, when located below the plurality of linear dummy bumps 130d2 and the plurality of segmented dummy bumps 130d3, the plurality of dummy substrate vias 114d can be formed as a columnar structure with a circular top view and disposed separately along the plurality of linear dummy bumps 130d2 and the plurality of segmented dummy bumps 130d3. Furthermore, the plurality of functional bumps 130f can be formed as a columnar structure and can have a circular top view shape compared to the plurality of linear dummy bumps 130d2 and the plurality of segmented dummy bumps 130d3.

[0108] In FIG. 5C In the semiconductor package 50c shown, the plurality of dummy bumps 130d4 of the package sealing ring PSR can be formed as a columnar structure with a circular top view shape, similar or identical to the plurality of functional bumps 130f. According to some embodiments, the plurality of dummy conductive pads 112d, 128d at the bottom side and the top side of the plurality of dummy bumps 130d4 are formed in a circular pattern, a segmented pattern, a linear pattern, or a combination thereof, and connected to the plurality of dummy bumps 130d4. In addition, similar to the plurality of dummy bumps 130d4 and the plurality of functional bumps 130f, the plurality of dummy substrate vias 114d can be formed as a columnar structure with a circular top view shape and disposed separately along the plurality of dummy bumps 130d4.

[0109] Referring to FIG. 5DThe package seal ring PSR in the semiconductor package 50d includes a plurality of dummy bumps 130d5 arranged along the edges of the device die 100a, and includes a plurality of dummy bumps 130d6 laterally surrounded by the plurality of segmented dummy bumps 130d5. That is, the plurality of dummy bumps 130d5 are arranged separately along an outer ring path proximate to the edges of the device die 100a, while the plurality of dummy bumps 130d6 are arranged separately along an inner ring path surrounded by the outer ring path. In addition, portions of the plurality of outer dummy bumps 130d5 extending along one edge of the device die 100a are each formed as a wall structure, which is shown as a plurality of line segments in a top view. Further, other portions of the plurality of outer dummy bumps 130d5 can each extend along intersecting edges of the device die 100a, and are each shown as a pattern having an "L" shape in a plan view. Similarly, some of the inner dummy bumps 130d6 extending along a single edge of the device die 100a are each formed as a wall structure, which is shown as a plurality of line segments in a plan view. Alternatively, other inner dummy bumps 130d6 can each extend along intersecting edges of the device die 100a, and are each shown as an "L" shaped pattern in a plan view.

[0110] Although not shown, dummy conductive pads 112d, 128d of the package seal ring PSR at the bottom and top sides of the plurality of dummy bumps 130d5, 130d6 can be formed according to the plurality of dummy bumps 130d5, 130d6. Specifically, the dummy conductive pads 112d located below the plurality of dummy bumps 130d5, 130d6 can be arranged separately along the outer ring path and the inner ring path, and the dummy conductive pads 128d located above the plurality of dummy bumps 130d5, 130d6 can also be arranged separately along the outer ring path and the inner ring path. Further, the plurality of segmented dummy bumps 130d5, 130d6 can each contact a plurality of segmented dummy conductive patterns 112d, 128d through the bottom and top sides, respectively, while the plurality of dummy bumps 130d5, 130d6 having an "L" shaped top view shape can each contact a plurality of dummy conductive patterns 112d, 128d having an "L" shaped top view shape through the bottom and top sides, respectively.

[0111] On the other hand, the plurality of dummy substrate vias 114d of the package seal ring PSR can not be formed according to the plurality of dummy bumps 130d5, 130d6. Specifically, the plurality of dummy substrate vias 114d can be formed as a columnar structure having a circular top view shape, and arranged separately along the plurality of outer dummy bumps 130d5 and the plurality of inner dummy bumps 130d6. Also, the plurality of functional bumps 130f can also be formed as a columnar structure having a circular top view shape.

[0112] Reference FIG. 5EThe package seal ring PSR in the semiconductor package 50e can include a plurality of dummy bumps in three tiers. Specifically, a plurality of outer dummy bumps 130d7 can be arranged apart along an outer ring path proximate to edges of the device die 100a; a plurality of first inner dummy bumps 130d8 can be arranged apart along a first inner ring path enclosed by the outer ring path; and a plurality of second inner dummy bumps 130d9 can be arranged apart along a second inner ring path enclosed by the first inner ring path. Similar to the dummy bumps 130d5, 130d6 described above, the plurality of outer dummy bumps 130d7 can include segmented dummy bumps 130d7 and dummy bumps 130d7 having an "L"-shaped top-down shape. Similarly, the plurality of first inner dummy bumps 130d8 can include segmented first dummy bumps 130d8 and can optionally include first dummy bumps 130d8 having an "L"-shaped top-down shape. Further, the plurality of second inner dummy bumps 130d9 can include segmented second dummy bumps 130d9 and can optionally include second dummy bumps 130d9 having an "L"-shaped top-down shape. FIG. 5D Similar to the dummy bumps 130d5, 130d6 described above, the plurality of outer dummy bumps 130d7 can include segmented dummy bumps 130d7 and dummy bumps 130d7 having an "L"-shaped top-down shape. Similarly, the plurality of first inner dummy bumps 130d8 can include segmented first dummy bumps 130d8 and can optionally include first dummy bumps 130d8 having an "L"-shaped top-down shape. Further, the plurality of second inner dummy bumps 130d9 can include segmented second dummy bumps 130d9 and can optionally include second dummy bumps 130d9 having an "L"-shaped top-down shape.

[0113] Although not shown, a plurality of dummy conductive pads 112d, 128d of the package seal ring PSR at the bottom side and the top side of the plurality of dummy bumps 130d7, 130d8, 130d9 can be formed according to the plurality of dummy bumps 130d7, 130d8, 130d9. Specifically, the plurality of dummy conductive pads 112d located below the plurality of dummy bumps 130d7, 130d8, 130d9 can be arranged apart along the outer ring path, the first inner ring path, and the second inner ring path. Similarly, the plurality of dummy conductive pads 128d above the plurality of dummy bumps 130d7, 130d8, 130d9 can also be arranged apart along the outer ring path, the first inner ring path, and the second inner ring path. Further, the segmented dummy bumps 130d7, 130d8, 130d9 can respectively contact segmented ones of the plurality of dummy conductive patterns 112d, 128d through the bottom side and the top side, while the dummy bumps 130d7, 130d8, 130d9 having an "L"-shaped top-down shape can respectively contact the plurality of dummy conductive patterns 112d, 128d having an "L"-shaped top-down shape through the bottom side and the top side.

[0114] On the other hand, the dummy substrate vias 114d of the package sealing ring PSR can not be formed with the dummy bumps 130d7, 130d8, 130d9. Specifically, the dummy substrate vias 114d can be formed as columnar structures with a circular top view shape and disposed apart along the outer dummy bumps 130d7, the first inner dummy bumps 130d8, and the second inner dummy bumps 130d9. Also, the functional bumps 130f can also be formed as columnar structures with a circular top view shape.

[0115] FIG. 6A is a schematic cross-sectional view showing a portion of the package sealing ring PSR in the semiconductor package 50d according to some embodiments of the present disclosure. FIG. 5D is a schematic cross-sectional view showing a portion of the package sealing ring PSR in the semiconductor package 50d according to some embodiments of the present disclosure.

[0116] Reference is made to FIG. 6A In some embodiments, the die sealing ring DSR of the device die 100a can extend between the inner dummy bumps 130d6 and the edges of the device die 100a while overlapping the outer dummy bumps 130d5. In these embodiments, the dummy substrate vias 114d located directly below the inner dummy bumps 130d6 can be disposed on the inner side of the die sealing ring DSR away from the edges of the device die 100a and can be laterally spaced apart from the die sealing ring DSR. On the other hand, the dummy substrate vias 114d located directly below the outer dummy bumps 130d5 can be inserted into the die sealing ring DSR and can be respectively surrounded by the die sealing ring DSR.

[0117] FIG. 6B is a schematic cross-sectional view showing a portion of the package sealing ring PSR in the semiconductor package 50d according to some other embodiments of the present disclosure. FIG. 5D is a schematic cross-sectional view showing a portion of the package sealing ring PSR in the semiconductor package 50d according to some other embodiments of the present disclosure.

[0118] Reference is made to FIG. 6B In some other embodiments, the die sealing ring DSR of the device die 100a overlaps the outer dummy bumps 130d5 and the inner dummy bumps 130d6. In these embodiments, the dummy substrate vias 114d located directly below the outer dummy bumps 130d5 and the dummy substrate vias 114d located directly below the inner dummy bumps 130d5 can both be inserted into the die sealing ring DSR and respectively surrounded by the die sealing ring DSR.

[0119] FIG. 6C is a schematic cross-sectional view showing a portion of the package sealing ring PSR in the semiconductor package 50d according to some other embodiments of the present disclosure. FIG. 5E is a schematic cross-sectional view showing a portion of the package sealing ring PSR in the semiconductor package 50d according to some other embodiments of the present disclosure.

[0120] refer to FIG. 6C According to some embodiments, the die sealing ring DSR of the device die 100a can extend between a plurality of second inner dummy bumps 130d9 and a plurality of edges of the device die 100a, while overlapping with a plurality of first inner dummy bumps 130d8 and a plurality of outer dummy bumps 130d7. In these embodiments, a plurality of dummy substrate vias 114d located directly below the plurality of second inner dummy bumps 130d9 can be disposed on the inner side of the die sealing ring DSR away from the plurality of edges of the device die 100a, and can be laterally spaced from the die sealing ring DSR. On the other hand, the plurality of dummy substrate vias 114d located directly below the plurality of first inner dummy bumps 130d8 and the plurality of dummy substrate vias 114d located directly below the plurality of outer dummy bumps 130d7 can both be inserted into the die sealing ring DSR and can be respectively surrounded by the die sealing ring DSR.

[0121] As described above, many variations can be applied to the package sealing ring PSR. In other embodiments, variations related to die arrangement and die stacking can be applied.

[0122] FIG. 7A This is a schematic cross-sectional view showing a semiconductor package 70 according to some embodiments of the present disclosure.

[0123] Apart from some differences, semiconductor package 70 and reference FIG. 1A to FIG. 1C The described semiconductor package 10 is similar. Specifically, in FIG. 7A In the semiconductor package 70 shown, device die 100b is aligned with device die 100a, rather than laterally offset from device die 100a. As a result, device die 100b can completely overlap with device die 100a. Since device die 100b may not have any portion outside the range of device die 100a, connections between device die 100b and the redistribution wiring structure 144 without passing through device die 100a may not be available, and therefore encapsulation vias for establishing such connections can be omitted. Furthermore, since device die 100b is aligned with device die 100a, it is not necessary to place a dummy die next to device die 100b to balance the non-uniformity of the coefficient of thermal expansion on the encapsulation 142.

[0124] The manufacturing process used to form the semiconductor package 70 is similar to the reference. FIG. 2A to FIG. 2C and FIG. 3A to FIG. 3H The described process can omit the placement of the dummy die 154, skip the formation of the encapsulation through-hole 152, and the position of the device die 100b must be adjusted. For the sake of brevity, the entire process may not be repeated.

[0125] FIG. 7BThis is a schematic plan view of a semiconductor package 70 according to some embodiments of this disclosure. It should be noted that, for illustrative purposes, FIG. 7B Only a few components in semiconductor package 70 are shown in the image.

[0126] like FIG. 7B As shown, device die 100b can completely overlap with device die 100a. According to some embodiments, the size of device die 100b is smaller than the size of device die 100a. In these embodiments, a package seal ring PSR (only the plurality of dummy bumps 130d of the package seal ring PSR are shown) configured along multiple edges of device die 100a can be located outside the extent of device die 100b. That is, the package seal ring PSR can extend between multiple edges of device die 100a and multiple edges of device die 100b, and device die 100b can be laterally surrounded by the package seal ring PSR.

[0127] Furthermore, since device die 100b can completely overlap with device die 100a, multiple functional conductive pads 128f, multiple functional bumps 130f, and multiple functional conductive pads 112f within the range of device die 100b can all be used to establish communication between device dies 100a and 100b. Additionally, since there may be no encapsulation via, there may be no reference via. FIG. 1B The described encapsulation via region 158.

[0128] It should be noted that, for reference FIG. 1B and FIG. 5A to FIG. 5E The various designs of the described package sealing ring PSR can be applied to semiconductor package 70. Additionally, refer to... FIG. 1C and FIG. 6A to FIG. 6C The described configurations of the package sealing ring PSR and die sealing ring DSR can also be applied to the semiconductor package 70. Furthermore, although the plurality of bumps 130 in the semiconductor package 70 are depicted as being laterally confined by bonding layers 136, 138, the plurality of bumps 130 may optionally be defined by a reference layer. FIG. 4 The described bottom filler 400 seals the surface and can modify the manufacturing process used to form the semiconductor package 70.

[0129] FIG. 8 This is a schematic cross-sectional view showing a semiconductor package 80 according to some embodiments of the present disclosure.

[0130] Semiconductor package 80 is similar to reference FIG. 7A and FIG. 7BThe semiconductor package 70 is described. The main difference between semiconductor package 70 and semiconductor package 80 is that device dies 100a and 100b in semiconductor package 70 are arranged in a back-to-back die stack configuration, while device dies 100a and 100b in semiconductor package 80 are arranged in a face-to-face die stack configuration.

[0131] Specifically, such as FIG. 8 As shown, a plurality of metallization layers 104, a plurality of dielectric layers 106, and a plurality of wiring elements 108 formed on the active side of device die 100a face a plurality of metallization layers 116, a plurality of dielectric layers 118, and a plurality of wiring elements 120 formed on the active side of device die 100b. According to some embodiments, reference is made to... FIG. 1A , FIG. 4 The redistribution structure 122 described in Figure 7 is absent in the semiconductor package 80, and multiple bumps 130 between device dies 100a and 100b connect the active side of device dies 100a to the active side of device dies 100b. Additionally, bonding layer 136 may extend along the active side of device dies 100a, and bonding layer 138 may extend along the active side of device dies 100b. On the other hand, the back-side redistribution structure 110 at the back side of device dies 100a may also contact the redistribution structure 144.

[0132] Based on this face-to-face die stacking method, multiple dummy bumps 130d can be connected to multiple dummy substrate vias 114f through some wiring elements 108 and some conductive components in multiple metallization layers 104 on the active side of the device die 100a. These wiring elements 108 connected to the dummy bumps 130d can be referred to as dummy wiring elements 108d. Similarly, the multiple conductive components in the multiple metallization layers 104 and connected to the multiple dummy bumps 130d can be referred to as dummy conductive components 104d. That is, the package sealing ring PSR in the semiconductor package 80 can include not only multiple dummy bumps 130d, multiple dummy substrate vias 114d, and multiple dummy conductive pads 112d, but also multiple dummy wiring elements 108d and multiple dummy conductive components 104d. Furthermore, due to the reference... FIG. 1A , FIG. 4 The redistribution structure 122 described in Figure 7 may not exist in the semiconductor package 80, so the package sealing ring PSR in the semiconductor package 80 may not include the dummy conductive pad 128d in the redistribution structure 122.

[0133] In some embodiments, while the device die 100b and the bonding layer 138 extending along the active side of the device die 100b are laterally encapsulated by the encapsulant 142, the device die 100a and the bonding layer 136 can not be encapsulated. In these embodiments, singulation of the semiconductor package 80 can be performed by cutting through the encapsulant 142, the bonding layer 136, the device die 100a, and the redistribution line structure 144. As such, the device die 100a, the bonding layer 136, and the redistribution line structure 144 can extend to multiple sidewalls of the semiconductor package 80, and the sidewalls of the encapsulant 142, the sidewalls of the bonding layer 136, the sidewalls of the device die 100a, and the sidewalls of the redistribution line structure 144 can be substantially coplanar. Further, the sidewalls of the device die 100b and the sidewalls of the bonding layer 138 can be laterally recessed from the sidewalls of the bonding layer 136, the sidewalls of the device die 100a, and the sidewalls of the redistribution line structure 144. To establish contact with the active side of the device die 100b, a plurality of dummy bumps 130d of the package seal ring PSR can be formed at the inside of a plurality of edges of the device die 100b. On the other hand, the rest of the package seal ring PSR can be located within the bounds of the device die 100b or across the plurality of edges of the device die 100b while being located within the bounds of the device die 100a.

[0134] FIG. 9A to FIG. 9D FIG. 1 is a schematic cross-sectional view illustrating a process for forming a semiconductor package 80 according to some embodiments of the present disclosure.

[0135] Reference is made to FIG. 9A After the front side processing, the device die 100a in wafer form is subjected to a process similar to the process described with reference to FIG. 2A and FIG. 2B to form the lower conductive pillars 132 of the plurality of bumps 130 and the bonding layer 136 on the active side of the device die 100a. At this point, the semiconductor substrate 102 of the device die 100a has not yet been thinned from the back side, or has not yet been thinned to the final thickness. As such, the plurality of substrate vias 114 are not exposed at the back side of the semiconductor substrate 102, but are embedded in the semiconductor substrate 102. Further, the liner 109 and the back side redistribution line structure 110 have not yet been formed.

[0136] Reference is made to FIG. 9B Similar to the device die 100a, the device die 100b in wafer form is subjected to front side processing and formation of the upper conductive pillars 132 of the plurality of bumps 130 and the solder layer 134 and the bonding layer 138 on the active side of the device die 100b. Thereafter, the device die 100b can be singulated along with the bonding layer 138.

[0137] Subsequently, the FIG. 2C are subjected to a process similar to the process described with reference to FIG. 9BThe structure shown is flipped and attached to FIG. 9A The structure shown. The result is as follows. FIG. 9C As shown, bonding layers 136 and 138 are bonded to each other, and a plurality of bumps 130 are assembled and simultaneously surrounded by bonding layers 136 and 138. Further as... FIG. 9C As shown, after the bonding process, the device die 100b and the bonding layer 138 can be encapsulated by the encapsulant 142.

[0138] refer to FIG. 9D The current package structure can then be flipped and attached to the carrier substrate 900. When the back side of the semiconductor substrate 102 is exposed, a polishing process can be performed to thin the semiconductor substrate 102 until multiple substrate vias 114 are exposed.

[0139] refer to FIG. 9E Subsequently, a liner 109 and a backside redistribution structure 110 are formed on the back side of the device die 100b. Furthermore, a redistribution structure 144 can be formed on the backside redistribution structure 110 of the device die 100b. Additionally, multiple package I / Os 150 can be deployed on the redistribution structure 144.

[0140] Subsequently, the current package structure can be separated from the carrier substrate 900 and monolithized while being mounted on a dicing frame (not shown) to form a semiconductor package 80. Optionally, the semiconductor substrate 115 and encapsulation 142 of the device die 100b can be further thinned before monolithization.

[0141] It should be noted that, for reference FIG. 1B and FIG. 5A to FIG. 5E The various designs of the described package sealing ring PSR can be applied to semiconductor packages 80. Additionally, refer to... FIG. 1C and FIG. 6A to FIG. 6C The several configurations of the package sealing ring PSR and die sealing ring DSR described can also be applied to the semiconductor package 80. Furthermore, although the plurality of bumps 130 in the semiconductor package 80 are depicted as being laterally confined by bonding layers 136 and 138, the plurality of bumps 130 may optionally be defined by a reference... FIG. 4 The described bottom filler 400 seals the surface and can modify the manufacturing process used to form the semiconductor package 80. Therefore...

[0142] As described above, the present application provides a three-dimensional semiconductor package and a method of manufacturing the same. A plurality of device dies are stacked in the three-dimensional semiconductor package and are connected to each other through a plurality of bumps disposed between the plurality of device dies. To prevent the functional bumps from being damaged by stress and the invasion of moisture and / or chemicals, a package seal ring is provided around the functional bumps. Specifically, the package seal ring includes a plurality of dummy bumps that are identical in structure to the functional bumps but can not participate in signal transmission. The plurality of dummy bumps can be arranged separately along the edges of the bottom device die or be combined into a ring structure. In either way, the plurality of dummy bumps laterally surround the plurality of functional bumps and protect the plurality of functional bumps from damage caused by stress, moisture and / or chemicals. According to some embodiments, the package seal ring further includes a plurality of dummy substrate vias formed in the bottom device die. The plurality of dummy substrate vias are connected to the plurality of dummy bumps and laterally surround a plurality of functional substrate vias in the bottom device die that facilitate signal transmission. In this way, the functional substrate vias can also be protected by the package seal ring. In addition, in embodiments where the dummy bumps are disposed between vertically separated redistribution line structures, the package seal ring can further include a plurality of dummy conductive pads in the redistribution line structures that are in contact with the plurality of dummy bumps. In these embodiments, the plurality of dummy conductive pads can protect the surrounding conductive pads from possible damage. Thus, according to various embodiments, a semiconductor package with improved reliability can be obtained by further incorporating a package seal ring.

[0143] Other features and processes can also be included. For example, test structures can be included to assist in verifying testing of the 3D package or 3DIC device. The test structures can include, for example, test pads formed on the redistribution layer or substrate that allow for the use of probes and / or probe cards in testing the 3D package or 3DIC, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with testing methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0144] In one aspect of the present disclosure, a semiconductor package is provided. The semiconductor package includes a first device die and a second device die stacked on the first device die; a plurality of functional bumps disposed between the first device die and the second device die and electrically connected to the first device die and the second device die. A first encapsulation ring includes at least one dummy bump disposed along a plurality of edges of the first device die and arranged between the first and second device dies and laterally surrounding the plurality of functional bumps. In some embodiments, the at least one dummy bump is structurally identical to the plurality of functional bumps. In some embodiments, the at least one dummy bump includes a plurality of dummy bumps separately disposed along the plurality of edges of the first device die. In some embodiments, the at least one dummy bump includes a plurality of first segmented dummy bumps and a plurality of second segmented dummy bumps, each of the plurality of first segmented dummy bumps extending along a single one of the plurality of edges of the first device die, and the plurality of second segmented dummy bumps extending along intersecting edges of the plurality of edges of the first device die. In some embodiments, the at least one dummy bump includes a plurality of segmented dummy bumps and a plurality of linear dummy bumps, the plurality of segmented dummy bumps separately disposed along each of a first edge and a second edge of the plurality of edges of the first device die, and the plurality of linear dummy bumps continuously extending along a third edge and a fourth edge of the plurality of edges of the first device die, respectively. In some embodiments, the at least one dummy bump includes an annular dummy bump continuously extending along the plurality of edges of the first device die. In some embodiments, the at least one dummy bump includes a plurality of outer dummy bumps and a plurality of inner dummy bumps, the plurality of outer dummy bumps separately disposed along an outer ring path proximate to the plurality of edges of the first device die, and the plurality of inner dummy bumps separately disposed along an inner ring path laterally surrounded by the outer ring path. In some embodiments, the at least one dummy bump includes a plurality of outer dummy bumps, a plurality of first inner dummy bumps, and a plurality of second inner dummy bumps, the plurality of outer dummy bumps separately disposed along an outer ring path proximate to the plurality of edges of the first device die, the plurality of first inner dummy bumps separately disposed along a first inner ring path laterally surrounded by the outer ring path, and the plurality of second inner dummy bumps separately disposed along a second inner ring path laterally surrounded by the first inner ring path. In some embodiments, the first encapsulation ring further includes a plurality of dummy substrate vias formed to the first device die and in contact with the at least one dummy bump. In some embodiments, the plurality of dummy substrate vias are laterally surrounded by a second encapsulation ring in the first device die.In some embodiments, a first set of the plurality of dummy substrate vias is inserted into a second sealing ring of the first device die, and a second set of the plurality of dummy substrate vias is laterally surrounded by the second sealing ring.

[0145] In another aspect of the present disclosure, a semiconductor package is provided. The semiconductor package includes a first device die and a second device die overlapping the first device die; a plurality of functional bumps disposed between the first device die and the second device die and electrically connected to the first device die and the second device die. A first sealing ring includes at least one first sealing ring laterally surrounding the plurality of functional bumps between the first and second device dies; a first bonding layer disposed between the first device die and the second device die and extending along a side of the first device die facing the second device die. A second bonding layer disposed between the first bonding layer and the second device die and bonded to the first bonding layer, wherein the plurality of functional bumps and at least one dummy bump extend through the first and second bonding layers. In some embodiments, a plurality of sidewalls of the first bonding layer are substantially coplanar with a plurality of sidewalls of the first device die. In some embodiments, the semiconductor package further includes a redistribution structure between the second bonding layer and the second device die, wherein the second bonding layer is formed along the redistribution structure and has a plurality of sidewalls substantially coplanar with a plurality of sidewalls of the redistribution structure. In some embodiments, the first sealing ring further includes a plurality of dummy conductive pads formed in the redistribution structure and in contact with the plurality of dummy bumps. In some embodiments, the second bonding layer extends along a side of the second device die facing the first device die and has a plurality of sidewalls substantially coplanar with a plurality of sidewalls of the second device die.

[0146] In another aspect of the disclosure, a method for manufacturing a semiconductor package is provided. The method includes forming a plurality of functional bumps to establish a vertical signal transmission path between a first device die and a second device die stacked on the first device die; forming a first seal ring along a plurality of edges of the first device die, including forming at least one dummy bump laterally surrounding the plurality of functional bumps between the first and second device dies. In some embodiments, forming the first seal ring further includes forming a plurality of dummy substrate vias into the first device die, and the at least one dummy bump overlaps and connects with the plurality of dummy substrate vias. In some embodiments, forming the first seal ring further includes forming a plurality of dummy conductive pads in a redistribution layer structure between a second bonding layer and the second device die, and the plurality of dummy conductive pads overlaps and connects with the plurality of dummy bumps. In some embodiments, the method of manufacturing the semiconductor package further includes forming a first bonding layer and a second bonding layer during forming the plurality of functional bumps and the at least one dummy bump, wherein the first bonding layer and the second bonding layer are bonded to each other and laterally surround the plurality of functional bumps and the at least one dummy bump.

[0147] The foregoing has outlined rather generally the features of several embodiments in order that the detailed description that follows can be better understood. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize the equivalents of the various elements described herein and, of course, they can readily apply the equivalents to other processes and structures without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, characterized in that, include: A first device die and a second device die stacked on top of the first device die; Multiple functional bumps are disposed between the first device die and the second device die, and are electrically connected to the first device die and the second device die; as well as The first sealing ring includes a plurality of edges arranged along the first device die and disposed between the first device die and the second device die, and at least one dummy bump that is laterally surrounding the plurality of functional bumps.

2. The semiconductor package according to claim 1, characterized in that, The at least one dummy bump is structurally identical to the plurality of functional bumps.

3. The semiconductor package according to claim 1, characterized in that, The at least one dummy bump includes a plurality of first segment dummy bumps and a plurality of second segment dummy bumps arranged separately along the plurality of edges of the first device die, each of the plurality of first segment dummy bumps extending along a single one of the plurality of edges of the first device die, and the plurality of second segment dummy bumps extending along a plurality of intersecting edges of the plurality of edges of the first device die.

4. The semiconductor package according to claim 1, characterized in that, The at least one dummy bump includes a plurality of segmented dummy bumps and a plurality of linear dummy bumps, the plurality of segmented dummy bumps being separately arranged along each of the first edge and the second edge of the plurality of edges of the first device die, and the plurality of linear dummy bumps extending continuously along the third edge and the fourth edge of the plurality of edges of the first device die, respectively.

5. The semiconductor package according to claim 1, characterized in that, The at least one dummy bump includes an annular dummy bump that extends continuously along the plurality of edges of the first device die.

6. The semiconductor package according to claim 1, characterized in that, The at least one dummy bump includes a plurality of outer dummy bumps and a plurality of inner dummy bumps. The plurality of outer dummy bumps are arranged separately along an outer ring path close to the plurality of edges of the first device die, and the plurality of inner dummy bumps are arranged separately along an inner ring path that is laterally surrounded by the outer ring path.

7. The semiconductor package according to claim 1, characterized in that, The first sealing ring further includes a plurality of dummy substrate vias formed to the first device die and in contact with the at least one dummy bump.

8. A semiconductor package, characterized in that, include: A first device die and a second device die that overlaps with the first device die; Multiple functional bumps are disposed between the first device die and the second device die, and are electrically connected to the first device die and the second device die; The first sealing ring includes at least one dummy bump that laterally surrounds the plurality of functional bumps between the first device die and the second device die; A first bonding layer is disposed between the first device die and the second device die, and extends along the side of the first device die toward the second device die; as well as A second bonding layer is disposed between the first bonding layer and the second device die and is bonded to the first bonding layer. The plurality of functional bumps and the at least one dummy bump extend through the first bonding layer and the second bonding layer.

9. The semiconductor package according to claim 8, characterized in that, It also includes a redistribution structure located between the second bonding layer and the second device die, wherein the second bonding layer is formed along the redistribution structure and has a plurality of sidewalls substantially coplanar with the plurality of sidewalls of the redistribution structure.

10. The semiconductor package according to claim 8, characterized in that, The second bonding layer extends along the side of the second device die facing the first device die and has a plurality of sidewalls substantially coplanar with a plurality of sidewalls of the second device die.

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