Clock source providing circuit of intelligent driving assistance system

Abstract

The utility model provides a clock source providing circuit of an intelligent driving assistance system. The first chip is used for providing a first clock signal; a second chip; the D flip-flop comprises a data input end D, a clock end CP, an output end Q and a reverse output end, the data input end D is connected with the reverse output end, the output end Q is connected with the second chip, the clock end CP receives a first clock signal output by the first chip, the D flip-flop is used for carrying out frequency division by two on the first clock signal, and the output end Q is connected with the reverse output end. And the second clock signal is output to a second chip through the output end Q. Compared with the prior art, the clock signal output by the MCU is subjected to two-frequency division processing by adopting the D trigger, and the clock signal after frequency division is provided for the intelligent driving auxiliary chip, so that the clock signal meeting the requirement can be provided for the intelligent driving auxiliary chip, and the cost can be saved.

Description

TECHNICAL FIELD

[0001] The utility model relates to clock source provides technical field, especially in an intelligent driving auxiliary system (that is ADAS) clock source provides circuit. BACKGROUND

[0002] S32G is the MCU chip of NXP enzhi pico company, and J5 (Horizon Robotics Journey 5.0) is Horizon J5 auxiliary driving chip. Horizon J5 platform is generally used with enzhi pico S32G, but, the existing vehicle of J5+S32G platform has the following problems:

[0003] 1, J5 chip must output accurate clock signal for camera frame synchronization, simultaneously, J5 chip needs external input accurate clock signal, and the requirement is 0.5Hz;

[0004] 2, the PWM (Pulse width modulation, namely pulse width modulation) output module function of S32G matched with J5 chip is single, and the minimum clock signal can only be output 1Hz, cannot output 0.5Hz clock signal to J5 for frame synchronization;

[0005] 3, need external increase an MCU output 0.5HZ clock signal to J5 chip, and cost increases;

[0006] 4, do not output accurate 0.5Hz clock signal to J5 chip, and frame rate is not synchronous, and picture is split.

[0007] Therefore, it is necessary to provide a new technical scheme to solve the above problems. CONTENT OF UTILITY MODEL

[0008] One of the purposes of the utility model is to provide a clock source providing circuit of intelligent driving auxiliary system, it adopts D trigger to carry out 2 frequency division processing to the clock signal of MCU output, and provides the clock signal after frequency division to intelligent driving auxiliary chip, to not only can provide the clock signal satisfying the requirement to intelligent driving auxiliary chip, and can save the cost.

[0009] According to one aspect of the utility model, the utility model provides a clock source providing circuit of intelligent driving auxiliary system, it includes;First chip, it is used to provide first clock signal;Second chip;D trigger, it includes data input end D, clock end CP, output end Q and reverse output end The data input end D is with the reverse output end The output end Q is connected with the second chip, the clock end CP receives the first clock signal output by the first chip, the D flip-flop is used for 2 frequency division of the first clock signal to generate a second clock signal, and the second clock signal is output to the second chip through the output end Q.

[0010] Further, the clock source providing circuit of the intelligent driving assistance system further comprises a level conversion circuit, an input end of the level conversion circuit is connected with the output end Q of the D flip-flop, and an output end of the level conversion circuit is connected with the second chip; the level conversion circuit is used for switching the second clock signal from a first voltage domain to a second voltage domain to generate and output a third clock signal to the second chip, wherein the first voltage domain is higher than the second voltage domain.

[0011] Further, the first chip is an MCU chip, and the second chip is an auxiliary driving chip.

[0012] Further, the first chip is an S32G, and the second chip is a Horizon J5.

[0013] Further, the first voltage domain is 3.3V, and the second voltage domain is 1.8V.

[0014] Further, the frequency of the first clock signal is 1Hz, and the frequencies of the second clock signal and the third clock signal are 0.5Hz.

[0015] Further, the D flip-flop further comprises a reset end R, a set end S and a power supply end VCC, and the reset end R and the set end S are connected with the power supply end VCC.

[0016] Compared with the prior art, the D flip-flop is used for 2 frequency division processing of the clock signal output by the MCU, and the frequency-division clock signal is provided to the intelligent driving assistance chip, so that the intelligent driving assistance chip can not only be provided with a clock signal meeting the requirements, but also cost can be saved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical scheme of the embodiments of the utility model, the following will briefly introduce the drawings needed to be used in the embodiment description, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained according to these drawings without paying creative labor, wherein:

[0018] Figure 1 It is the circuit schematic diagram of the clock source providing circuit of the intelligent driving assistance system (namely ADAS) in an embodiment of the utility model;

[0019] Figure 2 For example, in one embodiment of this utility model Figure 1 The waveforms of the first clock signal at the clock terminal CP and the second clock signal at the output terminal Q of the D flip-flop are shown.

Detailed Implementation Methods

[0020] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments. Unless otherwise specified, the terms coupling, connection, linking, and interconnection used herein to indicate electrical connection mean direct or indirect connection. For example, A being connected to B includes both a direct electrical connection between A and B and a connection between A and B via electrical components or circuits.

[0022] In the description of this utility model, it should be understood that the terms "upper", "lower", "front", "back", "positive", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0023] Please refer to Figure 1 The diagram shown is a circuit diagram of the clock source supply circuit for an intelligent driving assistance system (i.e., ADAS) in one embodiment of the present invention. Figure 1 The clock source circuit of the intelligent driving assistance system shown includes a first chip 110, a second chip 120, and a D flip-flop 130.

[0024] The first chip 110 is used to provide the first clock signal. The D flip-flop 130 (e.g., 74LVC1G74DP) includes a data input terminal D, a clock terminal CP, an output terminal Q, and an inverting output terminal. Data input terminal D and inverting output terminal The output terminal Q is connected to the second chip 120. The clock terminal CP receives the first clock signal output by the first chip 110. The D flip-flop 130 is used to divide the first clock signal by 2 to generate the second clock signal. The second clock signal is output to the second chip 120 through the output terminal Q.

[0025] The D flip-flop 130 controls the storage and output of data through a clock signal, has two stable states (0 and 1), please refer to Figure 2 As shown in the embodiment of the utility model Figure 1 The waveform diagram of the first clock signal of the clock end CP of the D flip-flop and the second clock signal of the output end Q is shown.

[0026] Figure 1 The clock source providing circuit of the intelligent driving assistance system further comprises a level conversion circuit 140 (for example, SN74LVC1T45QDCKQQ1), an input end of the level conversion circuit 140 is connected with the output end Q of the D flip-flop 130, and an output end of the level conversion circuit 140 is connected with the second chip 120; the level conversion circuit 140 is used for switching the second clock signal output by the D flip-flop 130 from a first voltage domain to a second voltage domain, so as to generate and output a third clock signal to the second chip 120, wherein the first voltage domain is higher than the second voltage domain.

[0027] In Figure 1 In the specific embodiment shown, the first chip 110 is an MCU chip, specifically, the first chip 110 is S32G, and S32G is an MCU chip of NXP Enzhai company; the second chip 120 is an auxiliary driving chip, specifically, the second chip 120 is J5 (Horizon Robotics Journey 5.0), that is, Horizon J5 auxiliary driving chip.

[0028] In Figure 1 In the specific embodiment shown, the first voltage domain is 3.3V, and the second voltage domain is 1.8V; the frequency of the first clock signal is 1Hz, and the frequencies of the second clock signal and the third clock signal are 0.5Hz.

[0029] In Figure 1 In the specific embodiment shown, the D flip-flop 130 further comprises a reset end R, a set end S and a power supply end VCC, wherein the reset end R and the set end S are both connected with the power supply end VCC.

[0030] In summary, the clock source providing circuit of the intelligent driving assistance system provided by the utility model adds the D flip-flop 130 and the level conversion circuit 140 between S32G and Horizon J5 auxiliary driving chip, so that

[0031] The 1Hz minimum clock signal (namely the first clock signal) output by the PWM output module of S32G is 2-divided by the D flip-flop 130 to generate a 0.5Hz second clock signal for the J5 chip; if the voltage domain of the 0.5Hz second clock signal is inconsistent with the voltage domain of the 0.5Hz clock signal required by the J5 chip, the 0.5Hz second clock signal can also be switched from the first voltage domain to the second voltage domain by the level conversion circuit 140 to output a 0.5Hz third clock signal, so that the voltage domain of the 0.5Hz third clock signal is consistent with the voltage domain of the 0.5Hz clock signal required by the J5 chip. In this way, the utility model not only can provide the clock signal required by the J5 horizon auxiliary driving chip, but also can save the cost.

[0032] It should be noted that any modification made by the person skilled in the art to the specific embodiments of the utility model does not deviate from the scope of the claims of the utility model. Accordingly, the scope of the claims of the utility model is not limited to the foregoing specific embodiments.

Claims

1. A clock source providing circuit for an intelligent driving assistance system, characterized in that, It includes; The first chip is used to provide the first clock signal; Second chip; A D flip-flop includes a data input terminal D, a clock terminal CP, an output terminal Q, and an inverting output terminal. The data input terminal D and the inverting output terminal The output terminal Q is connected to the second chip, the clock terminal CP receives the first clock signal output by the first chip, the D flip-flop is used to divide the first clock signal by 2 to generate a second clock signal, and the second clock signal is output to the second chip through the output terminal Q.

2. The clock source supply circuit for the intelligent driving assistance system according to claim 1, characterized in that, It also includes; Level conversion circuit, The input terminal of the level conversion circuit is connected to the output terminal Q of the D flip-flop, and its output terminal is connected to the second chip. The level conversion circuit is used to switch the second clock signal from the first voltage domain to the second voltage domain, so as to generate and output a third clock signal to the second chip. The first voltage domain is higher than the second voltage domain.

3. The clock source supply circuit for the intelligent driving assistance system according to claim 2, characterized in that, The first chip is an MCU chip; The second chip is a driver assistance chip.

4. The clock source supply circuit for the intelligent driving assistance system according to claim 3, characterized in that, The first chip is an S32G; The second chip is the Horizon J5.

5. The clock source supply circuit for the intelligent driving assistance system according to claim 4, characterized in that, The first voltage domain is 3.3V; The second voltage domain is 1.8V.

6. The clock source supply circuit for the intelligent driving assistance system according to claim 4, characterized in that, The frequency of the first clock signal is 1Hz; The frequencies of the second and third clock signals are 0.5 Hz.

7. The clock source supply circuit for the intelligent driving assistance system according to claim 1, characterized in that, The D flip-flop also includes a reset terminal R, a set terminal S, and a power supply terminal VCC. Both the reset terminal R and the set terminal S are connected to the power supply terminal VCC.

Images