Mode conversion broadband rollback enhancement amplifying circuit and amplifier

Abstract

The utility model provides a mode conversion broadband rollback enhancement amplification circuit and an amplifier. The mode conversion broadband rollback enhancement amplification circuit comprises a power divider, a main power amplifier input matching network, a main transistor, a main bonding wire, an auxiliary power amplifier input matching network, an auxiliary transistor, an auxiliary bonding wire, an output matching network and a rear matching network, wherein the drain electrode of the auxiliary transistor is connected with the first end of the auxiliary bonding wire, and the source electrode of the auxiliary transistor is grounded; the second end of the auxiliary bonding wire is connected with the second end of the output matching network, and the third end of the auxiliary bonding wire is connected with the rear matching network; the auxiliary transistor has a double-bonding-wire structure, and the influence of parasitic inductance of the bonding wires on a circuit is reduced, so that the drain electrode phase of the auxiliary transistor is closer to an expected characteristic, and better power amplification performance is realized.

Description

TECHNICAL FIELD

[0001] The utility model relates to microwave power amplifier technical field especially relates to a mode conversion wideband backoff enhancement amplification circuit and amplifier. BACKGROUND

[0002] In the current microwave power amplifier circuit design, Doherty amplifier as the commonly used backoff efficiency enhancement technology, it has excellent backoff efficiency, but due to the limitation of 1 / 4 wavelength transmission line, the overall bandwidth is narrow. Switchless class G (SLCG) amplifier is a new type of backoff efficiency enhancement technology, which realizes wider bandwidth through two-quadrant modulation, but the existing SLCG technology needs to realize the two-quadrant modulation process through the matching network, and the phase shift caused by the auxiliary road matching element will cause the increase of the auxiliary transistor voltage at the edge frequency point, thereby causing the decline of the power amplifier performance at the edge frequency point. The new wideband backoff enhancement amplifier with Doherty-SLCG mode conversion only retains the SLCG circuit structure of the main road matching network, realizes two-quadrant elimination, and avoids the negative impact of auxiliary road phase shift on output power. The matching network is equivalent to SLCG circuit when the phase shift is 0 degree, and is equivalent to Doherty amplifier circuit when the phase shift is 90 degrees. When the phase shift of the main road matching network gradually transitions from 0 degree to 90 degrees, the circuit can gradually transition from SLCG mode to Doherty mode. This also makes the circuit can maintain high backoff efficiency in wider band.

[0003] However, in actual design, the bonding wire connected from the transistor to the external circuit in the wideband backoff enhancement amplifier with Doherty-SLCG mode conversion has a non-negligible parasitic inductance, which causes the phase of the auxiliary transistor internal drain node to deviate from the phase of the combining point. The phase change causes the internal voltage of the auxiliary road transistor to rise, causing the amplification circuit to enter the saturation state in advance, causing the phase of the main road signal and the auxiliary road signal at the output end of the amplifier to be not completely consistent when synthesized, and further reducing the output power. The amplifier works away from the theoretical wideband high backoff performance.

[0004] Therefore, the prior art still needs to be improved and developed. UTILITY MODEL CONTENT

[0005] In view of the above shortcomings of the prior art, the purpose of the utility model is to provide a mode conversion wideband backoff enhancement amplification circuit and amplifier to solve the problem of parasitic inductance of the bonding wire of the new wideband backoff enhancement amplifier with Doherty-SLCG mode conversion causing phase shift and affecting circuit performance.

[0006] The technical scheme of the utility model is as follows:

[0007] A mode conversion broadband backoff enhancement amplification circuit, comprising: a power divider, a main power amplifier input matching network, a main transistor, a main bonding line, an auxiliary power amplifier input matching network, an auxiliary transistor, an auxiliary bonding line, an output matching network, and a post matching network; wherein,

[0008] The input end of the power divider is connected with a radio frequency signal input end, the first output end of the power divider is connected with the input end of the main power amplifier input matching network, and the second output end of the power divider is connected with the input end of the auxiliary power amplifier input matching network, so as to perform power distribution on a radio frequency input signal.

[0009] The output end of the main power amplifier input matching network is connected with the gate of the main transistor, so as to match the port output impedance of the main power amplifier input matching network to the source impedance of the main transistor and absorb the parasitic capacitance in the main transistor.

[0010] The drain of the main transistor is connected with one end of the main bonding line, and the drain of the main transistor is grounded; the other end of the main bonding line is connected with the first end of the output matching network.

[0011] The output end of the delay network is connected with the input end of the auxiliary power amplifier input matching network, so as to eliminate the phase difference between the signal at the input end of the auxiliary input matching network and the main road signal.

[0012] The output end of the auxiliary power amplifier input matching network is connected with the gate of the auxiliary transistor, so as to match the port output impedance of the auxiliary input matching network to the source impedance of the auxiliary transistor and absorb the parasitic capacitance in the auxiliary transistor.

[0013] The drain of the auxiliary transistor is connected with the first end of the auxiliary bonding line, and the source of the auxiliary transistor is grounded; the second end of the auxiliary bonding line is connected with the second end of the output matching network, and the third end of the auxiliary bonding line is connected with the post matching network.

[0014] The output matching network is used to absorb the parasitic parameters of the main transistor and the parasitic capacitance of the auxiliary transistor.

[0015] The output end of the post matching network is connected with a radio frequency signal output end, so as to absorb the parasitic capacitance of the auxiliary transistor and the parasitic effect of the bonding line.

[0016] The further setting of the utility model discloses, the auxiliary bonding line includes first auxiliary bonding line and second auxiliary bonding line, one end of first auxiliary bonding line with one end of second auxiliary bonding line with the drain electrode of auxiliary transistor is connected, the other end of first auxiliary bonding line with the output matching network is connected, the other end of second auxiliary bonding line with the input end of rear matching network is connected;

[0017] The further setting of the utility model discloses, the rear matching network includes: first rear matching transmission line, second rear matching transmission line, third rear matching transmission line, fourth rear matching transmission line, fifth rear matching transmission line, sixth rear matching transmission line and seventh rear matching transmission line, wherein,

[0018] One end of first rear matching transmission line with second auxiliary bonding line is connected, and the other end of first rear matching transmission line with one end of second rear matching transmission line is connected, one end of third rear matching transmission line with the common connection end of first rear matching transmission line and second rear matching transmission line is connected, and the other end of third rear matching transmission line with one end of fourth rear matching transmission line is connected, one end of fifth rear matching transmission line with the common connection end of third rear matching transmission line and fourth rear matching transmission line is connected, and the other end of fifth rear matching transmission line is connected with radio frequency signal output end and one end of sixth rear matching transmission line respectively, one end of seventh rear matching transmission line with the common connection end of second auxiliary bonding line and first rear matching transmission line is connected, and the other end of seventh rear matching transmission line is grounded, and the other end of second rear matching transmission line, the other end of fourth rear matching transmission line and the other end of sixth rear matching transmission line are open circuit.

[0019] The further setting of the utility model discloses, the output matching network includes: first output matching transmission line, second output matching transmission line, third output matching transmission line and output matching capacitor, wherein,

[0020] One end of first output matching transmission line with main bonding line is connected, and the other end of first output matching transmission line with one end of output matching capacitor is connected, the other end of output matching capacitor with one end of third output matching transmission line is connected, and third output matching transmission line with first auxiliary bonding line is connected, one end of second output matching transmission line with the common connection end of first output matching transmission line and output matching capacitor is connected, and the other end of second output matching transmission line is grounded.

[0021] The further setting of the utility model discloses, main power amplifier input matching network includes: first main input matching transmission line, second main input matching transmission line, third main input matching transmission line, fourth main input matching transmission line, first main input matching capacitor, second main input matching capacitor, third main input matching capacitor, first main input matching resistance and second main input matching resistance, wherein,

[0022] One end of first main input matching capacitor is connected with power divider, the other end of first main input matching capacitor is connected with one end of second main input matching transmission line, the other end of second main input matching transmission line is connected with one end of third main input matching capacitor and one end of first main input matching resistance respectively, the other end of third main input matching capacitor and the other end of first main input matching resistance are connected with gate of main transistor, one end of first main input matching transmission line is connected with common terminal of first main input matching capacitor and second main input matching transmission line, the other end of first main input matching transmission line is open circuit, one end of fourth main input matching transmission line is connected with common terminal of second main input matching transmission line and third main input matching capacitor, the other end of fourth main input matching transmission line is open circuit, one end of third main input matching transmission line is connected with common terminal of second main input matching transmission line and third main input matching capacitor, the other end of third main input matching transmission line is connected with one end of second main input matching capacitor, the other end of second main input matching capacitor is grounded, one end of second main input matching resistance is connected with common terminal of third main input matching transmission line and second main input matching capacitor, the other end of second main input matching resistance is connected with voltage signal input end.

[0023] The further setting of the utility model discloses, auxiliary power amplifier input matching network includes: first auxiliary input matching transmission line, second auxiliary input matching transmission line, third auxiliary input matching transmission line, fourth auxiliary input matching transmission line, first auxiliary input matching capacitor, second auxiliary input matching capacitor, third auxiliary input matching capacitor, first auxiliary input matching resistance and second auxiliary input matching resistance, wherein,

[0024] One end of the first auxiliary input matching capacitor is connected with the power divider, the other end of the first auxiliary input matching capacitor is connected with one end of the second auxiliary input matching transmission line, the other end of the second auxiliary input matching transmission line is connected with one end of the third auxiliary input matching capacitor and one end of the second auxiliary input matching resistor respectively, the other end of the third auxiliary input matching capacitor and the other end of the second auxiliary input matching resistor are connected with the gate of the auxiliary transistor; one end of the first auxiliary input matching transmission line is connected with the common connection end of the first auxiliary input matching capacitor and the second auxiliary input matching transmission line, the other end of the first auxiliary input matching transmission line is open circuit; one end of the third auxiliary input matching transmission line is connected with the common connection end of the second auxiliary input matching transmission line and the third auxiliary input matching capacitor, the other end of the third auxiliary input matching transmission line is open circuit; one end of the fourth auxiliary input matching transmission line is connected with the common connection end of the second auxiliary input matching transmission line and the third auxiliary input matching capacitor, the other end of the fourth auxiliary input matching transmission line is connected with one end of the second auxiliary input matching capacitor, the other end of the second auxiliary input matching capacitor is grounded; one end of the first auxiliary input matching resistor is connected with the common connection end of the fourth auxiliary input matching transmission line and the second auxiliary input matching capacitor, the other end of the first auxiliary input matching resistor is connected with the voltage signal input end.

[0025] The power divider is an equal-division Wilkinson power divider.

[0026] The utility model further comprises a delay network, the input end of the delay network is connected with the second output end of the power divider, the output end of the delay network is connected with the input end of the auxiliary power amplifier input matching network, and is used for eliminating the phase difference between the signal at the input end of the auxiliary path input matching network and the main path signal.

[0027] The delay network comprises a first delay transmission line, a second delay transmission line, a third delay transmission line, a fourth delay transmission line, a fifth delay transmission line, a sixth delay transmission line, a seventh delay transmission line, an eighth delay transmission line and a first delay capacitor; one end of the first delay transmission line is connected to the power divider, and the other end of the first delay transmission line is connected to one end of the fourth delay transmission line; one end of the second delay transmission line and one end of the third delay transmission line are respectively connected to common connection ends of the first delay transmission line and the fourth delay transmission line, the other end of the second delay transmission line is open, and the other end of the third delay transmission line is grounded; the other end of the fourth delay transmission line is connected to one end of the first delay capacitor, the other end of the first delay capacitor is connected to one end of the fifth delay transmission line, and the other end of the fifth delay transmission line is connected to one end of the eighth delay transmission line; one end of the sixth delay transmission line and one end of the seventh delay transmission line are respectively connected to common connection ends of the fifth delay transmission line and the eighth delay transmission line, the other end of the sixth delay transmission line is open, the other end of the seventh delay transmission line is grounded, and the other end of the eighth delay transmission line is connected to the auxiliary power amplifier input matching network.

[0028] The power divider comprises a first power divider transmission line, a second power divider transmission line, a third power divider transmission line, a fourth power divider transmission line, a fifth power divider transmission line, a sixth power divider transmission line, a first power divider resistor, a second power divider resistor and a third power divider resistor; wherein,

[0029] One end of the first power divider transmission line is connected with the radio frequency signal input end, the other end of the power divider transmission line is connected with one end of the second power divider transmission line, the other end of the second power divider transmission line is connected with one end of the third power divider transmission line, the other end of the third power divider transmission line is connected with the input end of the main power amplifier input matching network; one end of the fourth power divider transmission line is connected with the radio frequency signal input end, the other end of the power divider transmission line is connected with one end of the fifth power divider transmission line, the other end of the fifth power divider transmission line is connected with one end of the sixth power divider transmission line, the other end of the sixth power divider transmission line is connected with the input end of the main power amplifier input matching network; one end of the first power divider resistor is connected with the common connection end of the first power divider transmission line and the second power divider transmission line, the other end of the first power divider resistor is connected with the common connection end of the fourth power divider transmission line and the fifth power divider transmission line; one end of the second power divider resistor is connected with the common connection end of the second power divider transmission line and the third power divider transmission line, the other end of the second power divider resistor is connected with the common connection end of the fifth power divider transmission line and the sixth power divider transmission line; one end of the third power divider resistor is connected with the common connection end of the third power divider transmission line and the main power amplifier input matching network, the other end of the third power divider resistor is connected with the common connection end of the sixth power divider transmission line and the auxiliary power amplifier input matching network.

[0030] Based on the above-mentioned mode conversion wideband backoff enhancement amplifying circuit, the utility model further provides an amplifier, the amplifier internally is provided with one kind of mode conversion wideband backoff enhancement amplifying circuit as mentioned above.

[0031] The utility model provides a kind of mode conversion wideband rollback enhancement amplification circuit and amplifier provided in the utility model, it includes: power divider, main power amplifier input matching network, main transistor, main bonding line, auxiliary power amplifier input matching network, auxiliary transistor, auxiliary bonding line, output matching network, after matching network;Power divider, main power amplifier input matching network, main transistor, main bonding line, auxiliary power amplifier input matching network, auxiliary transistor, auxiliary bonding line, output matching network, after matching network;Wherein, the input end of power divider is connected with radio frequency signal input end, the first output end of power divider is connected with the input end of main power amplifier input matching network, the second output end of power divider is connected with the input end of the auxiliary power amplifier input matching network, for radio frequency input signal is carried out power allocation;The output end of main power amplifier input matching network is connected with the gate of main transistor, for the port output impedance of main power amplifier input matching network is matched to the source impedance of main transistor, and the parasitic capacitance in main transistor is absorbed;The drain of main transistor is connected with one end of main bonding line, and the drain of main transistor is grounded;The other end of main bonding line is connected with the first end of output matching network;The output end of auxiliary power amplifier input matching network is connected with the gate of auxiliary transistor, for the port output impedance of auxiliary input matching network is matched to the source impedance of auxiliary transistor, and the parasitic capacitance in auxiliary transistor is absorbed;The drain of auxiliary transistor is connected with the first end of auxiliary bonding line, and the source of auxiliary transistor is grounded;The second end of auxiliary bonding line is connected with the second end of output matching network, and the third end of auxiliary bonding line is connected with after matching network;The output matching network is used to absorb the parasitic parameter of main transistor and the parasitic capacitance of auxiliary transistor;The output end of after matching network is connected with radio frequency signal output end, for absorbing the parasitic capacitance of auxiliary transistor and the parasitic effect of bonding line.Compared with prior art, the utility model discloses a kind of mode conversion wideband rollback enhancement amplification circuit and amplifier, wherein, the input end of output matching network and after matching network is connected with the output end of auxiliary bonding line respectively, the parasitic effect of bonding line is absorbed by the output matching network and the after matching network, then the influence of parasitic inductance in bonding line on circuit is reduced, so that auxiliary bonding line and parasitic capacitance become part of matching network, so as to realize impedance matching.Make the drain phase of auxiliary transistor more close to expected characteristic, realize better power amplifier performance. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or prior art, below will to the drawing needed to be used in the embodiment or prior art description simple introduction, obviously, the drawing in the following description only some embodiments of the utility model, for those skilled in the art, under the premise of not paying creative labor, other drawings can also be obtained according to the structure shown in these drawings.

[0033] Figure 1 The utility model discloses a mode conversion wideband backoff enhancement amplification circuit's circuit structure block diagram.

[0034] Figure 2 The utility model discloses a mode conversion wideband backoff enhancement amplification circuit's rear end circuit principle diagram.

[0035] Figure 3 The utility model discloses a mode conversion wideband backoff enhancement amplification circuit's front end circuit principle diagram.

[0036] Figure 4 The utility model discloses a mode conversion wideband backoff enhancement amplification circuit's rear end circuit principle diagram.

[0037] The utility model discloses a mode conversion wideband backoff enhancement amplification circuit's front end circuit principle diagram. Specific embodiments

[0038] The utility model provides a mode conversion wideband backoff enhancement amplification circuit and amplifier, for the purpose, technical scheme and effect of the utility model are more clear, definite, the following refers to the drawing and holds the example to the utility model further detailed explanation, it should be understood, the specific embodiment described here is only used to explain the utility model, and is not used to limit the utility model.

[0039] In the embodiment and the patent range, unless the article has special limitation in the text, "a", "one", "the" and "the" can include plural forms. If the embodiment of the utility model has the description of "first", "second" and the like, the description of "first", "second" and the like is only used for the description purpose, and can not be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the feature limited by "first", "second" can be explicitly or implicitly include at least one feature.

[0040] It should be further understood that the phrase "comprises" used in the specification of the present application means that the features, integers, steps, operations, elements and / or components described in the specification exist, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be an intermediate element. In addition, "connected" or "coupled" used herein can include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any one of the associated listed items and all combinations thereof.

[0041] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as generally understood by those skilled in the art to which the present application belongs. It should also be understood that terms such as those defined in a general dictionary should be understood to have meanings consistent with those in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as such.

[0042] In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of the ordinary skilled in the art, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, also not within the protection scope required by the present application.

[0043] Please refer to Figure 1 The utility model provides a mode conversion wideband backoff enhancement amplification circuit, it includes: power divider 100, main power amplifier input matching network 200, main transistor Q300, main bonding line 400, auxiliary power amplifier input matching network 600, auxiliary transistor Q700, auxiliary bonding line 800, output matching network 900, post matching network 1000.

[0044] The input end of the power divider 100 is connected with the radio frequency signal input end RF IN, the first output end of the power divider 100 is connected with the input end of the main power amplifier input matching network 200, the second output end of the power divider 100 is connected with the input end of the auxiliary power amplifier input matching network 600, for power distribution of the radio frequency input signal; the output end of the main power amplifier input matching network 200 is connected with the gate of the main transistor Q300, for matching the port output impedance of the main power amplifier input matching network 200 to the source impedance of the main transistor Q300, and absorbing the parasitic capacitance in the main transistor Q300; the drain of the main transistor Q300 is connected with one end of the main bonding line 400, and the drain of the main transistor Q300 is grounded; the other end of the main bonding line 400 is connected with the output matching network 900; the output end of the auxiliary power amplifier input matching network 600 is connected with the gate of the auxiliary transistor Q700, for matching the port output impedance of the auxiliary input matching network to the source impedance of the auxiliary transistor Q700, and absorbing the parasitic capacitance in the auxiliary transistor Q700; the drain of the auxiliary transistor Q700 is connected with the first end of the auxiliary bonding line 800, and the source of the auxiliary transistor Q700 is grounded; the second end of the auxiliary bonding line 800 is connected with the output matching network 900, and the third end of the auxiliary bonding line 800 is connected with the back matching network 1000; the output matching network 900 is used for absorbing the parasitic parameters of the main transistor Q300 and the parasitic capacitance of the auxiliary transistor Q700; the output end of the back matching network 1000 is connected with the radio frequency signal output end, for absorbing the parasitic capacitance of the auxiliary transistor Q700 and the parasitic effect of the bonding line.

[0045] In specific implementation, the input end of the power divider 100 is connected with the radio frequency signal input end RF IN, the first output end of the power divider 100 is connected with the main path branch, and the second output end is connected with the auxiliary path branch. The power divider 100 is an equal Wilkinson power divider, which performs equal power distribution on the radio frequency input signal, and outputs the main path signal and the auxiliary path signal after equal power distribution to the input end of the main power amplifier input matching network 200 and the input end of the auxiliary power amplifier input matching network 600 respectively. The main path input matching network matches the port output impedance of the main path input matching network to the impedance of the main path drive stage transistor. The impedance-matched main path signal flows through the main path drive stage transistor for signal amplification, and is output to the output matching network 900 through the main bonding line 400, and the output matching network 900 absorbs the parasitic capacitance of the main transistor Q300.

[0046] In the auxiliary branch, the auxiliary power amplifier input matching network 600 is used to match the port output impedance of the auxiliary power amplifier input matching network with the impedance of the auxiliary transistor Q700 module, and the auxiliary branch signal is amplified by the auxiliary transistor Q700 after impedance matching. The auxiliary branch signal in the auxiliary branch and the main branch signal in the main branch are combined at the drain end of the auxiliary transistor Q700, and output the input end of the post matching network 1000 signal, and then output to the radio frequency signal output end after impedance matching by the post matching network 1000. Since the drain of the auxiliary transistor Q700 is connected to the output matching network 900 and the post matching network 1000 through the bonding line, the parasitic parameters in the auxiliary bonding line 800 and the parasitic capacitance of the transistor are absorbed by the output matching network 900 and the post matching network 1000. The post matching network 1000 is used to realize impedance matching of the overall circuit, so that the transistor can work at the optimal impedance and realize the best power amplification performance. Further, the output end of the post matching network 1000 is also connected in parallel with a signal matching resistance RL, and the signal matching resistance is adjustable, which is used to improve the degree of freedom in circuit design, eliminate signal reflection, and improve signal quality.

[0047] Further, please refer to Figure 1 and Figure 2 , the auxiliary bonding line 800 includes a first auxiliary bonding line 810 and a second auxiliary bonding line 820, one end of the first auxiliary bonding line 810 and one end of the second auxiliary bonding line 820 are connected to the drain of the auxiliary transistor Q700, the other end of the first auxiliary bonding line 810 is connected to the output matching network 900, and the other end of the second auxiliary bonding line 820 is connected to the input end of the post matching network 1000; in the conventional design, the combining point of the main branch signal and the auxiliary branch signal is at P point, and the output matching network 900 of the main branch can only absorb the parasitic parameters of the main branch, but cannot absorb the parasitic parameters of the auxiliary branch, so that the phase of the drain node of the auxiliary branch is deviated from the predicted performance due to the influence of the parasitic capacitance and the bonding line. In the auxiliary bonding line 800 of the double bonding line structure of the utility model, the combining point becomes Q point, as shown in Figure 2 , the parasitic capacitance of the auxiliary transistor Q700 in the auxiliary branch and the bonding line become part of the output matching network 900, which can be absorbed by the output matching network 900.

[0048] Further, the back matching network 1000 comprises: a first back matching transmission line TLC1, a second back matching transmission line TLC2, a third back matching transmission line TLC3, a fourth back matching transmission line TLC4, a fifth back matching transmission line TLC5, a sixth back matching transmission line TLC6 and a seventh back matching transmission line TLC7; one end of the first back matching transmission line TLC1 is connected with the second auxiliary bonding line 820, and the other end of the first back matching transmission line TLC1 is connected with one end of the second back matching transmission line TLC2; one end of the third back matching transmission line TLC3 is connected with the common connection end of the first back matching transmission line TLC1 and the second back matching transmission line TLC2, and the other end of the third back matching transmission line TLC3 is connected with one end of the fourth back matching transmission line TLC4; one end of the fifth back matching transmission line TLC5 is connected with the common connection end of the third back matching transmission line TLC3 and the fourth back matching transmission line TLC4, and the other end of the fifth back matching transmission line TLC5 is connected with the radio frequency signal output end and one end of the sixth back matching transmission line TLC6 respectively; one end of the seventh back matching transmission line TLC7 is connected with the common connection end of the second auxiliary bonding line and the first back matching transmission line TLC1, and the other end of the seventh back matching transmission line TLC7 is grounded; the other end of the second back matching transmission line TLC2, the other end of the fourth back matching transmission line TLC4 and the other end of the sixth back matching transmission line TLC6 are open circuits.

[0049] Specifically, the back matching network 1000 is a third-order low-pass network, the second back matching transmission line TLC2, the fourth back matching transmission line TLC4 and the sixth back matching transmission line TLC6 are parallel open circuits, which are low-pass elements and used for absorbing part of the parasitic capacitance of the auxiliary transistor Q700 and impedance transformation. The seventh back matching transmission line TLC7 is added in the back matching network 1000 as a short circuit line, which is used for providing the bias voltage of the auxiliary transistor Q700. The back matching network 1000 is used for absorbing part of the parasitic capacitance of the auxiliary path and the parasitic effect of the bonding line, and realizing impedance matching, so that the power amplifier circuit works in the optimal performance state. By absorbing part of the parasitic capacitance of the auxiliary path and the parasitic parameters of the bonding line, and providing the drain bias of the auxiliary transistor Q700, the main path matching network is closer to the performance predicted by the SLCG theory, so that the entire amplifier circuit is equivalent to a transmission line of a symmetric network.

[0050] The output matching network 900 comprises a first output matching transmission line TLM1, a second output matching transmission line TLM2, a third output matching transmission line TLM3 and an output matching capacitor CM4. One end of the first output matching transmission line TLM1 is connected with the main bonding line 400, the other end of the first output matching transmission line TLM1 is connected with one end of the output matching capacitor CM4, the other end of the output matching capacitor CM4 is connected with one end of the third output matching transmission line TLM3, and the third output matching transmission line TLM3 is connected with the first auxiliary bonding line 810. One end of the second output matching transmission line TLM2 is connected with the common terminal of the first output matching transmission line TLM1 and the output matching capacitor CM4, and the other end of the second output matching transmission line TLM2 is grounded.

[0051] The output matching network 900 is a band-pass matching network. In order to reduce the influence of the parasitic parameters of the transistor and the bonding line on the theoretical characteristics of the circuit, the output matching network 900 is used to simultaneously absorb all the parasitic capacitances at the drain end of the main transistor Q300, part of the parasitic capacitances at the drain end of the auxiliary transistor Q700, the parasitic inductances in the main bonding line 400 and the first auxiliary bonding line 810, and the phase shift of the auxiliary branch caused by the auxiliary branch output matching element. The output matching network 900 is used to absorb the parasitic capacitances of the main transistor Q300 and part of the parasitic capacitances of the auxiliary transistor Q700, and part of the parasitic inductances in the bonding line. The output matching network 900 absorbs the additional phase shift caused by the bonding line, prevents the drain voltage of the auxiliary transistor Q700 from being too high at the back-off point, and reaches the saturation state in advance after the auxiliary transistor Q700 is turned on. The output matching network 900 is used to reduce the compression generated by the auxiliary transistor Q700 at high power, thereby reducing the influence of the auxiliary transistor Q700 on the performance of the overall circuit.

[0052] Please refer to Figure 1 and Figure 3The main power amplifier input matching network 200 comprises a first main input matching transmission line TLinM1, a second main input matching transmission line TLinM2, a third main input matching transmission line TLinM3, a fourth main input matching transmission line TLinM4, a first main input matching capacitor CinM1, a second main input matching capacitor CinM2, a third main input matching capacitor CinM3, a first main input matching resistor RinM1, and a second main input matching resistor RinM2. One end of the first main input matching capacitor CinM1 is connected to the power divider 100, and the other end of the first main input matching capacitor CinM1 is connected to one end of the second main input matching transmission line TLinM2. The other end of the second main input matching transmission line TLinM2 is connected to one end of the third main input matching capacitor CinM3 and one end of the first main input matching resistor RinM1, respectively. The other end of the third main input matching capacitor CinM3 and the other end of the first main input matching resistor RinM1 are connected to the gate of the main transistor Q300. One end of the first main input matching transmission line TLinM1 is connected to the common connection end of the first main input matching capacitor CinM1 and the second main input matching transmission line TLinM2. The other end of the first main input matching transmission line TLinM1 is open. One end of the fourth main input matching transmission line TLinM4 is connected to the common connection end of the second main input matching transmission line TLinM2 and the third main input matching capacitor CinM3, and the other end of the fourth main input matching transmission line TLinM4 is open. One end of the third main input matching transmission line TLinM3 is connected to the common connection end of the second main input matching transmission line TLinM2 and the third main input matching capacitor CinM3, and the other end of the third main input matching transmission line TLinM3 is connected to one end of the second main input matching capacitor CinM2. The other end of the second main input matching capacitor CinM2 is grounded. One end of the second main input matching resistor RinM2 is connected to the common connection end of the third main input matching transmission line TLinM3 and the second main input matching capacitor CinM2, and the other end of the second main input matching resistor RinM2 is connected to the signal input end VGM. The main power amplifier input matching network 200 is used to realize impedance transformation from the port output impedance of the main output end of the power divider 100 to the impedance of the connected transistor. The second main input matching capacitor CinM2 is a bypass capacitor, which is used to filter high-frequency noise in the input signal as a filtering object and filter high-frequency noise carried by the previous stage.

[0053] Further, the auxiliary power amplifier input matching network 600 comprises a first auxiliary input matching transmission line TLinA1, a second auxiliary input matching transmission line TLinA2, a third auxiliary input matching transmission line TLinA3, a fourth auxiliary input matching transmission line TLinA4, a first auxiliary input matching capacitor CinA1, a second auxiliary input matching capacitor CinA2, a third auxiliary input matching capacitor CinA3, a first auxiliary input matching resistor RinA1 and a second auxiliary input matching resistor RinA2. One end of the first auxiliary input matching capacitor CinA1 is connected with the power divider 100, and the other end of the first auxiliary input matching capacitor CinA1 is connected with one end of the second auxiliary input matching transmission line TLinA2. The other end of the second auxiliary input matching transmission line TLinA2 is connected with one end of the third auxiliary input matching capacitor CinA3 and one end of the second auxiliary input matching resistor RinA2 respectively. The other end of the third auxiliary input matching capacitor CinA3 and the other end of the second auxiliary input matching resistor RinA2 are connected with the gate of the auxiliary transistor. One end of the first auxiliary input matching transmission line TLinA1 is connected with the common connection end of the first auxiliary input matching capacitor CinA1 and the second auxiliary input matching transmission line TLinA2. The other end of the first auxiliary input matching transmission line TLinA1 is open. One end of the third auxiliary input matching transmission line TLinA3 is connected with the common connection end of the second auxiliary input matching transmission line TLinA2 and the third auxiliary input matching capacitor CinA3, and the other end of the third auxiliary input matching transmission line TLinA3 is open. One end of the fourth auxiliary input matching transmission line TLinA4 is connected with the common connection end of the second auxiliary input matching transmission line TLinA2 and the third auxiliary input matching capacitor CinA3, and the other end of the fourth auxiliary input matching transmission line TLinA4 is connected with one end of the second auxiliary input matching capacitor CinA2. The other end of the second auxiliary input matching capacitor CinA2 is grounded. One end of the first auxiliary input matching resistor RinA1 is connected with the common connection end of the fourth auxiliary input matching transmission line TLinA4 and the second auxiliary input matching capacitor CinA2, and the other end of the first auxiliary input matching resistor RinA1 is connected with the signal input end VGM. The second auxiliary input matching capacitor CinA2 is a bypass capacitor, which is used to filter the high-frequency noise in the input signal as a filtering object and filter the high-frequency noise carried by the previous stage.

[0054] Further, the delay network 500 comprises: a first delay transmission line TLD1, a second delay transmission line TLD2, a third delay transmission line TLD3, a fourth delay transmission line TLD4, a fifth delay transmission line TLD5, a sixth delay transmission line TLD6, a seventh delay transmission line TLD7, an eighth delay transmission line TLD8 and a first delay capacitor CD1; wherein one end of the first delay transmission line TLD1 is connected to the power divider 100, and the other end of the first delay transmission line TLD1 is connected to one end of the fourth delay transmission line TLD4; one end of the second delay transmission line TLD2 and one end of the third delay transmission line TLD3 are connected to the common connection end of the first delay transmission line TLD1 and the fourth delay transmission line TLD4 respectively, the other end of the second delay transmission line TLD2 is open, and the other end of the third delay transmission line TLD3 is grounded; the other end of the fourth delay transmission line TLD4 is connected to one end of the first delay capacitor CD1, the other end of the first delay capacitor CD1 is connected to one end of the fifth delay transmission line TLD5, and the other end of the fifth delay transmission line TLD5 is connected to one end of the eighth delay transmission line TLD8; one end of the sixth delay transmission line TLD6 and one end of the seventh delay transmission line TLD7 are connected to the common connection end of the fifth delay transmission line TLD5 and the eighth delay transmission line TLD8 respectively, the other end of the sixth delay transmission line TLD6 is open, the other end of the seventh delay transmission line TLD7 is grounded, and the other end of the eighth delay transmission line TLD8 is connected to the auxiliary power amplifier input matching network 600.

[0055] Specifically, the delay network 500 is used to eliminate the phase difference between the signal at the input end of the auxiliary path input matching network and the main path signal, so as to match the phase of the auxiliary path signal with the main path signal. The output end of the delay network 500 is connected to the input end of the auxiliary power amplifier input matching network 600, and is used to eliminate the phase difference between the signal at the input end of the auxiliary path input matching network and the main path signal. When the radio frequency input signal flows into the main branch and the auxiliary branch respectively after being divided into non-equal power signals, the phase difference between the networks generated due to the different network structures of the main branch and the auxiliary branch is different. Therefore, the delay network 500 is used to eliminate the phase difference between the main branch and the auxiliary branch, so as to ensure that the main branch and the auxiliary branch have appropriate phase relationship and ensure that the phase relationship of the main branch and the auxiliary branch is matched.

[0056] Further, the power divider 100 comprises a first power divider transmission line TLPD1, a second power divider transmission line TLPD2, a third power divider transmission line TLPD3, a fourth power divider transmission line TLPD4, a fifth power divider transmission line TLPD5, a sixth power divider transmission line TLPD6, a first power divider resistance RPD1, a second power divider resistance RPD2 and a third power divider resistance RPD3; wherein one end of the first power divider transmission line TLPD1 is connected to the radio frequency signal input end RF IN, the other end of the power divider transmission line is connected to one end of the second power divider transmission line TLPD2, the other end of the second power divider transmission line TLPD2 is connected to one end of the third power divider transmission line TLPD3, the other end of the third power divider transmission line TLPD3 is connected to the input end of the main power amplifier input matching network 200; one end of the fourth power divider transmission line TLPD4 is connected to the radio frequency signal input end RF IN, the other end of the power divider transmission line is connected to one end of the fifth power divider transmission line TLPD5, the other end of the fifth power divider transmission line TLPD5 is connected to one end of the sixth power divider transmission line TLPD6, the other end of the sixth power divider transmission line TLPD6 is connected to the input end of the main power amplifier input matching network 200; one end of the first power divider resistance RPD1 is connected to the common connection end of the first power divider transmission line TLPD1 and the second power divider transmission line TLPD2, the other end of the first power divider resistance RPD1 is connected to the common connection end of the fourth power divider transmission line TLPD4 and the fifth power divider transmission line TLPD5; one end of the second power divider resistance RPD2 is connected to the common connection end of the second power divider transmission line TLPD2 and the third power divider transmission line TLPD3, the other end of the second power divider resistance RPD2 is connected to the common connection end of the fifth power divider transmission line TLPD5 and the sixth power divider transmission line TLPD6; one end of the third power divider resistance RPD3 is connected to the common connection end of the third power divider transmission line TLPD3 and the main power amplifier input matching network 200, the other end of the third power divider resistance RPD3 is connected to the common connection end of the sixth power divider transmission line TLPD6 and the auxiliary power amplifier input matching network 600.

[0057] In particular, reference is made to Figure 1 and Figure 2When the mode conversion wideband backoff enhancement amplification circuit works, the dielectric constant of the microstrip line in the circuit is 2.2. The main auxiliary transistor is the basis for the realization of the power amplifier circuit, wherein the main transistor Q300 mainly provides the output power of the power amplifier as a whole at low power, and the auxiliary transistor Q700 mainly provides at high power. In the actual processing process, the transistor will have a certain package, so as to avoid the transistor required by the power amplifier circuit from being directly exposed to the air in the part connected with the circuit, therefore, the package of the main transistor Q300 and the auxiliary transistor Q700 is regarded as having a non-ignorable parasitic effect. As shown in Figure 2 The parasitic parameters existing at the drain end of the main transistor Q300 are the main parasitic capacitor CoutM, and the parasitic parameters existing at the drain end of the auxiliary transistor Q700 are the auxiliary parasitic capacitor CoutA. Due to the double bond line structure, the drain end of the auxiliary transistor Q700 is connected with the input end of the output matching network 900 and the input end of the post matching network 1000 respectively. Since the parasitic capacitances of the main auxiliary transistor are not equal, the output matching network 900 cannot completely absorb the parasitic capacitance of the auxiliary path. Specifically, the auxiliary parasitic capacitor in the auxiliary transistor Q700 can be equivalent to a first auxiliary parasitic capacitor CoutA1 and a second auxiliary parasitic capacitor CoutA2. Among them, due to the difference in parasitic capacitance of the main auxiliary transistor, the first auxiliary parasitic capacitor CoutA1 is the part absorbed by the output matching network 900, and the part not absorbed is the second auxiliary parasitic capacitor CoutA2, which needs to be absorbed through the post matching network 1000. Therefore, in the utility model, the drain end of the auxiliary transistor Q700 is connected with the post matching network 1000 through the double bond line structure, and the parasitic capacitance of the auxiliary transistor Q700 in the auxiliary path and the first auxiliary bond line 810 become part of the output matching network 900 and are absorbed by the output matching network 900. The post matching network 1000 absorbs part of the parasitic capacitance of the auxiliary path and the parasitic effect of the bond line, realizes the matching between the 50Ω impedance and RoptM, and makes the power amplifier impedance RoptM the optimal value 50Ω. At this time, it can be equivalent to an optimal impedance RoptM, and a transmission line with a phase of 0-90 degrees, and then the mode conversion wideband backoff enhancement amplification circuit is equivalent to a symmetrical network, realizing the theoretical performance of wideband and high backoff.

[0058] Figure 4The auxiliary transistor Q700 internal node drain voltage amplitude change value at the back-off point is shown. The back-off point is the time node when the main transistor Q300 just reaches saturation and the auxiliary transistor Q700 has not yet turned on. At this time, the auxiliary transistor Q700 internal node drain voltage Vdsa,obo at the back-off point is the auxiliary transistor Q700 drain voltage value when the main transistor Q300 drain voltage reaches saturation. Simulation results show that the internal voltage of the auxiliary transistor Q700 at the back-off point in the prior art is significantly higher than the proposed double bang line scheme, especially after the 3GHz frequency band, the voltage of the auxiliary transistor Q700 exceeds 18 volts. This can significantly reduce the power that the auxiliary transistor Q700 can output after turning on, cause the amplification circuit to enter the saturation state in advance, and thus affect the performance of the entire circuit. The auxiliary transistor Q700 drain voltage of the mode conversion wideband back-off enhancement amplification circuit in the utility model remains stable in the 3GHz frequency band, and is closer to the performance of the theoretical power amplifier than the prior art.

[0059] The utility model also provides an amplifier, it includes above-mentioned one kind mode conversion wideband back-off enhancement amplification circuit, specifically like the embodiment of one kind mode conversion wideband back-off enhancement amplification circuit described, here no longer repeat. In partial preferable embodiments, the real object of the power amplifier adopts PCB processing, uses commercial medium plate RO5880, and the area of entire power amplifier is 10.7*5.8 square centimeters.

[0060] In summary, the utility model discloses a mode conversion wideband back-off enhancement amplification circuit and amplifier, and its beneficial effects are that: through the configuration of double bang line, the absorption of transistor parasitic parameters and impedance transformation are realized in combination with the back matching network, the influence of bang line parasitic inductance on the circuit is reduced, the drain phase of auxiliary transistor is closer to the expected characteristic, thereby realizing better power amplifier performance. By connecting two bang lines to the main path and the back matching network respectively, the auxiliary bang line and the parasitic capacitor can become part of the matching network, while only the SLCG circuit structure of the main path matching network is reserved, the number of auxiliary path components is further reduced, the parasitic effects of the parasitic capacitor and the bang line are absorbed through the three-order low-pass back matching network, and impedance matching is realized.

[0061] It should be understood that the application of the utility model is not limited to the above examples, and those skilled in the art can improve or change according to the above description, and all these improvements and changes should belong to the protection scope of the claims attached to the utility model.

Claims

1. A mode conversion wideband backoff enhancement amplification circuit, characterized by, The application relates to a power amplifier, which comprises a power divider, a main power amplifier input matching network, a main transistor, a main bonding line, an auxiliary power amplifier input matching network, an auxiliary transistor, an auxiliary bonding line, an output matching network and a post matching network. The input end of the power divider is connected with a radio frequency signal input end, the first output end of the power divider is connected with the input end of the main power amplifier input matching network, and the second output end of the power divider is connected with the input end of the auxiliary power amplifier input matching network, so as to perform power distribution on a radio frequency input signal. The output end of the main power amplifier input matching network is connected with the gate of the main transistor, so as to match the port output impedance of the main power amplifier input matching network to the source impedance of the main transistor and absorb the parasitic capacitance in the main transistor. The drain of the main transistor is connected with one end of the main bonding line, and the drain of the main transistor is grounded; the other end of the main bonding line is connected with the first end of the output matching network. The output end of the auxiliary power amplifier input matching network is connected with the gate of the auxiliary transistor, so as to match the port output impedance of the auxiliary input matching network to the source impedance of the auxiliary transistor and absorb the parasitic capacitance in the auxiliary transistor. The drain of the auxiliary transistor is connected with the first end of the auxiliary bonding line, and the source of the auxiliary transistor is grounded; the second end of the auxiliary bonding line is connected with the second end of the output matching network, and the third end of the auxiliary bonding line is connected with the post matching network. The output matching network is used for absorbing the parasitic parameters of the main transistor and the parasitic capacitance of the auxiliary transistor. The output end of the post matching network is connected with a radio frequency signal output end, so as to absorb the parasitic capacitance of the auxiliary transistor and the parasitic effect of the bonding line. The auxiliary bonding line comprises a first auxiliary bonding line and a second auxiliary bonding line, one end of the first auxiliary bonding line and one end of the second auxiliary bonding line are connected with the drain of the auxiliary transistor, the other end of the first auxiliary bonding line is connected with the output matching network, and the other end of the second auxiliary bonding line is connected with the input end of the post matching network.

2. A mode conversion wideband backoff enhancement amplification circuit according to claim 1, wherein, The post matching network comprises a first post matching transmission line, a second post matching transmission line, a third post matching transmission line, a fourth post matching transmission line, a fifth post matching transmission line, a sixth post matching transmission line and a seventh post matching transmission line; wherein, 3. A mode conversion wideband backoff enhancement amplification circuit according to claim 2, wherein, ​ One end of the first back matching transmission line is connected with the second auxiliary bonding line, and the other end of the first back matching transmission line is connected with one end of the second back matching transmission line; one end of the third back matching transmission line is connected with the common connection end of the first back matching transmission line and the second back matching transmission line, and the other end of the third back matching transmission line is connected with one end of the fourth back matching transmission line; one end of the fifth back matching transmission line is connected with the common connection end of the third back matching transmission line and the fourth back matching transmission line, and the other end of the fifth back matching transmission line is connected with the radio frequency signal output end and one end of the sixth back matching transmission line respectively; one end of the seventh back matching transmission line is connected with the common connection end of the second auxiliary bonding line and the first back matching transmission line, and the other end of the seventh back matching transmission line is grounded; the other end of the second back matching transmission line, the other end of the fourth back matching transmission line and the other end of the sixth back matching transmission line are open.

4. A mode conversion wideband backoff enhancement amplification circuit according to claim 2, wherein, The output matching network comprises a first output matching transmission line, a second output matching transmission line, a third output matching transmission line and an output matching capacitor; wherein, One end of the first output matching transmission line is connected with the main bonding line, the other end of the first output matching transmission line is connected with one end of the output matching capacitor, the other end of the output matching capacitor is connected with one end of the third output matching transmission line, and the third output matching transmission line is connected with the first auxiliary bonding line; one end of the second output matching transmission line is connected with the common connection end of the first output matching transmission line and the output matching capacitor, and the other end of the second output matching transmission line is grounded.

5. A mode conversion wideband backoff enhancement amplification circuit according to claim 1, wherein, The main power amplifier input matching network comprises a first main input matching transmission line, a second main input matching transmission line, a third main input matching transmission line, a fourth main input matching transmission line, a first main input matching capacitor, a second main input matching capacitor, a third main input matching capacitor, a first main input matching resistor and a second main input matching resistor; wherein, The main power amplifier input matching network comprises a first main input matching transmission line, a second main input matching transmission line, a third main input matching transmission line, a fourth main input matching transmission line, a first main input matching capacitor, a second main input matching capacitor, a third main input matching capacitor, a first main input matching resistor and a second main input matching resistor; wherein, One end of the first main input matching capacitor is connected with the power divider, the other end of the first main input matching capacitor is connected with one end of the second main input matching transmission line, the other end of the second main input matching transmission line is connected with one end of the third main input matching capacitor and one end of the first main input matching resistor respectively, the other end of the third main input matching capacitor and the other end of the first main input matching resistor are connected with the gate of the main transistor; one end of the first main input matching transmission line is connected with the common connection end of the first main input matching capacitor and the second main input matching transmission line; the other end of the first main input matching transmission line is open; one end of the fourth main input matching transmission line is connected with the common connection end of the second main input matching transmission line and the third main input matching capacitor, and the other end of the fourth main input matching transmission line is open; one end of the third main input matching transmission line is connected with the common connection end of the second main input matching transmission line and the third main input matching capacitor, the other end of the third main input matching transmission line is connected with one end of the second main input matching capacitor, and the other end of the second main input matching capacitor is grounded; one end of the second main input matching resistor is connected with the common connection end of the third main input matching transmission line and the second main input matching capacitor, and the other end of the second main input matching resistor is connected with the voltage signal input end.

6. A mode conversion wideband backoff enhancement amplification circuit according to claim 1, wherein, The auxiliary power amplifier input matching network comprises a first auxiliary input matching transmission line, a second auxiliary input matching transmission line, a third auxiliary input matching transmission line, a fourth auxiliary input matching transmission line, a first auxiliary input matching capacitor, a second auxiliary input matching capacitor, a third auxiliary input matching capacitor, a first auxiliary input matching resistor and a second auxiliary input matching resistor; wherein, One end of the first auxiliary input matching capacitor is connected with the power divider, and the other end of the first auxiliary input matching capacitor is connected with one end of the second auxiliary input matching transmission line, and the other end of the second auxiliary input matching transmission line is connected with one end of the third auxiliary input matching capacitor and one end of the second auxiliary input matching resistor respectively, and the other end of the third auxiliary input matching capacitor and the other end of the second auxiliary input matching resistor are connected with the gate of the auxiliary transistor; one end of the first auxiliary input matching transmission line is connected with the common connection end of the first auxiliary input matching capacitor and the second auxiliary input matching transmission line; the other end of the first auxiliary input matching transmission line is open; one end of the third auxiliary input matching transmission line is connected with the common connection end of the second auxiliary input matching transmission line and the third auxiliary input matching capacitor, and the other end of the third auxiliary input matching transmission line is open; one end of the fourth auxiliary input matching transmission line is connected with the common connection end of the second auxiliary input matching transmission line and the third auxiliary input matching capacitor, and the other end of the fourth auxiliary input matching transmission line is connected with one end of the second auxiliary input matching capacitor, and the other end of the second auxiliary input matching capacitor is grounded; one end of the first auxiliary input matching resistor is connected with the common connection end of the fourth auxiliary input matching transmission line and the second auxiliary input matching capacitor, and the other end of the first auxiliary input matching resistor is connected with the voltage signal input end.

7. A mode conversion wideband backoff enhancement amplification circuit according to claim 1, wherein, The power divider is an equal Wilkinson power divider.

8. A mode conversion wideband backoff enhancement amplification circuit according to claim 1, wherein, Further comprising a delay network, an input end of the delay network is connected with the second output end of the power divider, and an output end of the delay network is connected with the input end of the auxiliary power amplifier input matching network, for eliminating the phase difference between the signal at the input end of the auxiliary path input matching network and the main path signal.

9. A mode conversion wideband backoff enhancement amplification circuit according to claim 1, wherein, The power divider comprises a first power divider transmission line, a second power divider transmission line, a third power divider transmission line, a fourth power divider transmission line, a fifth power divider transmission line, a sixth power divider transmission line, a first power divider resistor, a second power divider resistor and a third power divider resistor; wherein, One end of the first power divider transmission line is connected with the radio frequency signal input end, the other end of the power divider transmission line is connected with one end of the second power divider transmission line, the other end of the second power divider transmission line is connected with one end of the third power divider transmission line, the other end of the third power divider transmission line is connected with the input end of the main power amplifier input matching network; one end of the fourth power divider transmission line is connected with the radio frequency signal input end, the other end of the power divider transmission line is connected with one end of the fifth power divider transmission line, the other end of the fifth power divider transmission line is connected with one end of the sixth power divider transmission line, the other end of the sixth power divider transmission line is connected with the input end of the main power amplifier input matching network; one end of the first power divider resistor is connected with the common connection end of the first power divider transmission line and the second power divider transmission line, the other end of the first power divider resistor is connected with the common connection end of the fourth power divider transmission line and the fifth power divider transmission line; one end of the second power divider resistor is connected with the common connection end of the second power divider transmission line and the third power divider transmission line, the other end of the second power divider resistor is connected with the common connection end of the fifth power divider transmission line and the sixth power divider transmission line; one end of the third power divider resistor is connected with the common connection end of the third power divider transmission line and the main power amplifier input matching network, the other end of the third power divider resistor is connected with the common connection end of the sixth power divider transmission line and the auxiliary power amplifier input matching network.

10. An amplifier characterized by, The amplifier is internally provided with a mode conversion wideband backoff enhancement amplifier circuit as claimed in any one of claims 1-9.

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