Fault signal self-locking circuit and electronic equipment

Abstract

The utility model provides a fault signal self-locking circuit and electronic equipment, and belongs to the technical field of electronic circuits, the circuit comprises a fault signal judgment circuit which outputs a high level signal under the condition that the voltage value of a fault input signal is lower than a reference voltage value, and outputs a high level signal under the condition that the voltage value of the fault input signal is higher than the reference voltage value; outputting a low-level signal; the fault signal latch circuit outputs a low-level fault output signal under the condition that the high-level signal is received for the first time, outputs a high-level fault output signal under the condition that the low-level signal is received, and outputs a high-level fault output signal under the condition that the received low-level signal is changed into the high-level signal; and under the condition that the unlocking circuit receives a high-level unlocking input signal, the unlocking circuit controls the fault signal latch circuit to output a fault output signal which is changed from a high level to a low level and then is kept unchanged. According to the utility model, the technical problem that fault signals cannot be effectively stored in the prior art can be solved.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, specifically to a fault signal self-locking circuit and electronic equipment. Background Technology

[0002] Traditional fault signals are typically detected by comparing the voltage of the signal to be detected with that of a reference signal using a comparator. If the voltage of the signal to be detected exceeds the reference signal, the comparator's output signal will change. If the signal to be detected recovers, the fault signal will automatically disappear.

[0003] In practical applications, the signal to be detected often exceeds the reference signal. In this case, the signal output by the comparator will also recover on its own according to the voltage of the signal to be detected. The fault signal cannot be effectively stored, which is not conducive to fault diagnosis or repair.

[0004] In summary, existing technical solutions cannot effectively store fault signals. Utility Model Content

[0005] In view of this, it is necessary to provide a fault signal self-locking circuit and electronic device to solve the technical problem that existing technical solutions cannot effectively store fault signals.

[0006] To address the aforementioned problems, firstly, this utility model provides a fault signal self-locking circuit, comprising:

[0007] The fault signal detection circuit is used to receive fault input signals and outputs a high-level signal when the fault input signal voltage value is lower than the reference voltage value, and outputs a low-level signal when the fault input signal voltage value is higher than the reference voltage value.

[0008] A fault signal latching circuit, connected to the fault signal judgment circuit, is used to output a low-level fault output signal when a high-level signal is received for the first time, and to output a high-level fault output signal when a low-level signal is received, and to output a high-level fault output signal when the received low-level signal becomes a high-level signal.

[0009] The unlocking circuit, connected to the fault signal latching circuit, is used to control the fault signal latching circuit to output a fault output signal that changes from high level to low level and remains unchanged after receiving a high-level unlocking input signal.

[0010] In one possible implementation, the fault signal determination circuit includes a first resistor, a second resistor, and a comparator;

[0011] The first end of the first resistor is connected to the power supply, and the second end of the first resistor is connected to the non-inverting input of the comparator and is also grounded through the second resistor.

[0012] The inverting input terminal of the comparator is connected to a fault input signal;

[0013] The non-inverting input of the comparator serves as the reference voltage for the fault input signal. The comparator outputs a high-level signal when the fault input signal voltage is lower than the reference voltage and a low-level signal when the fault input signal voltage is higher than the reference voltage.

[0014] In one possible implementation, the fault signal latching circuit includes a first diode, a third resistor, a fifth resistor, a sixth resistor, a first MOSFET, and a second MOSFET.

[0015] The cathode of the first diode is connected to the output terminal of the comparator, the anode of the first diode is connected to the first terminal of the third resistor and the drain of the second MOSFET, the second terminal of the third resistor is connected to the gate of the first MOSFET, the source of the first MOSFET is connected to the power supply, the drain of the first MOSFET is connected to the first terminal of the fifth resistor and the second terminal of the sixth resistor as a fault output signal terminal, the second terminal of the fifth resistor is connected to the gate of the second MOSFET, and the source of the second MOSFET and the second terminal of the sixth resistor are both grounded.

[0016] In one possible implementation, the first MOS transistor is a P-channel MOS transistor.

[0017] In one possible implementation, the second MOSFET is an N-channel MOSFET.

[0018] In one possible implementation, the fault signal latching circuit further includes a fourth resistor;

[0019] The two ends of the fourth resistor are connected to the gate (G) and source (S) of the first MOS transistor, respectively.

[0020] In one possible implementation, the unlocking circuit includes: a second diode;

[0021] The anode of the second diode is connected to the unlock input signal, and the cathode of the second diode is connected to the second terminal of the third resistor, one terminal of the fourth resistor, and the gate of the first MOS transistor.

[0022] In one possible implementation, the first diode is a silicon diode or a germanium diode, and the second diode is a silicon diode or a germanium diode.

[0023] Secondly, this utility model provides an electronic device, including the fault signal self-locking circuit described in any of the above claims and a power supply electrically connected to the fault signal self-locking circuit.

[0024] In one possible implementation, the power source is a lithium battery.

[0025] The beneficial effects of the above implementation method are as follows: The fault signal self-locking circuit and electronic device provided by this utility model have the following characteristics: When the fault signal judgment circuit is higher than the reference voltage value, the fault signal latching circuit outputs a low-level signal; When the low-level signal is received, the fault signal latching circuit outputs a high-level fault output signal, and when the received low-level signal becomes a high-level signal, it outputs a high-level fault output signal, thereby realizing the latching of fault signals (fault input signal and fault output signal). When the unlocking circuit receives a high-level unlocking input signal, it controls the fault signal latching circuit to output a fault output signal that changes from high level to low level and remains unchanged, thereby realizing the unlocking of the fault signal. This solves the technical problem that the existing technical solutions cannot effectively store fault signals. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 A schematic diagram of the fault signal self-locking circuit provided by this utility model;

[0028] Figure 2 This is a timing diagram of the relevant signals provided by this utility model. Detailed Implementation

[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present utility model, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the scope of protection of the present utility model.

[0030] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0031] The terms “comprising” and “having” and any variations thereof in the embodiments of this utility model are intended to cover non-exclusive inclusion, for example, a process, method, apparatus, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules that are explicitly listed, but may include other steps or modules that are not explicitly listed or that are inherent to such process, method, product or device.

[0032] The naming or numbering of steps in this embodiment of the utility model does not mean that the steps in the method flow must be executed in the time / logical order indicated by the naming or numbering. The execution order of the named or numbered process steps can be changed according to the technical purpose to be achieved, as long as the same or similar technical effect can be achieved.

[0033] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the present invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0034] This utility model provides a fault signal self-locking circuit and electronic device, which will be described below.

[0035] like Figure 1 As shown, this utility model provides a fault signal self-locking circuit, including:

[0036] The fault signal judgment circuit 10 is used to receive a fault input signal and output a high-level signal when the fault input signal voltage value is lower than the reference voltage value, and output a low-level signal when the fault input signal voltage value is higher than the reference voltage value.

[0037] The fault signal latching circuit 20 is connected to the fault signal judgment circuit 10. It is used to output a low-level fault output signal when a high-level signal is received for the first time, and to output a high-level fault output signal when a low-level signal is received, and to output a high-level fault output signal when the received low-level signal becomes a high-level signal.

[0038] The unlocking circuit 30 is connected to the fault signal latching circuit 20 and is used to control the fault signal latching circuit 20 to output a fault output signal that changes from high level to low level and remains unchanged after receiving a high-level unlocking input signal.

[0039] It is understandable that the fault input signal is also the fault detection signal. When the fault signal latching circuit 20 receives a low-level signal, it outputs a high-level fault output signal. When the received low-level signal changes to a high-level signal, it outputs a high-level fault output signal, thereby realizing the latching of fault signals (fault input signal and fault output signal).

[0040] When the unlock input signal is low, it does not affect the operation of other circuit modules. When the unlock signal outputs a high-level pulse, the fault output signal changes from high level to low level and remains unchanged.

[0041] When the unlocking circuit 30 receives a high-level unlocking input signal, it controls the fault signal latching circuit 20 to output a fault output signal that changes from a high level to a low level and remains unchanged, thereby unlocking the fault signal latching circuit 20. After the fault signal latching circuit 20 is unlocked, it outputs a low-level fault output signal when it receives a high-level signal for the first time.

[0042] In some embodiments, the fault signal determination circuit 10 includes a first resistor R1, a second resistor R2, and a comparator U1;

[0043] The first end of the first resistor R1 is connected to the power supply, and the second end of the first resistor R1 is connected to the non-inverting input of the comparator U1 and is also grounded through the second resistor R2.

[0044] The inverting input terminal of the comparator U1 is connected to the fault input signal;

[0045] The non-inverting input terminal of the comparator U1 serves as the reference voltage for the fault input signal. The comparator U1 is used to output a high-level signal when the fault input signal voltage value is lower than the reference voltage value, and to output a low-level signal when the fault input signal voltage value is higher than the reference voltage value.

[0046] In some embodiments, the fault signal latching circuit 20 includes a first diode D1, a third resistor R3, a fifth resistor R5, a sixth resistor R6, a first MOSFET Q1, and a second MOSFET Q2;

[0047] The cathode of the first diode D1 is connected to the output terminal of the comparator U1. The anode of the first diode D1 is connected to the first terminal of the third resistor R3 and the drain of the second MOSFET Q2. The second terminal of the third resistor R3 is connected to the gate of the first MOSFET Q1. The source of the first MOSFET Q1 is connected to the power supply. The drain of the first MOSFET Q1 is connected to the first terminal of the fifth resistor R5 and the second terminal of the sixth resistor R6 as a fault output signal terminal. The second terminal of the fifth resistor R5 is connected to the gate of the second MOSFET Q2. The source of the second MOSFET Q2 and the second terminal of the sixth resistor R6 are both grounded.

[0048] It is understandable that a MOSFET is a field-effect transistor, with G being the gate, D being the drain, and S being the source.

[0049] In some embodiments, the first MOSFET Q1 is a P-channel MOSFET.

[0050] The second MOSFET Q2 is an N-channel MOSFET.

[0051] In some embodiments, the fault signal latching circuit 20 further includes a fourth resistor R4;

[0052] The two ends of the fourth resistor R4 are connected to the gate and source of the first MOS transistor Q1, respectively.

[0053] In some embodiments, the unlocking circuit 30 includes: a second diode D2;

[0054] The anode of the second diode D2 is connected to the unlock input signal, and the cathode of the second diode D2 is connected to the second terminal of the third resistor R3, one terminal of the fourth resistor R4, and the gate of the first MOS transistor Q1.

[0055] In some embodiments, the first diode D1 is a silicon diode or a germanium diode, and the second diode D2 is a silicon diode or a germanium diode.

[0056] In some embodiments, referring to the fault signal self-locking circuit provided by this utility model, such as Figure 2 As shown, where:

[0057] At time t1, the fault input signal FAULT_IN voltage reaches the set threshold voltage (reference voltage FAULT_REF), and the VCAMP_OUT signal and the fault output signal FAULT_OUT change from low level to high level;

[0058] At time t2, the fault input signal FAULT_IN voltage is lower than the set threshold voltage (reference voltage). The comparator U1 output signal VCAMP_OUT changes from high level to low level. The fault output signal FAULT_OUT remains low, and the fault signal is latched.

[0059] At time 3.t3, the unlock input signal UNLOCK changes from low to high, the fault output signal FALUT_OUT changes from high to low, and the fault signal is cleared.

[0060] At time t4, the unlock input signal UNLOCK changes from high level to low level, and the entire circuit returns to its initial state.

[0061] This invention also provides an electronic device, including the fault signal self-locking circuit described in any of the above claims and a power supply electrically connected to the fault signal self-locking circuit. The power supply is a lithium battery.

[0062] The fault signal self-locking circuit and electronic device provided by this utility model have been described in detail above. Specific examples have been used to illustrate the principle and implementation of this utility model. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A fail-safe latching circuit, characterized by comprising: The application relates to a fault signal self-locking circuit. The fault signal judging circuit is used for connecting a fault input signal and outputting a high level signal when the voltage value of the fault input signal is lower than a reference voltage value, and outputting a low level signal when the voltage value of the fault input signal is higher than the reference voltage value. The fault signal latching circuit is connected with the fault signal judging circuit, and is used for outputting a low level fault output signal when a high level signal is received for the first time, outputting a high level fault output signal when a low level signal is received, and outputting a high level fault output signal when the received low level signal becomes a high level signal. The unlocking circuit is connected with the fault signal latching circuit, and is used for controlling the fault signal latching circuit to keep the fault output signal unchanged after the fault output signal changes from a high level to a low level when a high level unlocking input signal is received.

2. The fail-safe circuit of claim 1, wherein, The fault signal judging circuit comprises a first resistor, a second resistor and a comparator. The first end of the first resistor is connected with a power supply, the second end of the first resistor is connected with a same direction input end of the comparator and is also connected with the ground through the second resistor. The opposite direction input end of the comparator is connected with a fault input signal. The same direction input end of the comparator is used as a reference voltage of the fault input signal, the comparator is used for outputting a high level signal when the voltage value of the fault input signal is lower than the reference voltage value, and outputting a low level signal when the voltage value of the fault input signal is higher than the reference voltage value.

3. The fail-safe latch circuit of claim 2, wherein, The fault signal latching circuit comprises a first diode, a third resistor, a fifth resistor, a sixth resistor, a first MOS tube and a second MOS tube. The cathode of the first diode is connected with the output end of the comparator, the anode of the first diode is connected with the first end of the third resistor and the D pole of the second MOS tube, the second end of the third resistor is connected with the G pole of the first MOS tube, the S pole of the first MOS tube is connected with a power supply, the D pole of the first MOS tube is connected with the first end of the fifth resistor and the second end of the sixth resistor as a fault output signal end, the second end of the fifth resistor is connected with the G pole of the second MOS tube, and the S pole of the second MOS tube and the second end of the sixth resistor are simultaneously connected with the ground.

4. The fail-safe latch circuit of claim 3, wherein, The first MOS tube is a P channel MOS tube.

5. The fail-safe latch circuit of claim 3, wherein, The second MOS tube is an N channel MOS tube.

6. The fail-safe latch circuit of claim 3, wherein, The fault signal latching circuit further comprises a fourth resistor. The two ends of the fourth resistor are respectively connected with the G pole and the S pole of the first MOS tube.

7. The fail-safe latch circuit of claim 6, wherein, The unlocking circuit comprises a second diode. The anode of the second diode is connected with an unlocking input signal, and the cathode of the second diode is respectively connected with the second end of the third resistor, one end of the fourth resistor and the G pole of the first MOS tube.

8. The fail-safe latch circuit of claim 7, wherein, The first diode is a silicon diode or a germanium diode, and the second diode is a silicon diode or a germanium diode.

9. An electronic device, comprising: The application further relates to a power supply electrically connected with the fault signal self-locking circuit.

10. The electronic device of claim 9, wherein, The power supply is a lithium battery.

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