Multi-channel clock phase synchronization circuit

Abstract

The utility model provides a multi-channel clock phase synchronization circuit. The multi-channel clock phase synchronization circuit comprises a tuning voltage unit, a crystal oscillator, a first filter, a power divider, a first signal output circuit, a first attenuator, a phase-locked loop unit and a second signal output circuit, an in-phase input end of the tuning voltage unit inputs an external tuning voltage, a voltage output end of the tuning voltage unit is connected with a control voltage end of the crystal oscillator, a radio frequency output end of the crystal oscillator is connected with an input end of the power divider through the first filter, and a first output end of the power divider is connected with the first signal output circuit; the second output end of the power divider is connected with the differential reference clock input positive end of the phase-locked loop unit through the first attenuator, and the differential radio frequency output positive end of the phase-locked loop unit is connected with the second signal output circuit. According to the invention, two paths of clock signals with different frequencies can be provided, the phases of the clock signals with different frequencies are strictly coherent, and the phases of the clock signals with the same frequency between the modules are synchronous.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a multi-channel clock phase synchronization circuit. Background Technology

[0002] With the development of microwave technology, especially communication systems, various microwave components have emerged. Frequency source modules, as core components of various communication systems, primarily function to generate the necessary reference clock signals for each module. Ensuring phase synchronization of multiple clock signals is crucial in communication systems, especially in digital and wireless communication. Clock phase synchronization ensures the stability of the communication system and improves the accuracy of data transmission.

[0003] Currently, there are two main methods for achieving clock signal phase synchronization. The first method involves using a local oscillator at the receiving end to generate the same carrier frequency and phase as the transmitting end, and adjusting the frequency and phase of the local oscillator to keep it consistent with the signal transmitted. The second method uses a phase-locked loop (PLL) to achieve phase synchronization, which also involves comparing the received signal with the output of the local oscillator and adjusting the frequency and phase of the local oscillator to synchronize it with the received signal.

[0004] However, in practical applications, a frequency source module may have one or more clock signals, such as one low-frequency clock signal and one high-frequency clock signal. Existing technologies struggle to guarantee the phase coherence and phase synchronization of multiple clock signals. Utility Model Content

[0005] This application provides a multi-channel clock phase synchronization circuit to solve the problem that the prior art cannot guarantee the phase coherence and phase synchronization of multiple clock signals.

[0006] In a first aspect, this application provides a multi-channel clock phase synchronization circuit, including: a tuning voltage unit, a crystal oscillator, a first filter, a power divider, a first signal output circuit, a first attenuator, a phase-locked loop unit, and a second signal output circuit.

[0007] The non-inverting input terminal of the tuning voltage unit receives an external tuning voltage, the voltage output terminal of the tuning voltage unit is connected to the control voltage terminal of the crystal oscillator, the radio frequency output terminal of the crystal oscillator is connected to the input terminal of the power divider through the first filter, and the first output terminal of the power divider is connected to the first signal output circuit.

[0008] The second output terminal of the power divider is connected to the positive terminal of the differential reference clock input of the phase-locked loop unit via the first attenuator, and the positive terminal of the differential RF output of the phase-locked loop unit is connected to the second signal output circuit.

[0009] In one possible implementation, the first signal output circuit includes: a second attenuator, a first radio frequency amplifier, a second filter, a third attenuator, capacitors C1, C2, C11, and C12, and inductors L2 and L3.

[0010] The first output terminal of the power divider is connected to the input terminal of the first RF amplifier via the second attenuator and the capacitor C11 in sequence.

[0011] The output of the first RF amplifier is connected to the input of the second filter via the capacitor C12, and the output of the second filter is connected to the third attenuator.

[0012] One end of the inductor L2 is connected to an external power supply, and the other end of the inductor L2 is connected to the capacitors C1 and C2 as well as one end of the inductor L3. The other ends of the capacitors C1 and C2 are grounded, and the other end of the inductor L3 is connected to the output terminal of the first RF amplifier.

[0013] In one possible implementation, the first filter and the second filter are third-order bandpass filters;

[0014] The first filter includes: capacitor C14, capacitor C17, capacitor C18, inductor L5, inductor L8, and inductor L9;

[0015] One end of the inductor L5, the inductor L8 and the capacitor C18 is connected to the RF output terminal of the crystal oscillator, the other end of the inductor L8 and the capacitor C18 is connected to ground, and the other end of the inductor L5 is connected to one end of the capacitor C14.

[0016] The other end of capacitor C14 is connected to one end of inductor L9 and capacitor C17 and the input terminal of the power divider, and the other end of inductor L9 and capacitor C17 is grounded;

[0017] The second filter includes: capacitor C13, capacitor C15, capacitor C16, inductor L4, inductor L6, and inductor L7;

[0018] One end of the inductor L4, the inductor L6 and the capacitor C16 are connected as the input terminal of the second filter, the other end of the inductor L6 and the capacitor C16 are grounded, and the other end of the inductor L4 is connected to the capacitor C13.

[0019] The other end of capacitor C13 is connected to one end of inductor L7 and capacitor C15 as the output terminal of the second filter, and the other end of inductor L7 and capacitor C15 is grounded.

[0020] In one possible implementation, the phase-locked loop unit includes: a phase-locked loop and a phase-locked loop power supply circuit;

[0021] The phase-locked loop power supply circuit includes: capacitor C19, capacitor C20, capacitor C21, capacitor C22, capacitor C55, capacitor C56, resistor R21, resistor R22, and inductor L18.

[0022] The positive terminal of capacitor C19 and one end of capacitors C20, C21 and C22 are connected to the first control voltage input terminal of the phase-locked loop. The negative terminal of capacitor C19 and the other end of capacitors C20 and C21 are grounded, and the other end of capacitor C22 is grounded.

[0023] The positive terminal of the differential RF output of the phase-locked loop is connected to the resistor R21 and the capacitor C55 in sequence and then grounded.

[0024] The negative terminal of the differential RF output of the phase-locked loop is connected to one end of the resistor R22, and the other end of the resistor R22 is connected to one end of the inductor L18.

[0025] The other end of the inductor L18 and one end of the capacitor C56 are both connected to an external power source, and the other end of the capacitor C56 is grounded.

[0026] In one possible implementation, the phase-locked loop unit further includes: a phase-locked loop filter;

[0027] The phase-locked loop filter includes: capacitor C57, capacitor C58, capacitor C59, resistor R23, resistor R24, and resistor R25;

[0028] The charge pump output terminal of the phase-locked loop is connected to one end of capacitor C58, capacitor C59 and resistor R24, the other end of capacitor C58 is grounded through resistor R25, and the other end of capacitor C59 is grounded.

[0029] The other end of resistor R24 ​​is connected to one end of resistor R23, and the other end of resistor R23 is grounded through capacitor C57. The other end of resistor R23 is the output terminal of the phase-locked loop filter.

[0030] In one possible implementation, the phase-locked loop unit further includes: an external matching circuit;

[0031] The peripheral matching circuit includes: capacitors C23, C24, C25, C26, C27, C28, C29, C32, C33, C44, C45, C50, C51, C54, C60, and C61, as well as resistors R11, R12, R15, and R20;

[0032] The enable terminal of the phase-locked loop is connected to one end of the resistor R11, the other end of the resistor R11 is connected to an external control level, the other end of the resistor R11 is also connected to one end of the capacitor C28, and the other end of the capacitor C28 is grounded.

[0033] The first bias voltage input terminal of the phase-locked loop is grounded through the capacitor C27;

[0034] The synchronization control terminal of the phase-locked loop is connected to the phase synchronization signal through the resistor R12;

[0035] The digital power input terminal of the phase-locked loop is connected to an external power supply, and one end of the capacitor C33 is connected to the digital power input terminal, while the other end is grounded.

[0036] The voltage regulator input terminal of the phase-locked loop is grounded through the capacitor C51;

[0037] The charge pump power input terminal of the phase-locked loop is connected to an external power source, and the charge pump power input terminal is grounded through the capacitor C54.

[0038] The power supply terminal of the multi-mode frequency divider circuit of the phase-locked loop is connected to an external power supply, and the power supply terminal of the multi-mode frequency divider circuit is grounded through the capacitor C60.

[0039] The buffer power supply terminal of the phase-locked loop is connected to an external power supply, and the buffer power supply terminal is grounded through the capacitor C61.

[0040] The positive terminal of the differential RF output of the phase-locked loop is connected to the second signal output circuit through the capacitor C44;

[0041] The negative terminal of the differential RF output of the phase-locked loop is grounded after passing through the capacitor C50 and the resistor R20 in sequence;

[0042] The second control voltage input terminal of the phase-locked loop is connected to an external power supply, and the second control voltage input terminal is grounded through the capacitor C32;

[0043] The second bias voltage input terminal of the phase-locked loop is grounded through the capacitor C29;

[0044] The first reference voltage terminal of the phase-locked loop is grounded through the capacitor C23;

[0045] The second reference voltage terminal of the phase-locked loop is grounded through the capacitor C24;

[0046] The bias voltage terminal of the voltage-controlled varactor diode of the phase-locked loop is grounded through the capacitor C26;

[0047] The regulated output terminal of the phase-locked loop is grounded through the capacitor C25;

[0048] The second output terminal of the power divider is connected to the positive terminal of the differential reference clock input of the phase-locked loop unit via the first attenuator, including:

[0049] The second output terminal of the power divider is connected to one end of the capacitor C45 and the resistor R15 via the first attenuator. The other end of the capacitor C45 is connected to the positive terminal of the differential reference clock input of the phase-locked loop, and the other end of the resistor R15 is grounded.

[0050] In one possible implementation, the second signal output circuit includes: a third filter, a fourth filter, a fourth attenuator, a fifth attenuator, a second RF amplifier, capacitors C30, C31, C38, and C39, and inductors L10 and L11.

[0051] The positive terminal of the differential RF output of the phase-locked loop unit is connected to the input terminal of the third filter, and the output terminal of the third filter is connected to the input terminal of the second RF amplifier in sequence through the fourth attenuator and the capacitor C38.

[0052] The output of the second RF amplifier is connected to the input of the fourth filter through the capacitor C39, and the output of the fourth filter is connected to the fifth attenuator.

[0053] One end of the inductor L10 is connected to an external power supply, and the other end is connected to one end of the capacitors C30, C31 and L11. The other ends of the capacitors C30 and C31 are grounded, and the other end of the inductor L11 is connected to the output terminal of the second RF amplifier.

[0054] In one possible implementation, the third filter and the fourth filter are seventh-order bandpass filters;

[0055] The third filter includes: capacitors C42, C36, C37, C34, C48, C46, ​​C52, inductors L12, L13, and L14.

[0056] One end of capacitor C42 is the input terminal of the third filter, and the other end of capacitor C42 is connected to one end of inductor L12, capacitor C48 and capacitor C36. The other ends of inductor L12 and capacitor C48 are grounded.

[0057] The other end of capacitor C36 is connected to one end of inductor L13, capacitor C46 and capacitor C37, and the other ends of inductor L13 and capacitor C46 are grounded;

[0058] The other end of capacitor C37 is connected to one end of inductor L14, capacitor C52 and capacitor C34, and the other ends of inductor L14 and capacitor C52 are grounded;

[0059] The other end of capacitor C34 is the output terminal of the third filter;

[0060] The fourth filter includes: capacitors C43, C40, C41, C35, C49, C47, C53, inductors L15, L16, and L17.

[0061] One end of capacitor C43 is the input terminal of the fourth filter, and the other end of capacitor C43 is connected to one end of inductor L15, capacitor C49 and capacitor C40. The other ends of inductor L15 and capacitor C49 are grounded.

[0062] The other end of capacitor C40 is connected to one end of inductor L16, capacitor C47 and capacitor C41, and the other ends of inductor L16 and capacitor C47 are grounded.

[0063] The other end of capacitor C41 is connected to one end of inductor L17, capacitor C53 and capacitor C35, and the other ends of inductor L17 and capacitor C53 are grounded.

[0064] The other end of capacitor C35 is the output terminal of the fourth filter.

[0065] In one possible implementation, the tuning voltage unit includes: an operational amplifier, capacitor C3, capacitor C4, and resistor R8;

[0066] The non-inverting input terminal of the operational amplifier is grounded through the resistor R8, and the external tuning voltage is input into the operational amplifier through the non-inverting input terminal.

[0067] The negative power supply input terminal of the operational amplifier is grounded, the positive power supply input terminal is connected to an external power supply, and the positive power supply input terminal is connected to one end of capacitor C3 and capacitor C4, while the other end of capacitor C3 and capacitor C4 is grounded.

[0068] In one possible implementation, the multi-channel clock phase synchronization circuit further includes a power supply filtering circuit for the crystal oscillator.

[0069] The power supply filtering circuit includes: capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C10 and inductor L1;

[0070] One end of the inductor L1 is connected to an external power source and is connected to one end of the capacitors C5 and C6 and the positive terminal of the capacitor C9. The other ends of the capacitors C5 and C6 and the negative terminal of the capacitor C9 are grounded.

[0071] The other end of the inductor L1 is connected to the positive terminal of the capacitor C10 and one end of the capacitors C7 and C8, and then connected to the power input terminal of the crystal oscillator. The negative terminal of the capacitor C10 and the other end of the capacitors C7 and C8 are grounded.

[0072] This application provides a multi-channel clock phase synchronization circuit, comprising: a tuning voltage unit, a crystal oscillator, a first filter, a power divider, a first signal output circuit, a first attenuator, a phase-locked loop (PLL) unit, and a second signal output circuit. An external tuning voltage is input to the non-inverting input of the tuning voltage unit. The voltage output of the tuning voltage unit is connected to the control voltage terminal of the crystal oscillator. The RF output of the crystal oscillator is connected to the input of the power divider via the first filter. The first output of the power divider is connected to the first signal output circuit. The second output of the power divider is connected to the positive terminal of the differential reference clock input of the PLL unit via the first attenuator. The positive terminal of the differential RF output of the PLL unit is connected to the second signal output circuit. This application can provide two clock signals with different frequencies, and the phases of the clock signals at different frequencies are strictly correlated, ensuring phase synchronization of clock signals of the same frequency between modules. Attached Figure Description

[0073] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0074] Figure 1 This is a schematic diagram of the structure of the multi-channel clock phase synchronization circuit provided in the embodiments of this application;

[0075] Figure 2 This is a schematic diagram of the structure of a multi-channel clock phase synchronization circuit provided in another embodiment of this application. Detailed Implementation

[0076] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0077] To make the objectives, technical solutions, and advantages of this application clearer, the following description will be provided in conjunction with the accompanying drawings and specific embodiments.

[0078] Figure 1 This is a schematic diagram of the structure of the multi-channel clock phase synchronization circuit provided in the embodiments of this application.

[0079] like Figure 1 As shown, the multi-channel clock phase synchronization circuit provided in this embodiment includes: a tuning voltage unit, a crystal oscillator, a first filter, a power divider, a first signal output circuit, a first attenuator, a phase-locked loop unit, and a second signal output circuit.

[0080] The non-inverting input terminal of the tuning voltage unit receives an external tuning voltage, the voltage output terminal of the tuning voltage unit is connected to the control voltage terminal of the crystal oscillator, the radio frequency output terminal of the crystal oscillator is connected to the input terminal of the power divider through the first filter, and the first output terminal of the power divider is connected to the first signal output circuit.

[0081] The second output terminal of the power divider is connected to the positive terminal of the differential reference clock input of the phase-locked loop unit via the first attenuator, and the positive terminal of the differential RF output of the phase-locked loop unit is connected to the second signal output circuit.

[0082] In this embodiment, the crystal oscillator is a voltage-controlled oscillator (VCO) used to provide a 38.4MHz clock signal. This 38.4MHz clock signal is filtered by a first filter to suppress harmonics, remove interference signals from other frequencies (such as spurious signals from adjacent frequency bands), and suppress various noises and interferences (such as power supply noise and electromagnetic interference), thereby improving the quality of the clock signal. The filtered 38.4MHz clock signal is split into two 38.4MHz clock signals by a power divider. One 38.4MHz clock signal is output through a first signal output circuit, while the other 38.4MHz clock signal, after its power is adjusted by a first attenuator, is input to a phase-locked loop (PLL) unit. The PLL unit, controlled by a microcontroller, rewrites its registers to output a 100MHz clock signal, which is finally output through a second signal output circuit. An external tuning voltage is supplied to the crystal oscillator after passing through a tuning voltage unit. The crystal oscillator uses the external tuning voltage to fine-tune the frequency of the clock signal by ±2ppm and adjust the phase. This ensures that the 38.4MHz clock signals between modules are in phase. With the 38.4MHz clock signal of the phase-locked loop unit in phase, the phase synchronization function of the phase-locked loop is used to obtain a phase-synchronized 100MHz clock signal. Finally, the phases of the output 38.4MHz clock signal and the 100MHz clock signal are strictly coherent.

[0083] Figure 2 This is a schematic diagram of the structure of a multi-channel clock phase synchronization circuit provided in another embodiment of this application.

[0084] like Figure 2 As shown, the circuit in this embodiment comprises resistors R1 to R25, capacitors C1 to C61, inductors L1 to L18, a first RF amplifier A1, a second RF amplifier A2, an operational amplifier N1, a crystal oscillator N2, a power divider N3, and a phase-locked loop N4. Amplifiers A1 and A2 can be RF amplifiers of model SBB2089Z, operational amplifier N1 is a field-effect transistor (FET) operational amplifier, crystal oscillator N2 is a voltage-controlled oscillator (VCO), power divider N3 is a low insertion loss RF power divider, and phase-locked loop N4 is a phase-locked loop with a built-in VCO.

[0085] To facilitate understanding, the detailed structure of this circuit will be described below according to the direction of clock signal transmission.

[0086] In one possible embodiment, such as Figure 2As shown, the tuning voltage unit includes: operational amplifier N1, capacitor C3, capacitor C4, and resistor R8; the non-inverting input terminal of the operational amplifier is grounded through the resistor R8, and the external tuning voltage is input into the operational amplifier through the non-inverting input terminal; the negative power supply input terminal of the operational amplifier is grounded, the positive power supply input terminal is connected to an external power supply, and the positive power supply input terminal is connected to one end of capacitor C3 and capacitor C4, while the other end of capacitor C3 and capacitor C4 is grounded.

[0087] The operational amplifier N1 is model AD820, which contains eight pins (1-8). Pins 1, 5, and 8: N / C indicates No Connect; Pin 2: -IN is the inverting input terminal, used to receive the inverting input signal; Pin 3: +IN is the non-inverting input terminal, receiving the external tuning voltage input, which is the signal input terminal of the operational amplifier, determining the phase and gain direction of the output signal, and is grounded through resistor R8 as a signal reference point, participating in the differential signal processing of the operational amplifier; Pin 4: -Vs is the negative power supply input terminal, directly grounded to provide a low potential reference; Pin 7: +Vs is the positive power supply input terminal, connected to an external +5V power supply to provide the operating voltage for the internal circuit of the operational amplifier, and the parallel capacitors C3 (100pF) and C4 (1μF) are used for power supply filtering to suppress high-frequency noise and low-frequency ripple; Pin 6: Vout is the voltage output terminal, outputting the amplified signal, and the output voltage is generated according to the external tuning voltage input at pin 3 and the circuit gain (determined by the external resistor).

[0088] In one possible embodiment, such as Figure 2 As shown, the multi-channel clock phase synchronization circuit also includes a power supply filtering circuit for the crystal oscillator.

[0089] The power supply filtering circuit includes: capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C10 and inductor L1;

[0090] One end of the inductor L1 is connected to an external power supply (voltage is +5V), and is connected to one end of the capacitors C5 and C6 and the positive terminal of the capacitor C9. The other ends of the capacitors C5 and C6 and the negative terminal of the capacitor C9 are grounded.

[0091] The other end of the inductor L1 is connected to the positive terminal of the capacitor C10 and one end of the capacitors C7 and C8, and then connected to the power input terminal of the crystal oscillator. The negative terminal of the capacitor C10 and the other end of the capacitors C7 and C8 are grounded.

[0092] In this embodiment, crystal N2 is a voltage-controlled oscillator, model SFN24-MS4B-80M, containing pins 1 to 5. Pin 1: Vc is the control voltage terminal, used to input external control voltage. By changing the voltage value, the output frequency of the crystal oscillator is finely adjusted to achieve dynamic frequency regulation. Pin 2: Vref is the reference voltage pin, providing a stable reference voltage for the internal circuit of the crystal oscillator to ensure the accuracy and stability of the oscillation frequency. Pin 3: GND is the ground pin, providing the circuit reference ground potential to ensure the integrity of the internal signal of the crystal oscillator and help filter noise and stabilize the working state. Pin 4: RFout is the radio frequency output terminal, outputting the high-frequency oscillation signal generated by the crystal oscillator (such as a 38.4MHz clock signal) to provide clock for subsequent circuits (such as phase-locked loops and amplifiers). Pin 5: Vcc is the power input terminal, connected to an external +5V power supply, providing working power for the internal circuit of the crystal oscillator (such as the oscillation unit and drive circuit), ensuring that the crystal oscillates normally and outputs a stable signal.

[0093] In this embodiment, capacitors C5, C6, C7, C8, C9, and C10, along with inductor L1, form the power supply filter circuit for the crystal oscillator. Small-capacity capacitors like C5, C6, C7, and C8 (100pF) utilize their low impedance to high-frequency signals to bypass high-frequency noise on the power line to ground. Larger-capacity capacitors like C9 and C10 (10μF) filter out low-frequency ripple in the power supply. Inductor L1 and the capacitors form an LC filter circuit. The inductor's characteristic of impeding current changes allows it to suppress these changes when the power supply current changes abruptly. Combined with the capacitors, this further filters out noise of different frequencies, enhancing the filtering effect and making the power supply to the crystal oscillator more stable and pure. This reduces the impact of power supply noise and fluctuations on the crystal oscillator, contributing to a stable and accurate clock signal output from the crystal oscillator. It ensures the stability of the clock reference for the entire circuit system, thereby improving system stability and reliability.

[0094] In one possible embodiment, such as Figure 2 As shown, the first filter is a third-order bandpass filter;

[0095] The first filter includes: capacitor C14, capacitor C17, capacitor C18, inductor L5, inductor L8, and inductor L9;

[0096] One end of the inductor L5, the inductor L8 and the capacitor C18 is connected to the RF output terminal of the crystal oscillator, the other end of the inductor L8 and the capacitor C18 is connected to ground, and the other end of the inductor L5 is connected to one end of the capacitor C14.

[0097] The other end of capacitor C14 is connected to one end of inductor L9 and capacitor C17 and the input terminal of the power divider, and the other end of inductor L9 and capacitor C17 is grounded.

[0098] In this embodiment, the third-order bandpass filter has a narrower passband, precisely allowing signals within a specific bandwidth around 38.4MHz to pass through while effectively suppressing signals of other frequencies. It effectively suppresses out-of-band spurious signals and harmonic components. In radio frequency circuits, it prevents spurious signals from other frequency bands from interfering with the 38.4MHz clock signal, ensuring signal purity. Its steeper transition band characteristics mean that the signal attenuation rate from the passband to the stopband is faster. For the 38.4MHz clock signal, it can achieve a transition from allowing signal passage to significantly suppressing signal within a narrower frequency range, greatly suppressing out-of-band noise and interference signals, improving the signal-to-noise ratio, and making the output clock signal purer and more stable.

[0099] In one possible embodiment, such as Figure 2 As shown, the power divider N3 is model SBTC-2-10+, containing pins 1 to 5, with pins 1 and 2 grounded; pin 3: P1 is the first output terminal, used to output the first clock signal (38.4MHz clock 1); pin 4: P2 is the second output terminal, used to output the second clock signal (38.4MHz clock 2); pin 5: SUM is the input terminal, used to receive the 38.4MHz clock signal after filtering by the first filter.

[0100] In one possible embodiment, such as Figure 2 As shown, the first signal output circuit includes: a second attenuator, a first radio frequency amplifier, a second filter, a third attenuator, capacitors C1, C2, C11, and C12, and inductors L2 and L3.

[0101] The first output terminal of the power divider is connected to the input terminal of the first RF amplifier via the second attenuator and the capacitor C11 in sequence.

[0102] The output of the first RF amplifier is connected to the input of the second filter via the capacitor C12, and the output of the second filter is connected to the third attenuator.

[0103] One end of the inductor L2 is connected to an external power supply (+5V), the other end of the inductor L2 is connected to the capacitors C1 and C2 and one end of the inductor L3, the other ends of the capacitors C1 and C2 are grounded, and the other end of the inductor L3 is connected to the output terminal of the first RF amplifier.

[0104] In this embodiment, the second and third attenuators are used to adjust the 38.4MHz signal power. The input terminal of the first RF amplifier A1 is IN, and the output terminal is OUT. Capacitors C11 and C12 block DC power for amplifier A1, and inductor L3 acts as the bias junction for amplifier A1, blocking AC power to prevent signal interference to the power supply. Capacitors C1 and C2 and inductor L2 form the power supply filter circuit for amplifier A1, filtering out high-frequency noise, ripple voltage, or other interference components in the power supply to purify the power quality, suppress noise interference, and ensure that the amplifier receives a stable and clean DC power supply, thereby improving the accuracy and reliability of signal amplification.

[0105] In one possible embodiment, such as Figure 2 As shown, the second filter is a third-order bandpass filter; the second filter includes: capacitor C13, capacitor C15, capacitor C16, inductor L4, inductor L6 and inductor L7;

[0106] One end of the inductor L4, the inductor L6 and the capacitor C16 are connected as the input terminal of the second filter, the other end of the inductor L6 and the capacitor C16 are grounded, and the other end of the inductor L4 is connected to the capacitor C13.

[0107] The other end of capacitor C13 is connected to one end of inductor L7 and capacitor C15 as the output terminal of the second filter, and the other end of inductor L7 and capacitor C15 is grounded.

[0108] In this embodiment, the third-order bandpass filter has a steeper transition band characteristic, and the signal amplitude attenuates faster outside the passband, resulting in stronger suppression of out-of-band signals. It can better suppress harmonic components or other parasitic signals of the 38.4MHz clock signal, improve the signal's spectral characteristics, make the output clock signal purer and more stable, and reduce signal distortion.

[0109] In one possible embodiment, such as Figure 2 As shown, the phase-locked loop unit includes a phase-locked loop and a phase-locked loop power supply circuit.

[0110] In this embodiment, the phase-locked loop N4 is model LMX2572LP, containing pins 1 to 40, of which pins 2, 4, 6, 13, 14, 25, 31, 34, 39, and 40 are GND terminals, directly grounded. Pin 1: CE is the phase-locked loop enable terminal; a high level or a specific level activates the chip, while a low level disables the chip to reduce power consumption; Pin 3: VbiasVCO is the first bias voltage input terminal; Pin 5: SYNC is the synchronization control terminal; Pin 7: VccDIG is the digital power input terminal; Pin 8: OSCinP is the differential reference clock input positive terminal (this scheme uses a single-ended reference input); Pin 9: OSCinM is the differential reference clock input negative terminal; Pin 10: VregIN is the voltage regulator input terminal; Pin 11: VccCP is the charge pump power input terminal; Pin 12... Pin 15: CPout is the charge pump output; Pin 16: VccMASH is the power supply for the multi-mode divider circuit; Pin 17: SCK is the SPI serial clock pin, providing a clock signal (SPI1-SCK) for SPI communication and synchronizing data transmission timing; Pin 18: SDI is the SPI serial data input pin, used to write configuration data (SPI1-DATA) to the chip's internal registers; Pins 19: RFoutMP / RFoutBP are RF signal output pins; Pin 20: MUXout is a multi-function output pin, configured for lock detection (LOCK). DET, LD (indicating whether the phase-locked loop is locked); Pin 21: VccBUF is the buffer power supply terminal; Pin 22: RFoutAM is the negative terminal of the differential RF output; Pin 23: RFoutAP is the positive terminal of the differential RF output; Pin 24: CSB is the chip select signal pin (active low), which selects the chip (SPI1-LE) in SPI communication and allows data read and write operations; Pin 26: VccVCO2 is the second control voltage input terminal; Pin 27: VbiasVCO2 is the second bias voltage input terminal; Pin 28: SysRefReq is the system reference request pin, used to synchronize external system reference signals. Enhance the stability of multi-device collaborative operation; Pin 29: VrefVCO2 is the second reference voltage terminal; Pin 30: RampClk is the ramp clock input pin; Pin 32: RampDir is the ramp direction control pin; Pin 33: VbiasVARAC is the bias voltage terminal of the voltage-controlled varactor diode; Pin 35: Vtune is the VCO tuning voltage pin, which receives the control voltage output from the loop filter and directly adjusts the VCO oscillation frequency; Pin 36: VrefVCO is the first reference voltage terminal; Pin 37: VccVCO is the first control voltage input terminal; Pin 38: VregVCO is the regulated output terminal.

[0111] In one possible embodiment, such as Figure 2As shown, the phase-locked loop power supply circuit includes: capacitor C19, capacitor C20, capacitor C21, capacitor C22, capacitor C55, capacitor C56, resistor R21, resistor R22, and inductor L18.

[0112] The positive terminal of capacitor C19 and one end of capacitors C20, C21 and C22 are connected to the first control voltage input terminal of the phase-locked loop. The negative terminal of capacitor C19 and the other end of capacitors C20 and C21 are grounded, and the other end of capacitor C22 is grounded. The positive terminal of capacitor C19 is also connected to an external +3.3V power supply.

[0113] The positive terminal of the differential RF output of the phase-locked loop is connected to the resistor R21 and the capacitor C55 in sequence and then grounded.

[0114] The negative terminal of the differential RF output of the phase-locked loop is connected to one end of the resistor R22, and the other end of the resistor R22 is connected to one end of the inductor L18.

[0115] The other end of the inductor L18 and one end of the capacitor C56 are both connected to an external power supply (providing a +3.3V voltage), and the other end of the capacitor C56 is grounded.

[0116] In this embodiment, the phase-locked loop (PLL) power supply circuit provides a stable and clean power supply to the PLL chip. Capacitors (C19-C22, C55, C56) utilize their inherent characteristics to filter out high-frequency noise and low-frequency ripple in the power supply. For example, small-capacity capacitors (such as C20, C21) bypass high-frequency noise, while large-capacity capacitors (such as C19, C23) suppress low-frequency ripple. The circuit composed of inductor L18 and resistors (R21, R22) further suppresses interference on the power line, stabilizes the current, ensures the quality of the power supply to the PLL, reduces the impact of power fluctuations and noise on the PLL performance, and guarantees its stable operation.

[0117] In one possible embodiment, such as Figure 2 As shown, the phase-locked loop unit further includes: a phase-locked loop filter;

[0118] The phase-locked loop filter includes: capacitor C57, capacitor C58, capacitor C59, resistor R23, resistor R24, and resistor R25;

[0119] The charge pump output terminal of the phase-locked loop is connected to one end of capacitor C58, capacitor C59 and resistor R24, the other end of capacitor C58 is grounded through resistor R25, and the other end of capacitor C59 is grounded.

[0120] The other end of resistor R24 ​​is connected to one end of resistor R23, and the other end of resistor R23 is grounded through capacitor C57. The other end of resistor R23 is the output terminal of the phase-locked loop filter.

[0121] In this embodiment, the loop filter is used to process the error signal output by the internal phase detector. The filter, composed of capacitors (C57-C59) and resistors (R23-R25), filters the error signal, removing high-frequency components and allowing only low-frequency control signals to pass through, converting them into a smooth DC control voltage to control the frequency of the voltage-controlled oscillator (VCO). Simultaneously, it can adjust loop parameters, affecting the phase-locked loop's acquisition characteristics (such as acquisition time and acquisition range) and stability (such as preventing loop oscillation), playing a crucial role in ensuring the phase-locked loop accurately and quickly locks onto the target frequency.

[0122] In one possible embodiment, such as Figure 2 As shown, the phase-locked loop unit further includes: an external matching circuit;

[0123] The peripheral matching circuit includes: capacitors C23, C24, C25, C26, C27, C28, C29, C32, C33, C44, C45, C50, C51, C54, C60, and C61, as well as resistors R11, R12, R15, and R20;

[0124] The enable terminal of the phase-locked loop is connected to one end of the resistor R11, the other end of the resistor R11 is connected to an external control level, the other end of the resistor R11 is also connected to one end of the capacitor C28, and the other end of the capacitor C28 is grounded.

[0125] The first bias voltage input terminal of the phase-locked loop is grounded through the capacitor C27;

[0126] The synchronization control terminal of the phase-locked loop is connected to the phase synchronization signal through the resistor R12;

[0127] The digital power input terminal of the phase-locked loop is connected to an external power supply (+3.3V), one end of the capacitor C33 is connected to the digital power input terminal, and the other end is grounded;

[0128] The voltage regulator input terminal of the phase-locked loop is grounded through the capacitor C51;

[0129] The charge pump power input terminal of the phase-locked loop is connected to an external power supply (+3.3V), and the charge pump power input terminal is grounded through the capacitor C54;

[0130] The power supply terminal of the multimode frequency divider circuit of the phase-locked loop is connected to an external power supply (+3.3V), and the power supply terminal of the multimode frequency divider circuit is grounded through the capacitor C60.

[0131] The buffer power supply terminal of the phase-locked loop is connected to an external power supply (+3.3V), and the buffer power supply terminal is grounded through the capacitor C61;

[0132] The positive terminal of the differential RF output of the phase-locked loop is connected to the second signal output circuit through the capacitor C44;

[0133] The negative terminal of the differential RF output of the phase-locked loop is grounded after passing through the capacitor C50 and the resistor R20 in sequence;

[0134] The second control voltage input terminal of the phase-locked loop is connected to an external power supply (+3.3V), and the second control voltage input terminal is grounded through the capacitor C32;

[0135] The second bias voltage input terminal of the phase-locked loop is grounded through the capacitor C29;

[0136] The first reference voltage terminal of the phase-locked loop is grounded through the capacitor C23;

[0137] The second reference voltage terminal of the phase-locked loop is grounded through the capacitor C24;

[0138] The bias voltage terminal of the voltage-controlled varactor diode of the phase-locked loop is grounded through the capacitor C26;

[0139] The regulated output terminal of the phase-locked loop is grounded through the capacitor C25;

[0140] The second output terminal of the power divider is connected to the positive terminal of the differential reference clock input of the phase-locked loop unit via the first attenuator, including:

[0141] The second output terminal of the power divider is connected to one end of the capacitor C45 and the resistor R15 via the first attenuator. The other end of the capacitor C45 is connected to the positive terminal of the differential reference clock input of the phase-locked loop, and the other end of the resistor R15 is grounded.

[0142] In this embodiment, the peripheral matching circuit is used to achieve power supply decoupling and impedance matching, maximizing chip performance. Specifically, some capacitors (such as C23-C29, C32, C33, C54, C60, and C61) are used for power supply filtering and decoupling, further stabilizing the power supply voltage and reducing power supply noise interference to the phase-locked loop (PLL). The circuit composed of resistors (R11, R12, R15, and R20) and capacitors (such as C44, C45, C50, and C51) achieves impedance matching of signals, ensuring efficient signal transmission and reducing reflections and losses. Simultaneously, it also provides a certain degree of signal isolation, preventing mutual interference between different signals, allowing the PLL to work better with other circuit modules, and improving the overall system stability and reliability.

[0143] In one possible embodiment, such as Figure 2 As shown, the second signal output circuit includes: a third filter, a fourth filter, a fourth attenuator, a fifth attenuator, a second RF amplifier, capacitors C30, C31, C38, and C39, and inductors L10 and L11.

[0144] The positive terminal of the differential RF output of the phase-locked loop unit is connected to the input terminal of the third filter via capacitor C44, and the output terminal of the third filter is connected to the input terminal of the second RF amplifier via the fourth attenuator and capacitor C38 in sequence.

[0145] The output of the second RF amplifier is connected to the input of the fourth filter through the capacitor C39, and the output of the fourth filter is connected to the fifth attenuator.

[0146] One end of the inductor L10 is connected to an external power supply (+5V), and the other end is connected to one end of the capacitors C30, C31 and L11. The other ends of the capacitors C30 and C31 are grounded, and the other end of the inductor L11 is connected to the output of the second RF amplifier.

[0147] In this embodiment, the fourth and fifth attenuators are used to adjust the 100MHz signal power. The input terminal of the second RF amplifier A2 is IN, and the output terminal is OUT. Capacitors C38 and C39 block DC for amplifier A2, and inductor L11 is the bias junction of amplifier A2, blocking AC for amplifier A2 to prevent signal interference to the power supply. Capacitors C30 and C31 and inductor L10 form the power supply filter circuit of amplifier A2, which filters out high-frequency noise, ripple voltage or other interference components in the power supply to purify the power supply quality, suppress noise interference, and ensure that the amplifier obtains a stable and clean DC power supply, thereby improving the accuracy and reliability of signal amplification.

[0148] In one possible embodiment, such as Figure 2As shown, the third filter and the fourth filter are seventh-order bandpass filters; the third filter includes: capacitors C42, C36, C37, C34, C48, C46, ​​C52, inductors L12, L13, and L14.

[0149] One end of capacitor C42 is the input terminal of the third filter, and the other end of capacitor C42 is connected to one end of inductor L12, capacitor C48 and capacitor C36. The other ends of inductor L12 and capacitor C48 are grounded.

[0150] The other end of capacitor C36 is connected to one end of inductor L13, capacitor C46 and capacitor C37, and the other ends of inductor L13 and capacitor C46 are grounded;

[0151] The other end of capacitor C37 is connected to one end of inductor L14, capacitor C52 and capacitor C34, and the other ends of inductor L14 and capacitor C52 are grounded;

[0152] The other end of capacitor C34 is the output terminal of the third filter;

[0153] The fourth filter includes: capacitors C43, C40, C41, C35, C49, C47, C53, inductors L15, L16, and L17.

[0154] One end of capacitor C43 is the input terminal of the fourth filter, and the other end of capacitor C43 is connected to one end of inductor L15, capacitor C49 and capacitor C40. The other ends of inductor L15 and capacitor C49 are grounded.

[0155] The other end of capacitor C40 is connected to one end of inductor L16, capacitor C47 and capacitor C41, and the other ends of inductor L16 and capacitor C47 are grounded.

[0156] The other end of capacitor C41 is connected to one end of inductor L17, capacitor C53 and capacitor C35, and the other ends of inductor L17 and capacitor C53 are grounded.

[0157] The other end of capacitor C35 is the output terminal of the fourth filter.

[0158] In this embodiment, a seventh-order filter is used to filter a 100MHz clock signal and suppress harmonic spurious signals. Its advantages are similar to those of a third-order bandpass filter.

[0159] It should be noted that the first to fifth attenuators in the above embodiments are all π-type attenuators, such as... Figure 2 As shown, the first attenuator consists of R3, R9 and R10, the second attenuator consists of R1, R5 and R6, the third attenuator consists of R2, R4 and R7, the fourth attenuator consists of R13, R16 and R18, and the fifth attenuator consists of R14, R17 and R19.

[0160] Combination Figure 2 The multi-channel clock phase synchronization circuit provided in this embodiment operates as follows: Crystal oscillator N2 provides a 38.4MHz clock signal, which is then filtered by a first filter (a third-order bandpass filter) to suppress harmonics. The 38.4MHz clock signal is then split into two paths by power divider N3. One path, after power adjustment by a second attenuator, is amplified by 10dB by amplifier A1 to increase power. It then passes through a second filter (a third-order bandpass filter) to suppress harmonics again, and finally, after power adjustment by a third attenuator, the 38.4MHz clock signal is output. Another 38.4MHz clock signal, after its power is adjusted by the first attenuator, is supplied to phase-locked loop (PLL) N4. PLL N4, controlled by a microcontroller, rewrites its registers to output a 100MHz clock signal. This 100MHz clock signal then passes through a third filter (a seventh-order bandpass filter) to suppress harmonic spurious signals. It then passes through a fourth attenuator for power adjustment, followed by amplification by amplifier A2, and then through another fourth filter (a seventh-order bandpass filter) for further harmonic spurious suppression. Finally, it passes through a fourth-to-fifth attenuator for power adjustment before being output as a 100MHz clock signal. An external tuning voltage, after passing through operational amplifier N1, is supplied to crystal oscillator N2. Crystal oscillator N2 can fine-tune the frequency by ±2ppm and adjust the phase using the external tuning voltage to ensure phase synchronization of the 38.4MHz clock signals between modules. When the 38.4MHz reference clock signal of PLL N4 is in phase, the phase synchronization function of the PLL can be used, triggered via SYNC (e.g., ...). Figure 2 The phase synchronization (sync') is used to obtain a phase-synchronized 100MHz clock signal.

[0161] This embodiment not only enables strict coherence of multiple clock signals of different frequencies on the same module, but also phase synchronization of clocks of the same frequency on different modules; furthermore, by placing two-stage filters on the two signal output circuits respectively, spurious noise and harmonics are effectively suppressed, so that the clock signal has good phase noise. Moreover, through the coordinated cooperation between various components such as capacitors, inductors and resistors, the circuit has good anti-interference capability and can be used in complex electromagnetic environments.

[0162] For example, taking a 38.4MHz clock signal and a 100MHz clock signal as examples, the phase noise (unit: dBc / Hz relative to the carrier) at frequencies of 10Hz, 100Hz, 1kHz, 10kHz and 100kHz was detected, and the results are shown in Table 1 and Table 2, respectively.

[0163] Table 1: Phase noise of 38.4MHz clock signal

[0164]

[0165]

[0166] Table 2: Phase noise of 100MHz clock signal

[0167]

[0168] It should be noted that the parameters of each component in the circuit are as follows:

[0169] (1) Resistor R1 is a 0603 package resistor with a resistance of 53 ohms;

[0170] (2) Resistors R2, R3, and R14 are 0603 packaged resistors with a resistance of 12 ohms;

[0171] (3) Resistors R4, R7, R9, R10, R17, and R19 are 0603 package resistors with a resistance of 430 ohms;

[0172] (4) Resistors R5 and R6 are 0603 package resistors with a resistance of 116 ohms;

[0173] (5) Resistor R8 is a 0603 package resistor with a resistance of 10 kΩ;

[0174] (6) Resistor R11 is a 0402 package resistor with a resistance of 10 kΩ;

[0175] (7) Resistor R12 is a 0402 package resistor with a resistance of 0 ohms;

[0176] (8) Resistor R13 is a 0603 package resistor with a resistance of 18 ohms;

[0177] (9) Resistors R15, R20, R21, and R22 are 0402 packaged resistors with a resistance of 51 ohms;

[0178] (10) Resistors R16 and R18 are 0603 package resistors with a resistance of 300 ohms;

[0179] (11) Resistor R23 is a 0603 package resistor with a resistance of 0 ohms;

[0180] (12) Resistor R24 ​​is a 0603 package resistor with a resistance of 100 ohms;

[0181] (13) Resistor R25 is a 0603 package resistor with a resistance of 450 ohms;

[0182] (14) Capacitors C1, C4, C6, C8, and C30 are 0603 packaged capacitors with a capacitance of 1uF (microfarad);

[0183] (15) Capacitors C2, C31, C38, and C39 are 0603 packaged capacitors with a capacitance of 1000pF;

[0184] (16) Capacitors C3, C5, C7, and C59 are 0603 packaged capacitors with a capacitance of 100pF (picofarads);

[0185] (17) Capacitors C9, C10, and C19 are A-shell capacitors with a capacitance of 10uF.

[0186] (18) Capacitors C11 and C12 are 0603 packaged capacitors with a capacitance of 3000pF;

[0187] (19) Capacitors C13 and C14 are 0805 packaged capacitors with a capacitance of 27pF;

[0188] (20) Capacitors C15, C16, C17, and C18 are 0805 packaged capacitors with a capacitance of 300pF;

[0189] (21) Capacitors C20, C44, and C50 are 0402 packaged capacitors with a capacitance of 1000pF;

[0190] (22) Capacitors C21, C22, C25, C29, C32, C33, C51, C54, C55, C56, C60, and C61 are 0402 packaged capacitors with a capacitance of 1uF;

[0191] (23) Capacitors C23, C24, C26, C27, and C28 are 0402 packaged capacitors with a capacitance of 10uF;

[0192] (24) Capacitors C34, C35, C42, and C43 are 0805 packaged capacitors with a capacitance of 15pF;

[0193] (25) Capacitors C36, C37, C40, and C41 are 0805 packaged capacitors with a capacitance of 4.3pF;

[0194] (26) Capacitor C45 is a 0402 package capacitor with a capacitance of 3000pF;

[0195] (27) Capacitors C46 and C47 are 0805 packaged capacitors with a capacitance of 43pF;

[0196] (28) Capacitors C48, C49, C52, and C53 are 0805 packaged capacitors with a capacitance of 33pF;

[0197] (29) Capacitor C57 is a 0603 package capacitor with a capacitance of 1.5nF (nanofa).

[0198] (30) Capacitor C58 is a 0603 package capacitor with a capacitance of 25nF;

[0199] (31) Inductor L1 is a power inductor with an LPS4012-223M2 package;

[0200] (32) Inductors L2 and L10 are wire-wound inductors with a package size of 0603 and an inductance value of 1uH (microhenry);

[0201] (33) Inductors L3 and L11 are wire-wound inductors with a package size of 0603 and an inductance value of 820nH (NaHenry);

[0202] (34) Inductors L4 and L5 are wire-wound inductors with a package size of 0805 and an inductance value of 680nH;

[0203] (35) Inductors L6, L7, L8, and L9 are wire-wound inductors with a package size of 0805 and an inductance value of 56nH.

[0204] (36) Inductors L12, L13, L14, L15, L16, and L17 are self-made hollow inductors;

[0205] (37) Inductor L18 is a wire-wound inductor with a package of 0603 and an inductance of 47nH.

[0206] Furthermore, the features of the embodiments shown in the accompanying drawings or the various embodiments mentioned in this specification should not be construed as independent embodiments. Rather, each feature described in one example of an embodiment can be combined with one or more other desired features from other embodiments to produce other embodiments not described in words or with reference to the accompanying drawings.

[0207] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A multi-path clock phase synchronization circuit, characterized by, The application relates to a signal output circuit, which comprises a tuning voltage unit, a crystal oscillator, a first filter, a power divider, a first signal output circuit, a first attenuator, a phase-locked loop unit and a second signal output circuit. The in-phase input end of the tuning voltage unit inputs an external tuning voltage, the voltage output end of the tuning voltage unit is connected with the control voltage end of the crystal oscillator, the radio frequency output end of the crystal oscillator is connected with the input end of the power divider through the first filter, and the first output end of the power divider is connected with the first signal output circuit. The second output end of the power divider is connected with the differential reference clock input positive end of the phase-locked loop unit through the first attenuator, and the differential radio frequency output positive end of the phase-locked loop unit is connected with the second signal output circuit. The first signal output circuit comprises a second attenuator, a first radio frequency amplifier, a second filter, a third attenuator, a capacitor C1, a capacitor C2, a capacitor C11, a capacitor C12, an inductor L2 and an inductor L3.

2. The multi-path clock phase synchronization circuit of claim 1, wherein, The first output end of the power divider is connected with the input end of the first radio frequency amplifier through the second attenuator and the capacitor C11 in sequence. The output end of the first radio frequency amplifier is connected with the input end of the second filter through the capacitor C12, and the output end of the second filter is connected with the third attenuator. One end of the inductor L2 is connected with a power supply, the other end of the inductor L2 is connected with the capacitor C1, the capacitor C2 and one end of the inductor L3, the other ends of the capacitor C1 and C2 are grounded, and the other end of the inductor L3 is connected with the output end of the first radio frequency amplifier. The first filter and the second filter are third-order band-pass filters.

3. The multi-path clock phase synchronization circuit of claim 2, wherein, The first filter comprises a capacitor C14, a capacitor C17, a capacitor C18, an inductor L5, an inductor L8 and an inductor L9. One end of the inductor L5, the inductor L8 and the capacitor C18 is connected with the radio frequency output end of the crystal oscillator, the other ends of the inductor L8 and the capacitor C18 are connected with the ground, and the other end of the inductor L5 is connected with one end of the capacitor C14. The other end of the capacitor C14 is connected with one end of the inductor L9, the capacitor C17 and the input end of the power divider, and the other ends of the inductor L9 and the capacitor C17 are grounded. The second filter comprises a capacitor C13, a capacitor C15, a capacitor C16, an inductor L4, an inductor L6 and an inductor L7. One end of the inductor L4, the inductor L6 and the capacitor C16 is connected, serving as the input end of the second filter, the other ends of the inductor L6 and the capacitor C16 are grounded, and the other end of the inductor L4 is connected with the capacitor C13. The other end of the capacitor C13 is connected with one end of the inductor L7 and the capacitor C15, serving as the output end of the second filter, and the other ends of the inductor L7 and the capacitor C15 are grounded. The phase-locked loop unit comprises a phase-locked loop and a phase-locked loop feed circuit.

4. The multi-path clock phase synchronization circuit of claim 1, wherein, ​ The phase-locked loop feed circuit comprises a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C55, a capacitor C56, a resistor R21, a resistor R22 and an inductor L18; The positive pole of the capacitor C19 is connected to the first control voltage input end of the phase-locked loop, one end of the capacitor C20, the capacitor C21 and the capacitor C22, the negative pole of the capacitor C19 and the other end of the capacitor C20 and the capacitor C21 are grounded, and the other end of the capacitor C22 is grounded; The positive end of the differential radio frequency output of the phase-locked loop is connected to the resistor R21 and the capacitor C55 in turn and then grounded; The negative end of the differential radio frequency output of the phase-locked loop is connected to one end of the resistor R22, and the other end of the resistor R22 is connected to one end of the inductor L18; The other end of the inductor L18 and one end of the capacitor C56 are both externally connected to a power supply, and the other end of the capacitor C56 is grounded.

5. The multi-path clock phase synchronization circuit of claim 4, wherein, The phase-locked loop unit further comprises a phase-locked loop loop filter; The phase-locked loop loop filter comprises a capacitor C57, a capacitor C58, a capacitor C59, a resistor R23, a resistor R24 and a resistor R25; The charge pump output end of the phase-locked loop is connected to one end of the capacitor C58, the capacitor C59 and the resistor R24, the other end of the capacitor C58 is grounded through the resistor R25, and the other end of the capacitor C59 is grounded; The other end of the resistor R24 is connected to one end of the resistor R23, the other end of the resistor R23 is grounded through the capacitor C57, and the other end of the resistor R23 is the output end of the phase-locked loop loop filter.

6. The multi-path clock phase synchronization circuit of claim 4, wherein, The phase-locked loop unit further comprises a peripheral matching circuit; The peripheral matching circuit comprises a capacitor C23, a capacitor C24, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, a capacitor C29, a capacitor C32, a capacitor C33, a capacitor C44, a capacitor C45, a capacitor C50, a capacitor C51, a capacitor C54, a capacitor C60 and a capacitor C61, and a resistor R11, a resistor R12, a resistor R15 and a resistor R20; The enable end of the phase-locked loop is connected to one end of the resistor R11, the other end of the resistor R11 is externally connected to a control level, the other end of the resistor R11 is also connected to one end of the capacitor C28, and the other end of the capacitor C28 is grounded; The first bias voltage input end of the phase-locked loop is grounded through the capacitor C27; The synchronization control end of the phase-locked loop is connected to a phase synchronization signal through the resistor R12; The digital power supply input end of the phase-locked loop is externally connected to a power supply, one end of the capacitor C33 is connected to the digital power supply input end, and the other end is grounded; The voltage stabilization input end of the phase-locked loop is grounded through the capacitor C51; The charge pump power supply input end of the phase-locked loop is externally connected to a power supply, and the charge pump power supply input end is grounded through the capacitor C54; The multi-mode frequency divider circuit power supply end of the phase-locked loop is externally connected to a power supply, and the multi-mode frequency divider circuit power supply end is grounded through the capacitor C60; The buffer power supply end of the phase-locked loop is externally connected with a power supply, and the buffer power supply end is grounded through the capacitor C61; The differential radio frequency output positive end of the phase-locked loop is connected with the second signal output circuit through the capacitor C44; The differential radio frequency output negative end of the phase-locked loop is grounded after passing through the capacitor C50 and the resistor R20 in sequence; The second control voltage input end of the phase-locked loop is externally connected with a power supply, and the second control voltage input end is grounded through the capacitor C32; The second bias voltage input end of the phase-locked loop is grounded through the capacitor C29; The first reference voltage end of the phase-locked loop is grounded through the capacitor C23; The second reference voltage end of the phase-locked loop is grounded through the capacitor C24; The bias voltage end of the voltage-controlled varactor diode of the phase-locked loop is grounded through the capacitor C26; The voltage-stabilized output end of the phase-locked loop is grounded through the capacitor C25; The second output end of the power divider is connected with the differential reference clock input positive end of the phase-locked loop unit through the first attenuator, and comprises: The second output end of the power divider is connected with the capacitor C45 and one end of the resistor R15 through the first attenuator, the other end of the capacitor C45 is connected with the differential reference clock input positive end of the phase-locked loop, and the other end of the resistor R15 is grounded.

7. The multi-path clock phase synchronization circuit of claim 1, wherein, The second signal output circuit comprises a third filter, a fourth filter, a fourth attenuator, a fifth attenuator, a second radio frequency amplifier, a capacitor C30, a capacitor C31, a capacitor C38, a capacitor C39, an inductor L10 and an inductor L11; The differential radio frequency output positive end of the phase-locked loop unit is connected with the input end of the third filter, and the output end of the third filter is connected with the input end of the second radio frequency amplifier through the fourth attenuator and the capacitor C38 in sequence; The output end of the second radio frequency amplifier is connected with the input end of the fourth filter through the capacitor C39, and the output end of the fourth filter is connected with the fifth attenuator; One end of the inductor L10 is externally connected with a power supply, the other end of the inductor L10 is connected with the capacitor C30, the capacitor C31 and one end of the inductor L11, the other ends of the capacitor C30 and the capacitor C31 are grounded, and the other end of the inductor L11 is connected with the output end of the second radio frequency amplifier.

8. The multi-path clock phase synchronization circuit of claim 7, wherein, The third filter and the fourth filter are seven-order band-pass filters; The third filter comprises a capacitor C42, a capacitor C36, a capacitor C37, a capacitor C34, a capacitor C48, a capacitor C46, a capacitor C52, an inductor L12, an inductor L13 and an inductor L14; One end of the capacitor C42 is the input end of the third filter, the other end of the capacitor C42 is connected with one end of the inductor L12, the capacitor C48 and the capacitor C36, and the other ends of the inductor L12 and the capacitor C48 are grounded; The other end of the capacitor C36 is connected with one end of the inductor L13, the capacitor C46 and the capacitor C37, and the other ends of the inductor L13 and the capacitor C46 are grounded; The other end of the capacitor C37 is connected to one end of the inductor L14, the capacitor C52 and the capacitor C34, and the other end of the inductor L14 and the capacitor C52 is grounded; The other end of the capacitor C34 is an output end of the third filter; The fourth filter comprises a capacitor C43, a capacitor C40, a capacitor C41, a capacitor C35, a capacitor C49, a capacitor C47, a capacitor C53, an inductor L15, an inductor L16 and an inductor L17; One end of the capacitor C43 is an input end of the fourth filter, and the other end of the capacitor C43 is connected to one end of the inductor L15, the capacitor C49 and the capacitor C40, and the other end of the inductor L15 and the capacitor C49 is grounded; The other end of the capacitor C40 is connected to one end of the inductor L16, the capacitor C47 and the capacitor C41, and the other end of the inductor L16 and the capacitor C47 is grounded; The other end of the capacitor C41 is connected to one end of the inductor L17, the capacitor C53 and the capacitor C35, and the other end of the inductor L17 and the capacitor C53 is grounded; The other end of the capacitor C35 is an output end of the fourth filter.

9. The multi-path clock phase synchronization circuit of any of claims 1-8, wherein, The tuning voltage unit comprises an operational amplifier, a capacitor C3, a capacitor C4 and a resistor R8; The non-inverting input end of the operational amplifier is grounded through the resistor R8, and an external tuning voltage is input into the operational amplifier through the non-inverting input end; The negative power supply input end of the operational amplifier is grounded, the positive power supply input end is externally connected to a power supply, and the positive power supply input end is connected to one end of the capacitor C3 and the capacitor C4, and the other end of the capacitor C3 and the capacitor C4 is grounded.

10. The multi-path clock phase synchronization circuit of any of claims 1-8, wherein, The power supply filtering circuit of the crystal oscillator is further included; The power supply filtering circuit comprises a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10 and an inductor L1; One end of the inductor L1 is externally connected to a power supply, and connected to one end of the capacitor C5 and the capacitor C6 and the positive electrode of the capacitor C9, and the other end of the capacitor C5 and the capacitor C6 and the negative electrode of the capacitor C9 is grounded; The other end of the inductor L1 is connected to the positive electrode of the capacitor C10 and one end of the capacitor C7 and the capacitor C8, and then connected to the power supply input end of the crystal oscillator, and the negative electrode of the capacitor C10 and the other end of the capacitor C7 and the capacitor C8 is grounded.

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