Semiconductor device and electronic apparatus

Abstract

The utility model provides a semiconductor device and electronic equipment. The semiconductor device includes a substrate and a gate structure. Wherein the substrate is provided with active regions and isolation regions, the isolation regions are arranged between the adjacent active regions, and the active regions are arranged between the adjacent isolation regions; the active region is provided with a groove, and the groove is filled with a semiconductor material for forming a source electrode or a drain electrode. The gate structure is arranged on the surface of the substrate and is arranged in the active region, and the end part of the gate structure extends to the isolation region connected with the active region. The gate structure comprises a gate and a side wall arranged on the side surface of the gate, an insulating protection layer is arranged on the surface of the isolation region, and the insulating protection layer covers the residual surface of the substrate except the gate structure in the isolation region; and the side wall extending to the isolation region is connected with the substrate. The insulating protection layer can protect the isolation region from being corroded, so that the side wall of the gate structure can keep higher integrity, and the semiconductor device can keep higher reliability and longer service life.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a semiconductor device and an electronic device. BACKGROUND

[0002] In the field of semiconductor technology, a metal oxide semiconductor field effect transistor (MOSFET) device includes an N-type metal oxide semiconductor field effect transistor (NMOS) and a P-type metal oxide semiconductor field effect transistor (PMOS). The carriers of the NMOS are electrons, and the carriers of the PMOS are holes. Since the effective mass of the hole is larger than that of the electron, the mobility of the hole is much smaller than that of the electron. In order to maintain the carrier balance in the MOSFET device and improve the speed of the PMOS, it is necessary to improve the mobility of the hole. In the related art, in order to improve the mobility of the hole, a silicon-germanium (SiGe) material is epitaxially grown in a source-drain electrode region of a semiconductor substrate, and a lateral compressive stress generated by the silicon-germanium material extrudes a channel region, so that the lattice constant in the channel region is reduced, thereby improving the mobility of the hole. However, in the pickling process after the epitaxial growth process, the side wall of the gate structure is damaged, thereby increasing the breakdown probability of the gate and the source and drain, and affecting the reliability and service life of the MOSFET device. CONTENT OF THE INVENTION

[0003] The present application provides a semiconductor device and an electronic device to solve the problem of reducing the reliability and service life of the semiconductor device due to the damage of the gate side wall.

[0004] In a first aspect, the present application provides a semiconductor device, which includes a substrate and a gate structure. The substrate has a plurality of active regions and a plurality of isolation regions, and the isolation regions are arranged between adjacent active regions. The active regions are arranged between adjacent isolation regions. At least one of the plurality of active regions is provided with a trench, and the trench is filled with a semiconductor material to form a source or a drain. The gate structure is provided in multiple, and at least one of the multiple gate structures is arranged in an active region and extends to the isolation regions adjacent to the active region at both ends. At least one of the multiple gate structures includes a gate and a side wall arranged on the side of the gate. The surface of the plurality of isolation regions is provided with an insulating protective layer. In the isolation region, the insulating protective layer covers the remaining surface of the substrate except the gate structure. The side wall extending to the isolation region is connected to the substrate.

[0005] In the manufacturing process of the prior semiconductor device, when etching the trench in the active region of the substrate, the substrate of the isolation region is also corroded by the acid solution to form an inevitable additional trench. In the acid washing process after the epitaxial growth of the semiconductor material in the trench, the acid solution will corrode the side wall of the isolation region from the bottom of the additional trench to separate the side wall from the substrate to form a gap, and the acid solution will also penetrate into the active region along the gap to corrode the side wall of the active region, so that the side wall loses the original blocking effect and increases the breakdown probability of the semiconductor device. The semiconductor device of the present application can protect the substrate of the isolation region from being corroded by the insulating protective layer on the remaining surface of the substrate except the gate structure in the isolation region during the trench etching process, so as to avoid the formation of the additional trench, thereby preventing the acid solution from corroding the bottom of the side wall of the isolation region through the additional trench of the isolation region in the subsequent acid washing process after epitaxial growth, so that the bottom of the side wall of the isolation region is always connected with the substrate, thereby keeping the high integrity of the side wall in the isolation region and the active region, keeping the original isolation effect of the side wall, and inhibiting the short channel effect. Therefore, the semiconductor device of the embodiment of the present application can avoid the breakdown problem of the gate to the source and the drain due to the cavity at the bottom of the side wall, so as to keep the high reliability and service life of the semiconductor device.

[0006] In an implementation manner, the etching rate of the insulating protective layer is lower than the etching rate of the substrate. The corrosion rate of the insulating protective layer is lower than the corrosion rate of the substrate, so that the insulating protective layer can protect the substrate of the isolation region from being etched during the trench etching process of the active region.

[0007] In an implementation manner, the substrate of the active region includes a first base layer, and the source or the drain is arranged on the first base layer, and the surface of the first base layer is not provided with the insulating protective layer; the substrate of the isolation region includes a first base layer and a second base layer which are arranged in a stack, the second base layer is an insulating layer, the gate structure of the isolation region is connected with the second base layer, and the insulating protective layer is arranged on the surface of the second base layer. The first base layer of the active region is mainly used for manufacturing the source or the drain and the channel. The substrate of the isolation region has a first base layer at the bottom, and a second base layer can be formed on the first base layer by etching and filling processes, and the second base layer is an insulating layer to realize the isolation between the active regions.

[0008] In an implementation manner, the first base layer is silicon, and the second base layer is silicon dioxide.

[0009] In an implementation manner, the insulating protective layer is a film layer which can be deposited on the second base layer, and the insulating protective layer is a film layer which cannot be deposited on the first base layer, so that the insulating protective layer can be directly formed on the surface of the second base layer of the isolation region by one process when the insulating protective layer is manufactured.

[0010] As an example, the insulating protective layer is a film layer formed on the surface of the isolation region by a selective deposition method. By using the selective deposition, the insulating protective layer can be directly formed on the surface of the isolation region, avoiding the formation of the insulating protective layer on the surface of the active region.

[0011] In an implementation, in the isolation region, the surface of the substrate adjacent to the insulating protective layer is coplanar with the surface of the substrate adjacent to the gate structure. That is, the substrate corresponding to the isolation region is not formed with an additional trench. The substrate of the isolation region is not formed with an additional trench, which can block the etching liquid from corroding the side wall through the trench of the isolation region in the later removal process of the hard mask layer, protecting the side wall from being damaged.

[0012] In an implementation, the insulating protective layer is an inorganic protective layer or an organic polymer layer. The use of the inorganic protective layer or the organic polymer layer can both achieve the protection of the substrate and etch the substrate of the isolation region by the etching liquid.

[0013] In an implementation, the inorganic protective layer includes one of aluminum oxide, titanium oxide, zinc oxide, thallium oxide, silicon nitride, silicon oxide, or silicon carbide. The surface of the substrate corresponding to the isolation region is formed with silicon oxide, and the use of aluminum oxide, titanium oxide, zinc oxide, thallium oxide, silicon oxide, silicon nitride, silicon oxide, or silicon carbide can achieve the selective deposition of silicon oxide, facilitating the formation of the insulating protective layer in the isolation region.

[0014] In an implementation, the organic polymer layer includes one of trimethoxysilane or perfluorooctyltriethoxysilane. The above polymer can be combined on the surface of the isolation region by selective deposition and can resist the corrosion of the acidic etching liquid, having a high acid corrosion resistance. Therefore, the isolation region can be effectively protected.

[0015] In an implementation, the thickness of the insulating protective layer is 1-10 nm. If the thickness of the insulating protective layer is too low, the insulating protective layer is prone to have in-plane defects, which is insufficient to effectively prevent corrosion. If the thickness of the insulating protective layer is too high, the height of the isolation region is prone to be too high, and the height difference between the isolation region and the source / drain region is too large, which can adversely affect the later device manufacturing. Therefore, the thickness of the insulating protective layer is controlled in the range of 1-10 nm, which can improve the protection effect of the insulating protective layer without affecting the semiconductor device manufacturing.

[0016] In an implementation, the trench is a sigma trench. The cross section of the trench in the direction perpendicular to the surface of the semiconductor substrate is a hexagon. The sigma trench can help to enhance the compressive stress of the subsequently formed source / drain electrode on the channel region, further improving the corresponding speed of the semiconductor device.

[0017] In one implementation, the lattice constant of the semiconductor material filled in the trench is greater than the lattice constant of the substrate. Thus, the semiconductor material filled in the trench can generate a lateral compressive stress to squeeze the channel region under the gate to make the lattice constant of the channel region smaller, thereby improving the mobility of the holes.

[0018] In a second aspect, the present application provides an electronic device, comprising: a circuit board and the semiconductor device of the present application, wherein the semiconductor device is arranged on the circuit board.

[0019] The electronic device of the present application can be a terminal mobile device such as a mobile phone, a tablet computer, a notebook computer, a smart wearable product, a virtual reality terminal device, an augmented reality terminal device, etc. The electronic device of the present application can also be a device such as a drone, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, and a communication electronic product. Since the semiconductor device of the present application has high reliability, the electronic device containing the semiconductor device of the present application also has high reliability.

[0020] In a third aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

[0021] providing a substrate, wherein the substrate has a plurality of active regions and a plurality of isolation regions, the isolation regions are arranged between adjacent active regions, the active regions are arranged between adjacent isolation regions, and the substrate has a plurality of gate structures on the surface thereof; at least one of the plurality of gate structures is arranged in an active region and has two ends extending to the isolation regions adjacent to the active region, respectively; and at least one of the plurality of gate structures comprises a gate and a side wall arranged on the side surface of the gate;

[0022] forming an insulating protective layer on the surface of the isolation region by using a selective deposition method, wherein the insulating protective layer covers the remaining surface of the substrate except for the gate structures on the isolation region;

[0023] forming a hard mask layer on the surface of the active region, the surface of the gate structure, and the surface of the insulating protective layer;

[0024] etching to remove the hard mask layer on the surface of the active region and the hard mask layer on the top surface of the gate structure;

[0025] etching to form a trench in the active region;

[0026] epitaxially growing a semiconductor material at the trench to form a source electrode or a drain electrode;

[0027] etching to remove the hard mask layer on the side surface of the side wall.

[0028] In the method for manufacturing the semiconductor device, before forming the hard mask layer, an insulating protective layer is formed on the surface of the isolation region. The insulating protective layer covers the remaining surface of the substrate except the gate structure in the isolation region. In the subsequent trench etching process of the active region, the insulating protective layer can protect the substrate in the isolation region from being etched to form additional trenches. In the acid washing process after epitaxial growth of semiconductor material in the trench, the insulating protective layer can also protect the substrate in the isolation region and the sidewall of the gate structure from being etched, so that the bottom of the sidewall in the isolation region is always connected with the substrate, thereby keeping the sidewall in the isolation region and the active region in a high integrity, keeping the original isolation effect of the sidewall, and inhibiting the short channel effect. Thus, the semiconductor device of the embodiment can avoid the problem of breakdown from the gate to the source and the drain due to the void at the bottom of the sidewall, thereby keeping the semiconductor device in a high reliability and service life.

[0029] In an implementation manner, the etching selectivity ratio of the insulating protective layer and the hard mask layer is greater than or equal to 18:1. The insulating protective layer is not easy to be etched compared with the hard mask layer, so that the substrate and the sidewall can be protected from being etched in the manufacturing process of the semiconductor device, and the sidewall can be kept in a high integrity.

[0030] In an implementation manner, in the isolation region, the surface of the substrate corresponding to the insulating protective layer is arranged in a coplanar manner with the surface of the substrate corresponding to the gate structure. That is, the substrate corresponding to the isolation region is not formed with a trench. The substrate of the isolation region is not formed with a trench, which can block the etching liquid from corroding the sidewall through the trench of the isolation region in the later removal process of the hard mask layer, and protect the sidewall from being damaged.

[0031] In an implementation manner, the insulating protective layer is an inorganic protective layer or an organic polymer layer. The inorganic protective layer or the organic polymer layer can both achieve the protection of the substrate from being etched by the etching liquid.

[0032] In an implementation manner, the inorganic protective layer includes at least one of aluminum oxide, titanium oxide, zinc oxide, thallium oxide, silicon nitride, silicon oxide, or silicon carbide. The isolation region is usually silicon oxide, and silicon nitride, silicon oxide, or silicon carbide can achieve selective deposition on silicon oxide, thereby facilitating the formation of the insulating protective layer on the isolation region.

[0033] In an implementation manner, the organic polymer layer includes one of trimethoxysilane or perfluorooctyltriethoxysilane. The above polymer can be combined on the surface of the isolation region through selective deposition and can resist the corrosion of the acid etching liquid, and has a high acid corrosion resistance. Thus, the isolation region can be effectively protected.

[0034] In an implementation, the thickness of the insulating protective layer is 1-10 nm. If the thickness of the insulating protective layer is too low, the insulating protective layer is prone to have in-plane defects and is not sufficient to effectively prevent corrosion. If the thickness of the insulating protective layer is too high, the height of the isolation region is prone to be too high, and the height difference between the isolation region and the source / drain region is too large, which can adversely affect the subsequent device manufacturing. Therefore, the thickness of the insulating protective layer is controlled in the range of 1-10 nm, which can improve the protection effect of the insulating protective layer without affecting the semiconductor device manufacturing.

[0035] In the above possible implementation, the data of the application, such as the thickness of the insulating protective layer, the etching selectivity ratio of the insulating protective layer and the hard mask layer, and the like, should be understood as being within the range defined by the application within the range of engineering measurement error. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a schematic diagram of a partial top view structure of a semiconductor device;

[0037] Figures 2 to 6 is a schematic diagram of a partial top view structure of a semiconductor device; Figure 1 is a schematic diagram of a cross-sectional structure of a manufacturing process at A-A and B-B shown in the figure;

[0038] Figure 7 is a TEM diagram of a side wall of a prior art semiconductor device;

[0039] Figure 8 is a schematic diagram of a partial top view structure of a semiconductor device according to an embodiment of the application;

[0040] Figures 9 to 13 is a schematic diagram of a partial cross-sectional structure of a manufacturing process of a semiconductor device according to the application;

[0041] Figure 14 is a reliability test comparison diagram of a semiconductor device according to the application and a comparative device.

[0042] REFERENCE NUMERALS:

[0043] 10-substrate; 101-active region; 102-isolation region; 103-first base layer; 104-second base layer;

[0044] 11-gate structure; 111-gate; 112-side wall; 113-gate mask layer;

[0045] 12-hard mask layer; 121-silicon oxide layer; 122-silicon nitride layer; 13-insulating protective layer;

[0046] S / D-source / drain region; G-trench; G0-adjacent trench; S-semiconductor material; C-channel region. DETAILED DESCRIPTION

[0047] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings.

[0048] The terminology used in the following description merely to describe specific embodiments, and is not intended to be limiting of the present application. As used in this specification and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0049] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" or "in other embodiments" or "in still other embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment, unless otherwise indicated. Furthermore, the terms "comprises," "comprising," "includes," "including," "has," "having" and the like are intended to be open-ended terms that do not exclude additional, unrecited elements or methods. Thus, the term "comprising" is used in the sense of "including" but not necessarily "consisting of."

[0050] For the convenience of understanding the semiconductor device, the manufacturing method thereof and the electronic device provided in the embodiments of the present application, the application scenarios thereof are first introduced as follows. The semiconductor device provided in the embodiments of the present application can be widely applied to any electronic product provided with a chip, such as a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product and the like. The consumer electronic product can be a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet and the like), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone and the like. The household electronic product can be a smart door lock, a television, a smart sound box, a refrigerator, a sweeping robot and the like. The vehicle-mounted electronic product can be a vehicle-mounted navigator, a vehicle-mounted display and the like. The financial terminal product can be an automated teller machine (ATM), an electronic device for self-service operation and the like. The communication electronic product can be a server, a memory, a radar, a base station and the like. According to actual requirements, other devices electrically connected with the chip can also be arranged in the electronic device, such as a printed circuit board (PCB), an input / output device and the like. It can be understood that the specific implementation of the semiconductor device can be determined according to the actual application scenario, which is not limited herein.

[0051] The semiconductor device mentioned in the present application can be used in a logic chip, a digital logic circuit, a memory (for example, a static random access memory), a microprocessor and the like. Taking a memory logic circuit as an example, an input / output (IO) device in the memory logic circuit undertakes the role of charging and discharging channels of a storage array. With the development of a new type of memory logic circuit, the read / write speed of the IO device is continuously improved. In order to adapt to the development of the memory logic circuit, the memory logic circuit can introduce an embedded source / drain epitaxial silicon germanium technology commonly used in logic chips to improve the on-state current of the IO device, so as to achieve the purpose of improving the driving speed. The technology uses stress generated by lattice mismatch of Ge-Si to improve the hole mobility. When epitaxially growing a SiGe strain material in a source / drain region, since the lattice constant of Ge is larger than that of Si About 4%, which will generate lateral compressive stress on the channel region, so that the Si lattice constant in the channel region is reduced, the hole effective mass is reduced, thereby improving the hole mobility, which can effectively increase the IO device on-state current. However, in the epitaxial growth process, it will have an etching effect on the side wall in the semiconductor device, so that the side wall loses the insulation protection function, and then affects the service life of the semiconductor device.

[0052] The following connection Figures 1 to 6 The process of damaging the side wall of the semiconductor device is explained.

[0053] Figure 1 It is a schematic diagram of a partial top view structure of a semiconductor device. As Figure 1 shown, the semiconductor device can include an active region 101 and an isolation region 102. The active region 101 is used to make active devices, such as can be used to make source or drain. The active region 101 can be multiple, and adjacent two of the multiple active regions 101 can be isolated by the isolation region 102. The isolation region 102 can be multiple. Adjacent isolation regions 102 can be isolated by the active region 101. The active region 101 can be provided with multiple gate structures 11. The multiple gate structures 11 are spaced apart. At least one of the multiple gate structures 11, such as each gate structure 11, can be disposed in the active region 101 and can extend to the isolation region 102 adjacent to the active region 101 at both ends. The lower surface of the gate structure 11 is the channel region.

[0054] Figures 2 to 6 It is a schematic diagram of the cross-sectional structure of the manufacturing process at A-A and B-B. Figure 1

[0055] As Figure 2 shown, the gate structure 11 can include a gate 111 and a side wall 112, and a gate mask layer 113 located on the top surface of the gate 111, for example, in the orientation shown. Figure 2 As Figure 3 shown, before etching a groove in the active region 101, a hard mask layer 12 needs to be deposited on the surface of the substrate 10, such as first depositing a hard mask silicon oxide layer 121 on the entire surface of the substrate 10, i.e. on the top surface, side surface of the gate structure 11, and on the surface of the entire active region 101 and the entire isolation region 102, and then depositing a hard mask silicon nitride layer 122 on the surface of the hard mask silicon oxide layer 121. The hard mask silicon oxide layer 121 and the hard mask silicon nitride layer 122 form the hard mask layer 12. By depositing the hard mask layer 12, the gate 111 can be protected from etching during the etching process.

[0056] After depositing the hard mask layer 12, the deposition is etched using a combination of dry etching and wet etching. Figure 4 It is a schematic diagram of the structure after etching the groove G. As Figure 4 ​As shown, after etching, the desired trench G is formed in the active region 101, while the isolation region 102 is also etched to form an additional trench G0. The sidewall of the additional trench G0 extends to the bottom of the side wall 112. Then, as shown in Figure 5 , the trench G in the active region 101 is filled with semiconductor material S, such as SiGe semiconductor material, by epitaxial growth process for forming the source or drain. At this time, the additional trench G0 in the isolation region 102 is in an empty state as no other semiconductor material is filled therein. In combination with Figure 5 and Figure 6 , then the hard mask layer 12 on the side of the gate structure 11 is removed by acid washing. In this process, as the additional trench G0 in the isolation region 102 is in an empty state as no other semiconductor material is filled therein, and in the process of removing the hard mask layer 12 by acid washing, the acid solution will gradually etch the side wall 112 of the gate structure 11 from bottom to top through the sidewall of the additional trench G0, so that the bottom of the side wall 112 of the gate structure 11 is separated from the substrate 10 of the isolation region 102. In addition, the acid solution can also etch the bottom of the side wall at the junction of the active region 101 and the isolation region 102 along the etching gap between the side wall 112 and the substrate 10, thereby damaging the integrity of the side wall 112 in the active region 101.

[0057] Figure 7 is a transmission electron microscope (TEM) image of the side wall of a prior art semiconductor device. As shown in Figure 7 , the bottom of the side wall 112 is in a hollow state, thereby affecting the insulation of the gate 111 to the source and drain. In combination with Figure 1 , Figure 6 and Figure 7 , when the bottom of the side wall 112 of the isolation region 102 is separated from the substrate by the acid solution, at the junction of the active region 101 and the isolation region 102, the acid solution will penetrate into the active region 101 along the gap between the side wall 112 and the substrate 10, further etching the side wall 112 of the active region 101, so that the side wall 112 in the active region 101 will also be corroded to some extent, thereby damaging the integrity of the side wall 112 in the active region 101. If the side wall 112 in the active region 101 is separated from the substrate 10, causing the side wall 112 to be hollow, as shown by the dashed area M in Figure 7 , the damaged side wall 112 cannot effectively isolate the source and drain from the channel region C, and the gate 111 to the source and drain is prone to breakdown, causing the device to fail.

[0058] In view of this, the embodiments of the present application provide a semiconductor device. The top view structural schematic diagram of the semiconductor device can continue to refer to Figure 1 . The cross-sectional structural schematic diagram can refer to Figure 8The semiconductor device of the embodiments of the present application can be a MOSFET device, such as a P-type field effect transistor or an N-type field effect transistor.

[0059] As shown in Figure 1 and Figure 8 , the semiconductor device can include a substrate 10. The substrate 10 of the semiconductor device can be a silicon-based substrate. In addition, germanium (Ge), silicon-germanium (SiGe), silicon-carbon (SiC), silicon-germanium-carbon (SiGeC), indium-arsenide (InAs), gallium-arsenide (GaAs), indium-phosphide (InP), or other III / V compound semiconductors, including multilayer structures of these semiconductors, can also be selected according to the type of semiconductor device and the functions to be achieved.

[0060] The substrate 10 in the embodiments of the present application can also have a plurality of active regions 101 and a plurality of isolation regions 102. The adjacent active regions 101 can be separated by the isolation regions 102 to achieve insulation between the adjacent active regions 101.

[0061] The active region 101 is a region in the semiconductor device that can conduct current, and mainly includes a source region, a channel region C, and a drain region. The source region, the channel region C, and the drain region undertake the task of transmitting current when the device is working. The active region 101 can be used to make active devices, such as source and drain. Among them, the source region and the drain region are collectively referred to as the source / drain region S / D.

[0062] The source / drain region S / D is provided with a trench G for the part of the source or drain formed thereby. The trench G of the active region 101 can be filled with semiconductor material S to form the source or drain. Continuing to refer to Figure 8 In the embodiments of the present application, the trench G can protrude towards the channel region C, so that the semiconductor material S filled in the trench G can press the channel region C, so that the lattice constant of the channel region C is reduced, and the mobility of the holes is improved. Exemplarily, the inner width of the trench G can be greater than the opening width of the trench G. Among them, the width direction of the trench G is the direction along which the trench G is Figure 8 the x direction shown in , that is, the direction perpendicular to the length direction of the gate 111 in the plane parallel to the surface of the substrate 10. In an embodiment, the inner width of the trench G is greater than the opening size of the trench G, and also greater than the bottom width of the trench G, as shown in Figure 8 in , the side wall of the trench G is approximately in the middle position and protrudes towards the channel region C. In other embodiments, the side wall of the trench G can also protrude towards the channel region C at other positions during specific implementation, and the side wall of the trench G can also have multiple positions protruding towards the channel region C. Exemplarily, the trench G in the embodiments of the present application can be a sigma trench G, and the cross section of the trench G in the direction perpendicular to the surface of the semiconductor substrate 10 is a hexagon. The sigma trench G can help to enhance the compressive stress of the subsequently formed source / drain on the channel region C, so as to further improve the corresponding speed of the semiconductor device.

[0063] The trench G is filled with a semiconductor material S, and the lattice constant of the semiconductor material S is greater than that of the substrate 10 corresponding to the active region 101. The semiconductor material S filled in the trench G can generate a lateral compressive stress to squeeze the channel region C, so as to reduce the lattice constant of the channel region C, thereby improving the mobility of the holes. Exemplarily, the substrate 10 can be silicon, and the semiconductor material S filled in the trench G can be an alloy semiconductor material, for example, a germanium-silicon (SiGe) material. Of course, the substrate 10 and the semiconductor material S filled in the trench G can also be other semiconductor materials, for example, the semiconductor material S filled in the trench G can also be a silicon carbide (SiC), a silicon phosphide (SiP), or the like.

[0064] In the active region 101, a channel region C is arranged between the source region and the drain region. A gate structure 11 can be arranged on the surface of the channel region C. The channel region C is a thin semiconductor layer between the source region and the drain region in the field effect transistor, and the current flowing therein is controlled by the potential of the gate structure 11. When a suitable voltage or current is applied, the channel region C becomes the main conduction path of the electrons or holes.

[0065] Referring to Figure 1 and Figure 8 At least one of the plurality of gate structures 11, for example, each gate structure 11 is arranged on the surface of the substrate 10 corresponding to the active region 101. A plurality of gate structures 11 can be arranged in each active region 101. The source and the drain are respectively arranged at the two sides of each gate structure 11. The channel region C is arranged below each gate structure 11. In order to fully utilize the channel region C, each gate structure 11 can be arranged along the length direction of one channel region C, completely covering the channel region C of the active region 101, and the end portions at the two ends of each gate structure 11 can extend to the isolation region 102 connected with the active region 101.

[0066] As shown in Figure 8 At least one of the plurality of gate structures 11, for example, each gate structure 11 includes a gate 111 and a side wall 112 arranged on the side surface of the gate 111. The gate 111 can be a polysilicon or a metal gate. A gate dielectric layer (not shown in the figure) can be arranged between the gate 111 and the substrate 10, and the gate dielectric layer can be silicon oxide or silicon oxynitride.

[0067] The side wall 112 can cover the entire side surface of the gate 111 on the side surface of the gate 111. By arranging the side wall 112 on the side surface of the gate 111, the distance between the ion implantation and the channel region C can be controlled by the side wall 112 during the light doping drain process, so as to reduce the influence of the doping on the channel region C, thereby reducing the electric field between the source and the drain. In an embodiment, the side wall 112 can be nitride, for example, silicon nitride.

[0068] In the active region 101, the bottom of the side wall 112, i.e. the side close to the substrate 10, is connected to the substrate 10. The presence of the side wall 112 can prevent the channel region C under the gate 111 from being broken down with the source and drain on both sides of the gate 111, thereby improving the reliability of the semiconductor device.

[0069] In the isolation region 102, in order to prevent the isolation region 102 from being damaged in the subsequent acid washing process after epitaxial growth of the semiconductor material, an insulating protective layer 13 can be arranged on the surface of the substrate 10 corresponding to the isolation region 102. The insulating protective layer 13 can cover the entire surface of the substrate 10 corresponding to the isolation region 102.

[0070] It can be understood that, since the active region 101 needs to be etched to form a groove according to requirements, the surface of the substrate 10 corresponding to the active region 101 is not provided with the insulating protective layer 13.

[0071] Since the isolation region 102 is protected by the insulating protective layer 13, in the obtained semiconductor device, the gate structure 11 is located at the end portion of the isolation region 102, the bottom of the side wall 112 of the gate structure 11 is in a connected state with the substrate 10, and the side surface of the insulating protective layer 13 is connected to the side surface of the side wall to protect the side wall 112 from being damaged.

[0072] In the semiconductor device of the embodiment of the present application, the substrate 10 corresponding to the isolation region 102 is not formed with a groove G. In the isolation region 102, the surface of the substrate 10 adjacent to the insulating protective layer 13 is arranged in a coplanar manner with the surface of the substrate adjacent to the gate structure 11.

[0073] By arranging the insulating protective layer 13 on the surface of the isolation region 102, after epitaxial growth of the source and drain, the substrate 10 corresponding to the isolation region 102 and the side wall 112 can be prevented from being corroded in the subsequent acid washing process, so as to ensure that the isolation function of the side wall 112 will not be lost.

[0074] In the embodiment of the present application, the insulating protective layer 13 can be an inorganic protective layer or an organic polymer layer. The insulating protective layer 13 can be formed by a selective deposition method, and therefore, the material for forming the insulating protective layer 13 can be a material capable of realizing selective deposition.

[0075] As shown in FIG. 1, the semiconductor device includes a substrate 10, a gate structure 11, a source 12 and a drain 13. Figure 8As shown, the substrate 10 of the active region 101 includes a first base layer 103, and the source or the drain is disposed on the first base layer 103, and the surface of the first base layer 103 is not provided with an insulating protective layer. The substrate 10 of the isolation region 102 includes a first base layer 103 and a second base layer 104 which are stacked. The second base layer 104 is an insulating layer. The gate structure 11 extending to the isolation region 102 is connected to the second base layer 104, and the insulating protective layer 13 is disposed on the surface of the second base layer 104. Among them, the first base layer 103 of the active region and the first base layer 103 of the isolation region 102 can be an integrated structure formed by the same material. As an exemplary illustration, the first base layer 103 can be silicon, and the second base layer 104 can be silicon dioxide. Therefore, the insulating protective layer 13 in the embodiment of the present application can be selected as a film layer that can be deposited on the second base layer 104, and is a film layer that cannot be deposited on the first base layer 103.

[0076] Among them, in an embodiment, the substrate 10 corresponding to the active region 101 can be a silicon-based substrate, such as an epitaxial silicon substrate. The isolation region 102 can be a shallow trench isolation (STI) region. The STI region is an insulating region, such as the substrate 10 corresponding to the region of the STI region can be silicon oxide, and when the STI is made, processing can be performed on the silicon substrate, such as forming by slotting and filling silicon oxide. When depositing the insulating protective layer 13, a material that can be deposited on the surface of the silicon oxide and not deposited on the surface of the silicon needs to be selected. Among them, when the substrate of the active region is silicon and the surface layer material of the substrate of the isolation region is silicon oxide, the selection of the deposition material can be selected according to the different reaction characteristics of silicon and silicon oxide. For example, a precursor capable of bonding with the chemical bond on the surface of the silicon oxide, such as an organic metal precursor, etc., can be introduced into the reaction chamber of the deposition equipment, and the insulating protective layer can be obtained after reaction.

[0077] Since the etching of the STI region occurs in the silicon etching and the acid washing process after the growth, the material of the insulating protective layer 13 is selected from a material capable of resisting the silicon etching and the acid washing process.

[0078] Exemplarily, when the insulating protective layer 13 is an inorganic protective layer, the insulating protective layer 13 can be selected from at least one of aluminum oxide, titanium oxide, zinc oxide, thallium oxide, silicon nitride, silicon oxide, or silicon carbide. When the insulating protective layer 13 is a polymer layer, the insulating protective layer 13 can be selected from at least one of trimethoxysilane or perfluorooctyltriethoxysilane.

[0079] In this embodiment, the thickness of the insulating protective layer 13 can be 1-10 nm. If the thickness of the insulating protective layer 13 is too low, it is difficult to form an effective protective effect. If the thickness of the insulating protective layer 13 is too high, it will increase the thickness of the isolation region 102. For example, the thickness of the insulating protective layer 13 can be any two values ​​between 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm.

[0080] For the same technical purpose, embodiments of this application also provide an electronic device. The electronic device provided in this application embodiment may include: a circuit board and a semiconductor device according to embodiments of this application. The semiconductor device is disposed on the circuit board and electrically connected to the circuit board. Because the semiconductor device of this application embodiment has high reliability, the electronic device including the semiconductor device of this application embodiment also has high reliability.

[0081] In this application, the electronic devices can be mobile phones, tablets, laptops, personal computers, personal digital assistants, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, home electronics, in-vehicle electronics, financial terminal products, and communication electronic products. Home electronics can be smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics can be in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can be automated teller machines (ATMs), self-service electronic devices, etc. Communication electronic products can be servers, storage devices, radar, base stations, and other communication equipment.

[0082] Based on the same technical objective, embodiments of this application also provide a method for fabricating a semiconductor device. The method for fabricating a semiconductor device provided in this application embodiment may include the following steps S1-S6. The following will be discussed in conjunction with the appendix... Figures 9 to 13 The fabrication process of the semiconductor device described in this application is explained in detail.

[0083] Step S1, as follows Figure 9 As shown, a substrate 10 is provided, which has an active region 101 and an isolation region 102. The isolation region 102 is disposed between adjacent active regions 101. A gate structure 11 is provided on the surface of the substrate 10. The gate structure 11 includes a gate 111, a gate mask layer 113, and sidewalls 112. The gate mask layer 113 is disposed on the top surface of the gate 111, and the sidewalls 112 are disposed on the side surfaces of the gate 111 and the gate mask layer 113.

[0084] A gate mask layer 113 is disposed on the top surface of the gate 111, and is used to protect the gate 111 from being damaged in subsequent etching processes. The gate mask layer 113 can be nitride, such as silicon nitride.

[0085] Referring to Figure 9 The substrate 10 is a semiconductor substrate. The semiconductor substrate can be selected from silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-carbon (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and can also be a multilayer structure formed by the above semiconductor materials, etc. In the embodiments of the present application, the substrate 10 is a silicon substrate.

[0086] The active regions 101 of the substrate 10 can be multiple, and the isolation regions 102 can also be multiple. Among the multiple active regions 101, two adjacent active regions 101 can be isolated by an isolation region 102 to prevent short-circuit breakdown between adjacent active regions 101.

[0087] The active region 101 of the substrate 10 includes a channel region C and a source / drain region S / D. The channel region C is used to form a channel region C, and the source / drain region S / D is used to form a source or a drain. The gate structure 11 is disposed on the substrate 10 corresponding to the position of the channel region C. Each channel region C can be provided with a source / drain region S / D on each side. Among the source / drain regions S / D on both sides of the channel region C, one side of the source / drain region S / D is used to form a source, and the other side of the source / drain region S / D is used to form a drain.

[0088] The isolation region 102 can be a shallow trench isolation (STI) region. The STI region is an insulating region, such as the substrate 10 corresponding to the region of the STI region can be silicon oxide, and during the fabrication of the STI, processing can be performed on the silicon substrate 10, such as by forming a groove and filling silicon oxide.

[0089] The gate structure 11 includes a gate 111 and a side wall 112, and can also include a gate dielectric layer (not shown in the figure) disposed between the gate 111 and the substrate 10.

[0090] In the process of forming the source and drain, ions can be implanted into the source and drain region of the substrate 10 by a lightly doped drain (LDD) process. By providing the side wall 112 on the side of the gate 111, the distance between the ion implantation and the channel region C can be controlled in the LDD process, and the influence of the doping on the channel region C can be reduced, so as to reduce the electric field between the source and the drain and inhibit the short channel effect. Exemplarily, the LDD process can include ion implantation, photoresist ashing, cleaning and the like. Due to the oxidation effect of the photoresist ashing process, a natural oxide layer with a certain thickness can be formed on the surface of the semiconductor substrate 10. The flame-retardant oxide layer can be removed by using a hydrofluoric acid solution.

[0091] With reference to the above description, the following steps are performed to form the semiconductor device. Figure 9 In the process of forming the gate structure 11, such as the deposition and etching process of the gate 111 and the side wall 112, the top of the gate 111 can be reserved with a certain thickness of the gate mask layer 113 as a sacrificial layer to protect the gate 111 in the subsequent process. The gate mask layer 113 can be a silicon nitride layer 122.

[0092] Step S2, as shown in the figure, selective deposition is performed on the surface of the substrate 10 to form an insulating protective layer 13 on the surface of the isolation region 102. Figure 10

[0093] When the deposition of the insulating protective layer 13 is performed, a material that can be deposited on the surface of silicon oxide but not on the surface of silicon needs to be selected. The insulating protective layer 13 can be an inorganic protective layer or an organic polymer layer. The formation of the insulating protective layer 13 can be formed by a selective deposition method, and therefore, the material of the insulating protective layer 13 can be a material that can achieve selective deposition. In addition, since the insulating protective layer 13 needs to resist the corrosion of phosphoric acid in the subsequent process, the material of the insulating protective layer 13 is a material that can resist the corrosion of phosphoric acid. The thickness of the insulating protective layer 13 obtained by selective deposition can be 1-10 nm.

[0094] Exemplarily, when the insulating protective layer 13 is an inorganic protective layer, the insulating protective layer 13 can be selected from at least one of aluminum oxide, titanium oxide, zinc oxide, thallium oxide, silicon nitride, silicon oxide or silicon carbide. When the insulating protective layer 13 is a polymer layer, the insulating protective layer 13 can be selected from at least one of trimethoxysilane or perfluorooctyltriethoxysilane.

[0095] Step S3, as shown in the figure, a hard mask layer 12 is formed on the surface of the active region 101, the surface of the gate structure 11 and the surface of the insulating protective layer 13. Figure 11

[0096] As shown in the figure, the hard mask layer 12 is used as a mask to perform the deposition and etching process of the gate electrode 111 and the side wall 112. Figure 11 ​​As shown, a silicon oxide layer 121 is first deposited on the entire surface of the substrate 10 according to the surface topography of the substrate 10, and then a silicon nitride layer 122 is deposited on the surface of the silicon oxide. The silicon oxide layer 121 and the silicon nitride layer 122 together serve as the hard mask layer 12. That is, a silicon oxide layer 121 and a silicon nitride layer 122 are deposited on the surface of the source / drain region S / D, the side surface of the gate structure 11, the top surface of the gate structure 11, and the surface of the insulating protective layer 13, serving as the hard mask layer 12 to protect the gate 111 in subsequent processes.

[0097] Exemplarily, when depositing the silicon oxide, the silicon oxide layer 121 in the hard mask layer 12 can be deposited by a chemical vapor deposition (CVD) process, serving as a buffer layer of the side wall 112 and the gate mask layer 113. The silicon nitride layer 122 in the hard mask layer 12 is deposited by a furnace tube process, covering the surface of the non-source / drain region S / D domain in the process of epitaxial growth, and realizing epitaxial selective growth.

[0098] The deposition thickness of the silicon oxide layer 121 is 1-6 nm. Exemplarily, the thickness of the silicon oxide layer 121 can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, or 6 nm or any value between any two of the above values. The deposition thickness of the silicon nitride layer 122 can be 5-30 nm. Exemplarily, the thickness of the silicon nitride layer 122 can be 5 nm, 6 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 22 nm, 24 nm, 25 nm, 28 nm, or 30 nm or any value between any two of the above values.

[0099] Step S4, as shown in Figure 12 As shown, the trench G etching: etching to remove the hard mask layer 12 on the surface of the active region 101 and the hard mask layer 12 on the top surface of the gate structure 11, and forming a trench G in the active region 101.

[0100] Referring to Figure 12 In this step, the hard mask layer 12 on the top surface of the gate structure 11 and the hard mask layer 12 on the surface of the substrate 10 can be etched and removed by a dry etching process, and the hard mask layer 12 on the surface of the side wall 112 is reserved. The hard mask layer 12 on the surface of the substrate 10 is etched and removed to expose the substrate 10, so as to realize etching processing of the substrate 10. The dry etching can be plasma etching. The gas used in the plasma etching can be chlorine, hydrogen chloride, hydrogen bromide, carbon tetrafluoride, or nitrogen trifluoride, etc. When the above-mentioned gas is used for dry etching, the etching time can be 50-150 s.

[0101] After the hard mask layer 12 on the surface of the substrate 10 is removed by etching, a groove G can be formed in the source / drain region S / D by a combination of dry etching and wet etching. For example, a groove can be first formed on the substrate 10 by dry etching, and then the substrate 10 after the groove is formed can be further etched by a wet etching process. The etching solution used in the wet etching can be tetramethylammonium hydroxide, and the etching time can be 100-400s.

[0102] Since the etching of silicon by tetramethylammonium hydroxide is anisotropic, after the silicon substrate 10 is etched by tetramethylammonium hydroxide, a groove G with a side wall protruding towards the channel direction can be obtained, such as a sigma groove.

[0103] Step S5, epitaxial growth: as shown in Figure 13 , a semiconductor material S is epitaxially grown in the groove G to form a source or drain.

[0104] After the groove G is etched, the surface of the groove G will be oxidized to form an oxide layer, so before epitaxial growth, the oxide layer on the inner wall of the groove G can be removed. For example, an in-situ cleaning process for epitaxy can be used to clean the inner wall of the groove G. For example, hydrogen fluoride (HF) and ammonia (NH3) can be used to treat the inner wall of the groove G.

[0105] After cleaning, as shown in Figure 13 , a semiconductor material S is epitaxially grown in the groove G, and the lattice constant of the semiconductor material S is greater than the lattice constant of the corresponding semiconductor material of the substrate 10. In this way, the semiconductor material S filled in the groove G can generate a lateral compressive stress to squeeze the channel region C, so that the lattice constant of the channel region C becomes smaller, thereby improving the hole mobility.

[0106] For example, the material of the substrate 10 can be silicon, and the semiconductor material S filled in the groove G can be an alloy semiconductor material, such as silicon germanium (SiGe), silicon carbide (SiC), silicon phosphide (SiP), etc. Among them, the semiconductor material S in the groove G can fill the groove G and protrude from the surface of the substrate 10.

[0107] For example, in the epitaxial growth, the silicon source can use silane or silicon dichloride, etc., and the germanium source can use germane (GeH4) for in-situ growth. During in-situ growth, impurity gas such as borane (B2H6) can be doped to introduce P-type doping.

[0108] Step S6, as shown in Figure 8 and Figure 13 , the hard mask layer 12 on the side of the side wall 112 is etched and removed.

[0109] As shown in Figure 8 and Figure 13As shown, after epitaxial growth of semiconductor material S inside and outside trench G, the hard mask layer 12 on the surface of sidewall 112 needs to be removed. During the removal of the hard mask layer 12, phosphoric acid solution and hydrochloric acid solution are required. For example, phosphoric acid solution can be used to etch and remove the silicon nitride layer 122 in the hard mask layer 12, and hydrochloric acid solution can be used to etch and remove the silicon oxide layer 121 in the hard mask layer 12.

[0110] The etching selectivity ratio of the insulating protective layer 13 to the hard mask layer 12 is greater than or equal to 18:1. Exemplarily, the etching selectivity ratio can be 18:1, 19:1, 20:1, 21:1, or a larger ratio. Therefore, during the process, the hard mask layer 12 is more easily etched, while the insulating protective layer 13 is etched at a lower rate. Thus, even after the hard mask layer 12 has been completely etched, the insulating protective layer 13 still provides protection in the STI region.

[0111] In addition to removing the hard mask layer of the sidewalls, the source and drain regions can be doped with heavy ions to form the source or drain with the required performance.

[0112] In the fabrication method of this application embodiment, during the etching process to remove the hard mask layer 12 of the sidewall 112, in the STI region, because a protective layer is provided on the surface of the substrate 10 in this region, and this protective layer can resist the corrosion of phosphoric acid and hydrochloric acid, the bottom of the sidewall 112 corresponding to the STI region will not be damaged during this process, and a dense connection will still exist between it and the substrate 10, without voids. The etching solution will also not corrode the sidewall 112 of the source / drain region S / D through this region. Therefore, the semiconductor device obtained using the fabrication method of this application embodiment has more stable performance.

[0113] To demonstrate the technical effectiveness of the semiconductor device of this application, respectively using Figures 8-13 The method of preparation of this application and Figures 2 to 6 The existing fabrication method shown is used to obtain experimental samples. Different samples were tested. The test results are as follows. Figure 14 As shown. (Refer to...) Figure 14 The breakdown voltage of the semiconductor device in this application embodiment is significantly improved. Under the same breakdown voltage, the probability of the semiconductor device in this application embodiment being broken down is greatly reduced.

[0114] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate having a plurality of active regions and a plurality of isolation regions, the isolation regions being arranged between adjacent active regions and the active regions being arranged between adjacent isolation regions; at least one of the plurality of active regions is provided with a trench filled with a semiconductor material for forming a source or a drain; a plurality of gate structures, at least one of the plurality of gate structures is arranged in one of the active regions and two end portions of the gate structure extend to the isolation regions adjacent to the active region, respectively; at least one of the plurality of gate structures comprises a gate and a sidewall arranged on a side surface of the gate; a surface of the plurality of isolation regions is provided with an insulating protective layer, the insulating protective layer covers a remaining surface of the substrate other than the gate structure in the isolation region, and the sidewall extending to the isolation region is connected to the substrate.

2. The semiconductor device according to claim 1, wherein An etching rate of the insulating protective layer is lower than an etching rate of the substrate.

3. The semiconductor device of claim 1, wherein The substrate of the active region comprises a first base layer, the source or the drain is arranged in the first base layer, and a surface of the first base layer is not provided with the insulating protective layer; the substrate of the isolation region comprises a first base layer and a second base layer arranged in a stack, the second base layer is an insulating layer, the gate structure extending to the isolation region is connected to the second base layer, and the insulating protective layer is arranged on a surface of the second base layer.

4. The semiconductor device according to claim 3, wherein The first base layer is silicon, and the second base layer is silicon dioxide.

5. The semiconductor device of claim 3, wherein The insulating protective layer is a film layer capable of being deposited on the second base layer, and the insulating protective layer is a film layer incapable of being deposited on the first base layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein In the isolation region, a surface of the substrate adjacent to the insulating protective layer is arranged coplanar with a surface of the substrate adjacent to the gate structure.

7. The semiconductor device according to any one of claims 1 to 5, wherein The insulating protective layer is an inorganic protective layer or an organic polymer layer.

8. The semiconductor device of claim 7, wherein, The inorganic protective layer comprises one of aluminum oxide, titanium oxide, zinc oxide, thallium oxide, silicon nitride, silicon oxide, or silicon carbide.

9. The semiconductor device of claim 7, wherein, The organic polymer layer comprises one of trimethoxysilane or perfluorooctyltriethoxysilane.

10. The semiconductor device according to any one of claims 1 to 5, wherein The thickness of the insulating protective layer is 1-10 nm.

11. An electronic device, comprising: The semiconductor device comprises: a circuit board and the semiconductor device according to any one of claims 1-10, the semiconductor device is arranged on the circuit board.

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