Pressure sensor chip
By employing SOI substrates and low-resistivity silicon substrates in MEMS pressure sensors, and using conductive silicon pillars and insulating isolation rings instead of copper plating processes, the problems of high cost and copper ion contamination in traditional pressure sensors are solved, achieving a lower-cost and higher-safety manufacturing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-07
- Publication Date
- 2026-04-03
AI Technical Summary
Traditional MEMS pressure sensors are expensive to manufacture and pose a risk of copper ion contamination. Furthermore, it is difficult to guarantee the uniformity and filling efficiency of electroplating in large-size or high aspect ratio TSV holes, leading to a decrease in yield.
Using SOI substrate and low-resistivity silicon substrate structure, conductive path is realized through bonding structure layer. Conductive silicon pillars are used to replace the traditional copper electroplating process. Combined with insulating isolation ring and bonding pillars, a pressure sensor is formed, eliminating the electroplating process, reducing the use of chemical reagents and wastewater treatment costs, and avoiding copper ion pollution.
It reduces the manufacturing cost of pressure sensors, improves production safety and yield, simplifies the manufacturing process, reduces the use of chemical reagents and wastewater treatment costs, and avoids the risk of copper ion contamination.
Smart Images
Figure CN224081097U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing, and more specifically, to a pressure sensor chip. Background Technology
[0002] In the field of MEMS pressure sensors, traditional technology commonly employs the Wheatstone bridge principle to detect pressure signals. Specifically, four piezoresistors are arranged in a specific layout at the edge of a strain gauge. When external pressure causes deformation of the strain gauge, the resistance of the piezoresistors changes accordingly, disrupting the bridge balance and outputting an electrical signal proportional to the pressure. To achieve efficient integration of the sensor with peripheral circuitry, traditional pressure sensor structures often use copper plating through transilluminated vias (TSVs) to form conductive paths, leading the electrodes of the sensing element to the wafer surface. However, this structure has the following drawbacks: Firstly, the copper plating process in this structure is complex, requiring multiple chemical treatments, which not only increases manufacturing costs but also introduces the risk of copper ion contamination. Secondly, for large-sized or high aspect ratio TSVs, plating uniformity and filling efficiency are difficult to guarantee, leading to a decrease in yield, further increasing production costs and extending the production cycle. Utility Model Content
[0003] The purpose of this invention is to provide a pressure sensor chip that can reduce the manufacturing cost of pressure sensors and improve their safety.
[0004] To achieve the above objectives, this utility model provides the following technical solution: a pressure sensor chip, comprising:
[0005] A functional structural component includes an SOI substrate and a Wheatstone bridge circuit formed on the SOI substrate, wherein the SOI substrate includes a sensitive thin film layer and the Wheatstone bridge circuit is formed on the sensitive thin film layer;
[0006] A cover plate, located on one side of the functional structure, includes a low-resistivity silicon substrate and an insulating isolation ring formed within the low-resistivity silicon substrate. The low-resistivity silicon substrate has conductive silicon pillars separated by the insulating isolation ring, the conductive silicon pillars serving as conductive pathways. A conductive pad is formed on the side of the cover plate away from the functional structure, the conductive pad being electrically connected to the conductive silicon pillars.
[0007] A bonding structure layer is located between the functional structural component and the cover plate. A bonding pillar is provided in the bonding structure layer, and the two ends of the bonding pillar are electrically connected to the Huisheng Bridge circuit and the conductive silicon pillar, respectively.
[0008] Furthermore, the cross-sectional shape of the conductive silicon pillar is square, circular, or elliptical.
[0009] Furthermore, the insulating isolation ring includes a polysilicon pillar and an insulating dielectric layer surrounding the polysilicon pillar.
[0010] Furthermore, an isolation hole is formed in the low-resistivity silicon substrate, the isolation hole penetrates the low-resistivity silicon substrate, and the insulating isolation ring is filled with an insulating dielectric material and a polycrystalline silicon material to form the insulating isolation ring.
[0011] Furthermore, the thickness of the low-resistivity silicon substrate is greater than 300 μm.
[0012] Furthermore, an insulating layer is formed on one side of the low-resistivity silicon substrate on which the conductive pad is formed, and an opening is formed on the insulating layer corresponding to the conductive silicon pillar. The conductive pad fills the opening and extends to the upper surface of the insulating layer.
[0013] Furthermore, the insulating layer is formed of silicon dioxide or silicon nitride.
[0014] Furthermore, the thickness of the suspended portion in the sensitive thin film layer can be set between 5-100 μm, and the length and width dimensions can be set between 5-200 μm.
[0015] Furthermore, an overflow groove is formed within the bonding structure layer, and the overflow groove is filled with an aluminum-germanium eutectic material to form a bonding pillar.
[0016] Furthermore, a first clearance cavity is formed through the bonding structure layer, and a second clearance cavity is formed on the side wall of the cover plate facing the first clearance cavity. The first clearance cavity is disposed corresponding to the second clearance cavity, and the first clearance cavity and the second clearance cavity are located above the Huistone bridge circuit.
[0017] The beneficial effects of this utility model are as follows: This application achieves the bonding of functional structural components and cover plates through a bonding structure layer to form a pressure sensor. The cover plate uses a low-resistivity silicon substrate as a support structure, and conductive silicon pillars are formed within the low-resistivity silicon substrate by using insulating isolation rings. These conductive silicon pillars serve as conductive paths, replacing the conductive paths formed by the traditional copper electroplating process. This type of pressure sensor eliminates the electroplating process during manufacturing, reduces the use of chemical reagents and wastewater treatment costs, avoids the risk of copper ion contamination, helps reduce the manufacturing cost of pressure sensors, and improves production safety.
[0018] The above description is only an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, the preferred embodiments of this utility model are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0019] Figure 1This is a cross-sectional view of a pressure sensor chip according to an embodiment of this application;
[0020] Figures 2 to 4 This is a schematic diagram of the pressure sensor chip fabrication process implemented in an embodiment of this application.
[0021] In the picture:
[0022] 10-Functional structural component; 11-SOI substrate; 111-Base silicon; 112-Sensitive thin film layer; 113-Wafer buried oxide layer; 114-Back cavity; 12-Westbridge circuit; 121-Varistor; 122-Varistor metal interconnect;
[0023] 20-Cover plate; 21-Low-resistivity silicon substrate; 211-Conductive silicon pillar; 22-Insulating isolation ring; 221-Polycrystalline silicon pillar; 222-Insulating dielectric layer; 23-Conductive pad; 24-Isolation hole; 25-Insulating layer; 26-Opening; 27-Second clearance cavity;
[0024] 30-Bonding structure layer; 301-First barrier layer; 302-Second barrier layer; 3021-Silicon nitride layer; 3022-Silicon dioxide layer; 31-Bonding pillar; 311-Germanium section; 312-Aluminum section; 32-Overflow groove; 321-First overflow groove; 322-Second overflow groove; 33-First clearance cavity; 34-Metal interconnect groove. Detailed Implementation
[0025] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.
[0026] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0027] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0028] Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.
[0029] Please see Figure 1 The pressure sensor chip shown in a preferred embodiment of this application includes a functional structural component 10, a cover plate 20, and a bonding structure layer 30. For ease of description, this embodiment uses... Figure 1 Set the bottom and top positions for the reference view.
[0030] The functional structure 10 includes an SOI substrate 11 and a Wheatstone bridge circuit 12 formed on the SOI substrate 11. The SOI substrate 11 includes a base 111, a sensitive thin film layer 112 located on the base 111, and a wafer buried oxide layer 113 located between the base 111 and the sensitive thin film layer 112. A back cavity 114 is formed on the base 111 and the wafer buried oxide layer 113 of the SOI substrate 11, and the back cavity 114 is located below the floating portion (not labeled) in the sensitive thin film layer 112. The length and width dimensions of the floating portion in the sensitive thin film layer 112 are set according to the device range, and the typical thickness value can be set between 5-100 μm, and the typical length and width dimensions can be set between 5-200 μm, in order to balance stress transfer efficiency and structural stability. The Wheatstone bridge circuit 12 is formed on the sensitive thin film layer 112. The Wheatstone bridge circuit 12 includes four mutually matched varistors 121 (defined by ion implantation process). The varistors 121 are electrically connected to each other by varistor metal interconnects 122 deposited by magnetron sputtering.
[0031] The cover plate 20 is located above the functional structure 10. The cover plate 20 includes a low-resistivity silicon substrate 21 and an insulating isolation ring 22 formed within the low-resistivity silicon substrate 21. The low-resistivity silicon substrate 21 has conductive silicon pillars 211 formed by the insulating isolation ring 22, which serve as conductive pathways. A conductive pad 23 is formed on the upper side of the cover plate 20, which is the side of the cover plate 20 furthest from the functional structure 10. The conductive pad 23 is electrically connected to the conductive silicon pillars 211. The conductive silicon pillars 211 and the conductive pad 23 provide an external electrical access path.
[0032] A bonding structure layer 30 is located between the functional structural component 10 and the cover plate 20. Bonding pillars 31 are used to bond the functional structural component 10 and the cover plate 20, serving as an intermediate medium to ensure signal transmission. Bonding pillars 31 are disposed within the bonding structure layer 30, with their two ends electrically connected to the Huisheng Bridge circuit 12 and the conductive silicon pillar 211, respectively. The bonding structure layer 30 is used to bond the functional structural component 10 and the cover plate 20 to form a pressure sensor. The cover plate 20 uses a low-resistivity silicon substrate 21 as a support structure. Insulating isolation rings 22 are used to separate and form conductive silicon pillars 211 within the low-resistivity silicon substrate 21. These conductive silicon pillars 211 serve as conductive paths, replacing the traditional conductive paths formed by copper electroplating. This pressure sensor structure eliminates the need for electroplating during manufacturing, reducing the use of chemical reagents and wastewater treatment costs, avoiding the risk of copper ion contamination, and contributing to cost reduction and improved safety.
[0033] It should be noted that, in this embodiment, by using a low-resistivity silicon material as the support structure, its low-resistivity characteristics can be utilized to ensure the conductivity of the conductive silicon pillar 211 and reduce signal transmission loss. In this embodiment, the thickness of the low-resistivity silicon substrate 21 is greater than 300 μm. This setting allows the low-resistivity silicon substrate 21 to provide sufficient mechanical support and prevents the stress generated during device flip-chip bonding from having a detrimental effect on its structure.
[0034] In one embodiment, the conductive silicon pillar 211 has a square, circular, or elliptical cross-sectional shape to reduce stress concentration, improve its fracture resistance, adapt to different precision etching processes, and facilitate parameter control during batch processing, thereby improving yield. The insulating isolation ring 22 can be made of commonly used insulating materials, such as silicon dioxide or silicon nitride. In this embodiment, the insulating isolation ring 22 includes a polycrystalline silicon pillar 221 made of polycrystalline silicon and an insulating dielectric layer 222 surrounding the polycrystalline silicon pillar 221. The insulating dielectric layer 222 is made of silicon dioxide. The insulating dielectric layer 222 provides basic insulation, while the polycrystalline silicon pillar 221 acts as a structural support to enhance the mechanical strength of the isolation ring and improve the stress problem caused by only thermo-oxygen filling. In detail, an annular isolation hole 24 is formed in the low-resistivity silicon substrate 21, and the isolation hole 24 penetrates the low-resistivity silicon substrate 21. The insulating isolation ring 22 is filled with insulating dielectric material and polycrystalline silicon material to form the insulating isolation ring 22. In this way, it is ensured that the pressure sensor is connected to the external circuit only through the conductive pad 23, so as to achieve accurate signal transmission.
[0035] An insulating layer 25 is formed on one side of the low-resistivity silicon substrate 21 where a conductive pad 23 is formed. An opening 26 is formed on the insulating layer 25 corresponding to a conductive silicon pillar 211. The conductive pad 23 fills the opening 26 and extends to the upper surface of the insulating layer 25. The insulating layer 25 can be made of conventional materials, such as silicon nitride or silicon dioxide. In a preferred embodiment, the insulating layer 25 is formed of silicon dioxide. Because silicon dioxide is highly compatible with silicon processes, a dense thin film can be formed through thermal oxidation or deposition. Furthermore, due to the excellent insulating properties (high breakdown voltage) of silicon dioxide, the long-term reliability of the pressure sensor is ensured.
[0036] In one embodiment, an overflow groove 32 is formed within the bonding structure layer 30, and the overflow groove 32 is filled with aluminum-germanium eutectic material to form bonding pillars 31. The width of the overflow groove 32 must be greater than the width of the bonding pillars 31 to ensure that when eutectic bonding occurs within the overflow groove 32, the metal material does not overflow to the outside, such as overflowing into the first clearance cavity 33 (described later). The first clearance cavity 33 is formed through the bonding structure layer 30, and a second clearance cavity 27 is formed on the side wall of the cover plate 20 facing the first clearance cavity 33. The first clearance cavity 33 is disposed corresponding to the second clearance cavity 27, and the first clearance cavity 33 and the second clearance cavity 27 are located above the Wheatstone bridge circuit 12. The first clearance cavity 33 and the second clearance cavity 27 provide buffer space for the Huistone bridge circuit 12, and at the same time prevent the bonding surface of the cover plate 20 and the bonding surface of the functional structural component 10 from failing to bond due to surface film protrusion during the bonding process. Specifically, the first clearance cavity 33 and the second clearance cavity 27 together ensure that the low-resistivity silicon substrate 21 and the SOI substrate 11 can make full contact during metal bonding, and avoid the metal connecting the Huistone bridge circuit 12 and the film of the cover plate 20 from failing to bond due to local protrusion. The back cavity 114 allows the sensitive thin film layer 112 to come into contact with the external environment (external pressure causes the sensitive thin film layer 112 to deform, thereby causing the varistor 121 on the sensitive thin film layer 112 to deform, and the change in resistance causes the change in electrical signal).
[0037] To facilitate those skilled in the art in obtaining the pressure sensor of this embodiment, this application also provides a method for manufacturing the pressure sensor, which is as follows:
[0038] S1: Prepare the pre-treatment structure of cover plate 20. Please refer to... Figure 2 , specifically:
[0039] S11: Provide a first wafer, which is a low-resistivity silicon substrate 21;
[0040] S12: Isolation holes 24 are formed by etching from the bottom surface of the low-resistivity silicon substrate 21 towards the top surface; in actual processes, the low-resistivity silicon substrate 21 does not have a fixed bottom surface and top surface, and isolation holes can be formed on either its bottom or top surface. For ease of description, this application uses... Figure 2 The direction shown is based on the bottom surface and is described using an isolation hole 24 formed by etching.
[0041] S13: First, an insulating dielectric material such as silicon dioxide is deposited in the isolation hole 24 to form an insulating dielectric layer 222 in the isolation hole 24. Then, polysilicon is deposited and grown to completely fill the isolation hole 24 to form a polysilicon pillar 221. After the isolation hole 24 is completely filled, the polysilicon and silicon dioxide on the wafer surface are removed by a wet etching process. The polysilicon pillar 221 and the insulating dielectric layer 222 are combined to form an insulating isolation ring 22.
[0042] S14: Silicon dioxide is deposited on the bottom surface of a low-resistivity silicon substrate 21 by plasma-enhanced chemical vapor deposition (PECVD), and a first barrier layer 301 containing a first overflow trench 321 is formed by photolithography etching. Metallic germanium is prepared on the surface of the first barrier layer 301 by magnetron sputtering. The metallic germanium outside the first overflow trench 321 is removed by photolithography etching, while the metallic germanium inside the first overflow trench 321 is retained. This portion of metallic germanium can be referred to as the germanium portion 311. The width of the germanium portion 311 within the first overflow trench 321 is smaller than the width of the first overflow trench 321.
[0043] S15: First, a first clearance cavity 33 is formed on the first barrier layer 301 of the bonding structure layer 30 and the low-resistivity silicon substrate 21 using reactive ion etching (RIE), and then a second clearance cavity 27 is formed using deep reactive ion etching (DRIE).
[0044] S2: Pre-processing structure for functional structural component 10. Please refer to... Figure 3 , specifically:
[0045] S21: Provide an SOI substrate 11, which includes, from top to bottom, a base silicon 111, a wafer buried oxide layer 113 and a top silicon layer, which is used to form a sensitive thin film layer 112, and the wafer buried oxide layer 112 is formed of silicon dioxide material.
[0046] S22: Four matched varistors 121 are formed on a silicon substrate by ion implantation;
[0047] S23: A thin layer of silicon nitride is deposited on the surface of SOI substrate 11 by plasma-enhanced chemical vapor deposition (PECVD) to form silicon nitride layer 3021, and then a layer of silicon dioxide is deposited by PECVD to form silicon dioxide layer 3022. A second barrier layer 302 containing metal interconnect trench 34 and second overflow trench 322 is formed by photolithography etching. Metal aluminum (or aluminum-copper alloy) is prepared on the surface by magnetron sputtering. Metal aluminum outside the metal interconnect trench 34 and second overflow trench 322 is removed by photolithography etching process. Metal aluminum inside the metal interconnect trench 34 and second overflow trench 322 is retained. This part of metal aluminum forms varistor metal interconnect 122 and aluminum part 312. The varistor metal interconnect 122 in the metal interconnect trench 34 is used to connect four varistors 121 to form Wheatstone bridge circuit 12. The varistor metal interconnect 122 and aluminum part 312 are electrically connected.
[0048] S3: The pre-processed cover plate 20 obtained in step S1 and the pre-processed functional structural component 10 obtained in step S2 are precisely aligned and subjected to a certain temperature and pressure to form a stable bonding structure. This structure is then further processed to form a pressure sensor. Please refer to... Figure 4 Specifically,
[0049] S31: The germanium portion 311 on the bottom surface of the low-resistivity silicon substrate 21 is precisely aligned with the aluminum portion 312 on the top surface of the SOI substrate 11. By applying high temperature (425℃~460℃) and a certain pressure, the two metals are fused together and eutectic, and finally an aluminum-germanium bonded pillar 31 is formed.
[0050] S32: Thin the top surface of the low-resistivity silicon substrate 21 to expose the insulating isolation ring 22, thereby forming a conductive silicon pillar 211 containing the insulating ring 22. The thickness of the thinned low-resistivity silicon substrate 21 is greater than 300um to ensure that the stress effect generated during the final flip-chip bonding process can be avoided.
[0051] S33: An insulating layer 25 is deposited on the top surface of a low-resistivity silicon substrate 21, and then a groove 26 is formed by exposure, etching and other methods. A metal electrode is prepared on the insulating layer 25 by magnetron sputtering, and a conductive pad 23 is finally formed by photolithography etching.
[0052] S34: A back cavity 114 is etched on the bottom wall of the SOI substrate 11. The back cavity 114 penetrates the substrate silicon 111 and the wafer buried oxide layer 113. In actual processes, the back cavity 114 can also extend to the sensitive thin film layer 112, so that the thickness of the sensitive thin film layer 112 is between 5-100um.
[0053] It should be noted that the order of steps S1 and S2 can be performed simultaneously, or the functional structural component 10 can be prepared first and then the cover plate 20 can be fabricated, depending on the actual working requirements. In the above steps, the total height and width of the first overflow groove 321 and the second overflow groove 322 should have a suitable ratio with the total height and width of the germanium part 311 and the aluminum part 312. A typical height value is 9KA for the aluminum part 312 and 7KA for the second overflow groove 322; the height of the germanium part 311 is 5KA and 2KA for the first overflow groove 321. The width of the overflow groove must be greater than the width of the bonding metal. This ensures that the metal does not overflow to the outside during bonding, while the aluminum-germanium metals fully contact and bond to a eutectic.
[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0055] The above embodiments only illustrate several implementation methods of this utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.
Claims
1. A pressure sensor chip, characterized in that, include: A functional structural component includes an SOI substrate and a Wheatstone bridge circuit formed on the SOI substrate, wherein the SOI substrate includes a sensitive thin film layer and the Wheatstone bridge circuit is formed on the sensitive thin film layer; A cover plate, located on one side of the functional structure, includes a low-resistivity silicon substrate and an insulating isolation ring formed within the low-resistivity silicon substrate. The low-resistivity silicon substrate has conductive silicon pillars separated by the insulating isolation ring, the conductive silicon pillars serving as conductive pathways. A conductive pad is formed on the side of the cover plate away from the functional structure, the conductive pad being electrically connected to the conductive silicon pillars. A bonding structure layer is located between the functional structural component and the cover plate. A bonding pillar is provided in the bonding structure layer, and the two ends of the bonding pillar are electrically connected to the Huisheng Bridge circuit and the conductive silicon pillar, respectively.
2. The pressure sensor chip as described in claim 1, characterized in that, The cross-sectional shape of the conductive silicon pillar is square, circular, or elliptical.
3. The pressure sensor chip as described in claim 2, characterized in that, The insulating isolation ring includes a polycrystalline silicon pillar and an insulating dielectric layer surrounding the outside of the polycrystalline silicon pillar.
4. The pressure sensor chip as described in claim 3, characterized in that, An isolation hole is formed in the low-resistivity silicon substrate, the isolation hole penetrates the low-resistivity silicon substrate, and the insulating isolation ring is filled with an insulating dielectric material and a polycrystalline silicon material to form the insulating isolation ring.
5. The pressure sensor chip as described in claim 1, characterized in that, The thickness of the low-resistivity silicon substrate is greater than 300 μm.
6. The pressure sensor chip as described in claim 1, characterized in that, An insulating layer is formed on one side of the low-resistivity silicon substrate on which the conductive pad is formed. An opening is formed on the insulating layer corresponding to the conductive silicon pillar. The conductive pad fills the opening and extends to the upper surface of the insulating layer.
7. The pressure sensor chip as described in claim 6, characterized in that, The insulating layer is formed of silicon dioxide or silicon nitride.
8. The pressure sensor chip as described in claim 1, characterized in that, The thickness of the suspended portion in the sensitive thin film layer can be set between 5-100 μm, and the length and width dimensions can be set between 5-200 μm.
9. The pressure sensor chip as described in claim 1, characterized in that, An overflow groove is formed within the bonding structure layer, and the overflow groove is filled with aluminum-germanium eutectic material to form a bonding pillar.
10. The pressure sensor chip as described in claim 1, characterized in that, A first clearance cavity is formed through the bonding structure layer, and a second clearance cavity is formed on the side wall of the cover plate facing the first clearance cavity. The first clearance cavity is arranged corresponding to the second clearance cavity, and the first clearance cavity and the second clearance cavity are located above the Huistone bridge circuit.