Dimming processing device
By designing a dimming processing device that integrates the functions of a dimming board and a display control board, and utilizing FPGA to achieve multi-dimensional modulation of the video stream, the high hardware cost and timing issues of the screen display control unit are solved, thereby improving the system's versatility and ease of maintenance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-04
- Publication Date
- 2026-04-03
AI Technical Summary
Existing screen display control units have high hardware costs and are complex to repair. Users encountering timing issues need to return the screen to the factory for repair, which can lead to problems such as image misalignment and flickering.
Design a dimming processing device, including a video decoding unit, a video modulation unit, a video encoding unit, and a signal transceiver unit. Utilize an FPGA to integrate the dimming board and display control board functions to achieve parallel modulation of the brightness, color temperature, contrast, and saturation of the video stream, thus avoiding timing issues.
It reduced hardware costs, improved system versatility, avoided image problems caused by timing issues, and simplified the maintenance process.
Smart Images
Figure CN224083585U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of image display technology, and in particular to a dimming processing device based on FPGA. Background Technology
[0002] The screen display control unit consists of a dimming board and a display control board, which involves a lot of hardware and is costly. Meanwhile, the display control board is mainly used to adjust and control the displayed image. However, display control boards produced by existing manufacturers generally use a closed-source solution. Therefore, when users encounter problems such as image misalignment or flickering caused by timing issues, the screen display control unit must be returned to the manufacturer for repair. Utility Model Content
[0003] In view of this, the first aspect of this utility model discloses a dimming processing device.
[0004] The dimming processing device includes a video decoding unit, a video modulation unit, a video encoding unit, and a signal transceiver unit;
[0005] The video decoding unit receives external video input signals and decodes the video input signals into a first video stream;
[0006] The video modulation unit receives the first video stream from the video decoding unit and at least one modulation signal from the signal transceiver unit, and modulates one or more of the brightness, color temperature, contrast, and saturation of the first video stream according to the modulation signal to form a second video stream;
[0007] The video encoding unit receives the second video stream from the video modulation unit and encodes the second video stream into a video output signal;
[0008] The signal transceiver unit receives control commands from the outside and generates at least one of the modulation signals according to the control commands.
[0009] In some embodiments disclosed in this utility model,
[0010] The video decoding unit includes the ADV7610 video decoding circuit;
[0011] The ADV7610 video decoding circuit includes a first HDMI interface, a first signal protection sub-circuit, a second signal protection sub-circuit, an ADV7610BBCZ chip, and an external crystal oscillator sub-circuit.
[0012] The first HDMI port is connected to an external HDMI plug;
[0013] The first signal protection sub-circuit is connected between the data function interface of the first HDMI interface and the ADV7610BBCZ chip;
[0014] The second signal protection sub-circuit is connected between the power function interface of the first HDMI interface and the ADV7610BBCZ chip.
[0015] The external crystal oscillator circuit is connected to the ADV7610BBCZ chip;
[0016] The ADV7610BBCZ chip is connected to the video modulation unit.
[0017] In some embodiments disclosed in this utility model,
[0018] The first signal protection sub-circuit includes a BV-ULC0524PA chip;
[0019] The BV-ULC0524PA chip is connected between the data function interface of the first HDMI interface and the ADV7610BBCZ chip.
[0020] In some embodiments disclosed in this utility model,
[0021] The second signal protection sub-circuit includes an SRV05-4 chip;
[0022] The SRV05-4 chip is connected between the power function interface of the first HDMI interface and the ADV7610BBCZ chip.
[0023] In some embodiments disclosed in this utility model,
[0024] The video modulation unit includes an FPGA;
[0025] The FPGA is configured with a signal analysis module, a brightness adjustment module, a color temperature adjustment module, a contrast adjustment module, and a saturation adjustment module.
[0026] The signal parsing module parses the control commands in the modulated signal;
[0027] The brightness adjustment module modulates the brightness of the first video stream according to the control command;
[0028] The color temperature adjustment module modulates the color temperature of the first video stream according to the control command;
[0029] The contrast adjustment module modulates the contrast of the first video stream according to the control command;
[0030] The saturation adjustment module modulates the saturation of the first video stream according to the control command.
[0031] In some embodiments disclosed in this utility model,
[0032] The FPGA is configured as JFM7325T-BGA900.
[0033] In some embodiments disclosed in this utility model,
[0034] The video encoding unit includes a video encoding circuit.
[0035] The video encoding circuit includes an ADV7511 chip, a third protection sub-circuit, a fourth protection sub-circuit, and a second HDMI interface.
[0036] The ADV7511 chip is connected to the video modulation unit;
[0037] The third signal protection sub-circuit is connected between the data function interface of the second HDMI interface and the ADV7511 chip;
[0038] The fourth signal protection sub-circuit is connected between the power function interface of the second HDMI interface and the ADV7511 chip.
[0039] In some embodiments disclosed in this utility model,
[0040] The signal transceiver unit includes a MAX3490 serial transceiver circuit.
[0041] In some embodiments disclosed in this utility model,
[0042] The dimming processing device includes a power module unit;
[0043] The power module unit supplies power to the video decoding unit, video modulation unit, video encoding unit, and signal transceiver unit;
[0044] In some embodiments disclosed in this utility model,
[0045] The dimming processing device includes a buffer unit;
[0046] The cache unit provides storage space to the video decoding unit, video modulation unit, and video encoding unit.
[0047] Compared with the prior art, the dimming processing device of this utility model integrates the necessary functions of the dimming board and the display control board through the video modulation unit, and can modulate multiple parameters of the video stream in parallel, which can avoid various image problems caused by timing and has good versatility. Attached Figure Description
[0048] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0049] Figure 1 This is a topological schematic diagram of the dimming processing device in this embodiment;
[0050] Figure 2 This is a schematic diagram of the video decoding unit in this embodiment;
[0051] Figure 3 This is a schematic diagram of the functional modules of the FPGA in this embodiment;
[0052] Figure 4 This is a schematic diagram of the video encoding unit in this embodiment;
[0053] Figure 5 This is a schematic diagram of the signal transceiver unit in this embodiment;
[0054] Figure 6a This is a partial structural diagram of the power module unit in this embodiment;
[0055] Figure 6b This is a partial structural diagram of the power module unit in this embodiment;
[0056] Figure 7 This is a schematic diagram of the cache unit in this embodiment. Detailed Implementation
[0057] The technical solutions of this utility model will be clearly and completely described below with reference to the embodiments of this utility model. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.
[0058] Figure 1 This is a topological schematic diagram of the dimming processing device in this embodiment.
[0059] Figure 1 The dimming processing device shown includes a video decoding unit, a video modulation unit, a video encoding unit, a signal transceiver unit, a power supply module unit, and a buffer unit.
[0060] The video decoding unit receives the video input signal from an external HDMI video source and decodes the HDMI video stream's video input signal into a first video stream of RGB888.
[0061] The video modulation unit is configured as an FPGA. The FPGA receives the first video stream from the video decoding unit and several modulation signals from the signal transceiver unit, and obtains modulation parameters from the modulation signals. The FPGA modulates the brightness, color temperature, contrast, saturation, etc. of the first video stream according to the modulation parameters to generate a second video stream.
[0062] The video encoding unit receives a second video stream from the video modulation unit, and the second video stream encoded in RGB888 is the video output signal of the HDMI video stream.
[0063] The signal transceiver unit receives control commands from the user and generates modulated signals according to the control commands.
[0064] Therefore, in this embodiment, the video decoding unit and the video encoding unit in the dimming processing device realize the conversion between HDMI video stream and RGB888 video stream; the video modulation unit can realize multi-dimensional modulation of the video stream in parallel according to control instructions.
[0065] Furthermore, Figure 2 This is a schematic diagram of the video decoding unit in this embodiment.
[0066] Figure 2 The video decoding unit shown includes the ADV7610 video decoding circuit.
[0067] The ADV7610 video decoding circuit includes a first HDMI interface, a first signal protection sub-circuit, a second signal protection sub-circuit, an ADV7610BBCZ chip, and an external crystal oscillator circuit.
[0068] The first HDMI port connects to an external HDMI plug.
[0069] The first signal protection sub-circuit includes two BV-ULC0524PA chips. The two BV-ULC0524PA chips are respectively connected between the data function interface of the first HDMI port and the ADV7610BBCZ chip. The data function interface refers to the pin interface used for data transmission in HDMI.
[0070] The second signal protection sub-circuit includes an SRV05-4 chip. The SRV05-4 chip is connected between the non-data function interface of the first HDMI interface and the ADV7610BBCZ chip. The non-data function interface refers to the pin interface of HDMI used for power transmission, signal enable, etc.
[0071] The external crystal oscillator circuit includes an X32F-G20SSA chip. The X32F-G20SSA chip is connected to the ADV7610BBCZ chip.
[0072] The ADV7610BBCZ chip is connected to the FPGA.
[0073] Therefore, the video decoding unit in this embodiment can convert HDMI video streams into RGB888 video streams and protect data signals, power supply voltages, etc., avoiding damage from transient overvoltages and electrostatic discharges.
[0074] Furthermore, Figure 3 This is a schematic diagram of the functional modules of the FPGA in this embodiment.
[0075] Figure 3 The FPGA selected is JFM7325T-BGA900. The FPGA is configured with a signal analysis module, a brightness adjustment module, a color temperature adjustment module, a contrast adjustment module, and a saturation adjustment module.
[0076] The signal parsing module parses the modulated signal to obtain control commands, which include one or more control parameters that need to be modulated.
[0077] The brightness adjustment module modulates the brightness of the first video stream according to the brightness control parameters.
[0078] The color temperature adjustment module modulates the color temperature of the first video stream according to the color temperature control parameters.
[0079] The contrast adjustment module modulates the contrast of the first video stream by controlling the contrast parameters.
[0080] The saturation adjustment module controls the saturation of the first video stream using its saturation control parameters.
[0081] Therefore, this implementation uses domestically produced PFGA as its core, integrating dimming and display control functions to achieve parallel processing and modulation of one or more parameters such as brightness, color temperature, and contrast, thus avoiding image problems caused by timing issues.
[0082] Furthermore, Figure 4 This is a schematic diagram of the video encoding unit in this embodiment.
[0083] Figure 4 The video encoding unit shown includes video encoding circuitry.
[0084] The video encoding circuit includes an ADV7511 chip, a third protection sub-circuit, a fourth protection sub-circuit, and a second HDMI interface.
[0085] The ADV7511 chip is connected to the video modulation unit;
[0086] The third signal protection sub-circuit includes two AZ1045-04F chips. The two AZ1045-04F chips are connected between the data function interface of the second HDMI port and the ADV7610BBCZ chip, respectively. The data function interface refers to the pin interface used for data transmission in HDMI.
[0087] The fourth signal protection sub-circuit includes an AZ1045-04F chip. The AZ1045-04F chip is connected between the non-data function interface of the second HDMI interface and the ADV7610BBCZ chip. The non-data function interface refers to pin interfaces such as those used for power transmission and signal enable in HDMI.
[0088] Therefore, the video encoding unit in this embodiment can convert RGB888 video streams into HDMI video streams and protect data signals, power supply voltages, etc., to avoid damage from electrostatic discharge.
[0089] Furthermore, Figure 5 This is a schematic diagram of the signal transceiver unit in this embodiment.
[0090] Figure 5 The signal transceiver unit shown includes a MAX3490 serial transceiver circuit.
[0091] The MAX3490 serial transceiver circuit includes the MAX3490ESA chip.
[0092] The MAX3490ESA chip and its peripheral circuitry are connected between the external user and the ADV7610BBCZ chip.
[0093] Therefore, the MAX3490 serial transceiver circuit in this embodiment realizes the reception and analysis of control commands from external users to obtain modulation signals that the FPGA can recognize.
[0094] Furthermore, Figure 6 is a structural schematic diagram of the power module unit in this embodiment.
[0095] Figure 6 shows that the power module unit includes a first power circuit and a second power circuit.
[0096] The first power supply circuit includes an LTM4644LY chip.
[0097] The first LTM4644LY chip and its peripheral circuitry provide 1V and 5V power supply voltages.
[0098] The second power supply circuit includes an LTM4644LY chip.
[0099] The second LTM4644LY chip and its peripheral circuitry provide 1.8V and 3.3V power supply voltages.
[0100] Furthermore, Figure 7 This is a schematic diagram of the cache unit in this embodiment.
[0101] Figure 7 The cache unit shown includes the SN74LVC8T25PW chip and the N25Q128A13EF740G chip. The SN74LVC8T25PW chip, the N25Q128A13EF740G chip, and their peripheral circuitry provide cache space for FPGAs, etc.
[0102] Based on this, the dimming processing device in this embodiment can integrate the control and display functions of traditional dimming boards and display control boards through the video modulation unit, and can modulate multiple dimensions of parameters of the video stream in parallel, avoiding various image problems caused by timing, and has good versatility.
[0103] The above are merely preferred embodiments of this utility model and are not intended to limit this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. A dimming processing device, characterized in that, include, The dimming processing device includes a video decoding unit, a video modulation unit, a video encoding unit, and a signal transceiver unit; The video decoding unit receives external video input signals and decodes the video input signals into a first video stream; The video modulation unit receives the first video stream from the video decoding unit and at least one modulation signal from the signal transceiver unit, and modulates one or more of the brightness, color temperature, contrast, and saturation of the first video stream according to the modulation signal to form a second video stream; The video encoding unit receives the second video stream from the video modulation unit and encodes the second video stream into a video output signal; The signal transceiver unit receives control commands from the outside and generates at least one of the modulation signals according to the control commands.
2. The dimming processing device according to claim 1, characterized in that, The video decoding unit includes the ADV7610 video decoding circuit; The ADV7610 video decoding circuit includes a first HDMI interface, a first signal protection sub-circuit, a second signal protection sub-circuit, an ADV7610BBCZ chip, and an external crystal oscillator sub-circuit. The first HDMI port is connected to an external HDMI plug; The first signal protection sub-circuit is connected between the data function interface of the first HDMI interface and the ADV7610BBCZ chip; The second signal protection sub-circuit is connected between the power function interface of the first HDMI interface and the ADV7610BBCZ chip. The external crystal oscillator circuit is connected to the ADV7610BBCZ chip; The ADV7610BBCZ chip is connected to the video modulation unit.
3. The dimming processing device according to claim 2, characterized in that, The first signal protection sub-circuit includes a BV-ULC0524PA chip; The BV-ULC0524PA chip is connected between the data function interface of the first HDMI interface and the ADV7610BBCZ chip.
4. The dimming processing device according to claim 2, characterized in that, The second signal protection sub-circuit includes an SRV05-4 chip; The SRV05-4 chip is connected between the power function interface of the first HDMI interface and the ADV7610BBCZ chip.
5. The dimming processing device according to claim 1, characterized in that, The video modulation unit includes an FPGA; The FPGA is configured with a signal analysis module, a brightness adjustment module, a color temperature adjustment module, a contrast adjustment module, and a saturation adjustment module. The signal parsing module parses the control commands in the modulated signal; The brightness adjustment module modulates the brightness of the first video stream according to the control command; The color temperature adjustment module modulates the color temperature of the first video stream according to the control command; The contrast adjustment module modulates the contrast of the first video stream according to the control command; The saturation adjustment module modulates the saturation of the first video stream according to the control command.
6. The dimming processing device according to claim 5, characterized in that, The FPGA is configured as JFM7325T-BGA900.
7. The dimming processing device according to claim 1, characterized in that, The video encoding unit includes a video encoding circuit. The video encoding circuit includes an ADV7511 chip, a third signal protection sub-circuit, a fourth signal protection sub-circuit, and a second HDMI interface. The ADV7511 chip is connected to the video modulation unit; The third signal protection sub-circuit is connected between the data function interface of the second HDMI interface and the ADV7511 chip; The fourth signal protection sub-circuit is connected between the power function interface of the second HDMI interface and the ADV7511 chip.
8. The dimming processing device according to claim 1, characterized in that, The signal transceiver unit includes a MAX3490 serial transceiver circuit.
9. The dimming processing device according to claim 1, characterized in that, The dimming processing device includes a power module unit; The power module unit supplies power to the video decoding unit, video modulation unit, video encoding unit, and signal transceiver unit.
10. The dimming processing device according to claim 1, characterized in that, The dimming processing device includes a buffer unit; The cache unit provides storage space to the video decoding unit, video modulation unit, and video encoding unit.