Integrated circuit device package

Abstract

An integrated circuit (IC) device package includes a structure having a base and a wall extending from the base; at least one IC die mounted to the base within the wall, each die having a top surface parallel to the base, and the die having a thickness extending perpendicular to the top surface along the axis, the thickness being at most equal to the height of the wall; a thermally conductive heat sink extending parallel to the base over the die and wall; and an interface layer including an adhesive layer portion disposed between the wall and the heat sink to bond the heat sink to the wall, and a thermal interface material (TIM) layer portion coplanar with and laterally displaced from the adhesive layer portion, the TIM layer portion disposed in thermally conductive relationship between the heat sink and each respective die, to dissipate heat from each respective die to the heat sink.

Description

[0001] Cross-reference of related applications

[0002] This disclosure claims the benefit of co-pending, co-assigned U.S. Provisional Patent Application No. 63 / 358,908, filed July 7, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to packages for integrated circuit dies. More specifically, this disclosure relates to packages and methods that include an interface layer portion that is in thermal contact with the integrated circuit die and package structure to reduce the possibility of delamination due to package layer warping. Background Technology

[0004] The background description provided herein is intended to provide a general context for this disclosure. Within the scope described in this background section, the work of the inventors of this invention, and aspects of the description that may not conform to the prior art at the time of submission, are neither explicitly nor implicitly acknowledged as prior art to the subject matter of this disclosure.

[0005] Integrated circuit devices include integrated circuit dies on which device circuitry is formed. Typically, the integrated circuit die is mounted on a substrate and protected by a package that surrounds or encloses the integrated circuit die. The package surrounding or enclosing the integrated circuit die can be a molded package. In an "exposed die" integrated circuit device package, the molded package includes walls surrounding the die surface attached to the substrate (typically one of the two largest surfaces of the die), and die sides perpendicular to the substrate, exposing the remaining sides of the integrated circuit die (typically the other of the two largest surfaces). A thermally conductive cap or shroud (called a "heat sink") can cover the exposed surfaces of the integrated circuit die to dissipate heat generated by the integrated circuit die during operation while protecting the die. The heat sink can be attached to the package via a thermally conductive interface layer to transfer heat from the integrated circuit die to the heat sink. However, after the heat sink is attached to the integrated circuit device package, warping of the package can cause the interface layer and the heat sink to delaminate from the package. Summary of the Invention

[0006] According to an implementation of the subject matter of this disclosure, an integrated circuit device package includes: a package structure having a base and a wall extending from the base; at least one integrated circuit die mounted within the wall to the base of the package structure, each of the at least one integrated circuit die having a top surface parallel to the base and each of the at least one integrated circuit die having a thickness extending along an axis perpendicular to the top surface, the thickness being at most equal to the height of the wall; a thermally conductive heat sink extending parallel to the base above the at least one integrated circuit die and above the wall; and an interface layer including an adhesive layer portion disposed between the wall and the heat sink to bond the heat sink to the wall, and a thermal interface material (TIM) layer portion coplanar with and laterally displaced from the adhesive layer portion, the TIM layer portion being disposed in a thermally conductive relationship between the heat sink and each corresponding integrated circuit die from the at least one integrated circuit die to dissipate heat from each corresponding integrated circuit die to the heat sink.

[0007] In a first implementation of this integrated circuit device package, the package structure may include molded package material.

[0008] In a second implementation of this integrated circuit device package, the adhesive layer portion may be thermally conductive.

[0009] In this third implementation of the integrated circuit device package, dies from at least one integrated circuit die are arranged in a stack of integrated circuit dies, the stack having a stack thickness perpendicular to the top surface, the thickness being at most equal to the height of the wall.

[0010] In this fourth implementation of the integrated circuit device package, the TIM layer portion may include any of the following: (a) polymer TIM, (b) graphite TIM, (c) metal TIM, and (d) liquid metal TIM.

[0011] In this fifth implementation of the integrated circuit device package, the adhesive layer portion may surround the TIM layer portion within the interface layer.

[0012] In this sixth implementation of the integrated circuit device package, the TIM layer portion can be flowable, and the adhesive layer portion can surround the TIM layer portion in the interface layer.

[0013] According to a first aspect of the sixth implementation, the adhesive layer portion can form a barrier between the integrated circuit die and the heat sink to accommodate the flowable TIM layer portion.

[0014] In this seventh implementation of the integrated circuit device package, the heat sink may include a flat cover.

[0015] In the eighth implementation of this integrated circuit device package, the heat sink may include a forged cover.

[0016] In this ninth implementation of the integrated circuit device package, the heat sink may include a stamped cap-shaped cover.

[0017] According to an implementation of the subject matter of this disclosure, a method for packaging at least one integrated circuit die is provided, wherein each of the at least one integrated circuit die is mounted to a package structure having a base and a wall extending from the base, and wherein each of the at least one integrated circuit die has a top surface parallel to the base, and wherein each of the at least one integrated circuit die has a thickness perpendicular to the top surface, the thickness being at most equal to the height of the wall, the method comprising applying an adhesive layer portion over the wall, applying a thermal interface material (TIM) layer portion coplanar with and laterally displaced from the adhesive layer portion, the TIM layer portion being in a thermally conductive relationship over each respective integrated circuit die in the at least one integrated circuit die, and placing a thermally conductive heat sink extending parallel to the base over each of the adhesive layer portion and the TIM layer portion to bond the heat sink to the wall with the adhesive layer portion and to form a thermally conductive relationship between the heat sink and each respective integrated circuit die with the TIM layer portion.

[0018] In a first implementation of this method, applying the TIM layer portion may include applying any of the following: (a) polymer TIM, (b) graphite TIM, (c) metal TIM, and (d) liquid metal TIM, which is coplanar with and laterally displaced from the adhesive layer portion, in a thermally conductive relationship between the heat sink and each respective integrated circuit die from at least one integrated circuit die, so as to dissipate heat from each respective integrated circuit die to the heat sink.

[0019] In a second implementation of this method, applying an adhesive layer portion above the wall may include applying an adhesive layer portion to surround the TIM layer portion.

[0020] In a third implementation of this method, when the TIM layer portion is flowable, applying an adhesive layer portion to surround the TIM layer portion may include applying an adhesive layer portion to form a barrier between the integrated circuit die and the heat sink to accommodate the TIM layer portion.

[0021] A fourth implementation of this method may also include: a cured adhesive layer portion, wherein the adhesive layer portion bonds the wall of the package structure to the heat sink.

[0022] According to a first aspect of the fourth implementation, curing the adhesive layer portion may include: heating the adhesive layer portion to a predetermined curing temperature for a predetermined curing duration.

[0023] In a fifth implementation of this method, placing a heat-conducting radiator extending parallel to the base over each of the adhesive layer portion and the TIM layer portion may include placing a flat cover over each of the adhesive layer portion and the TIM layer portion.

[0024] In a sixth implementation of this method, placing a heat-conducting radiator extending parallel to the base over each of the adhesive layer portion and the TIM layer portion may include placing a forged cap over each of the adhesive layer portion and the TIM layer portion.

[0025] In a seventh implementation of this method, placing a heat-conducting radiator extending parallel to the base above each of the adhesive layer portion and the TIM layer portion may include placing a stamped cap-shaped cover above each of the adhesive layer portion and the TIM layer portion. Attached Figure Description

[0026] Further features, nature, and various advantages of this disclosure will become apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein similar reference numerals always refer to similar parts, and in the drawings:

[0027] Figure 1 This is a vertical cross-sectional view of an integrated circuit device package according to an implementation of the subject matter of this disclosure;

[0028] Figure 2 Integrated circuit device packages (such as) illustrating some implementations of the subject matter of this disclosure are shown. Figure 1 The progress of the manufacturing stage (as shown);

[0029] Figure 3 It is a vertical cross-sectional view of a three-dimensional (3D) integrated circuit device package according to an implementation of the subject matter of this disclosure, including a stack of integrated circuit dies rather than individual integrated circuit dies;

[0030] Figure 4 This is a vertical cross-sectional view of a 2.5D integrated circuit device package according to some implementations of the subject matter of this disclosure, wherein multiple individual integrated circuit dies are separated by a middle wall;

[0031] Figure 5 This is a perspective view of an integrated circuit device package before the application of a heat sink, according to some implementations of the subject matter of this disclosure;

[0032] Figure 6 and Figure 7 It is similar to different types of heat sinks according to the implementation of the subject matter of this disclosure. Figure 1 A cross-sectional view of the implementation method of integrated circuit device package;

[0033] Figure 8 This is a flowchart illustrating a method for manufacturing an integrated circuit device package according to some implementations of the subject matter of this disclosure; and

[0034] Figure 9 This is a flowchart of a method for manufacturing an integrated circuit device package having a flowable thermal interface material (TIM) according to some implementations of the subject matter of this disclosure. Detailed Implementation

[0035] An "exposed die" integrated circuit device package of the type disclosed herein may have a base or substrate on which at least one integrated circuit die is mounted, and has walls, for example, molded from epoxy resin extending from the base and surrounding the integrated circuit die. As described above, in an exposed die integrated circuit device package, a thermally conductive cap or closure (referred to as a "heat sink") may be placed on the exposed surface of the integrated circuit die to dissipate heat generated by the integrated circuit die during operation while protecting the die. The heat sink may be attached to the package via a thermally conductive interface layer to transfer heat from the integrated circuit die to the heat sink.

[0036] However, after the heat sink is attached to the integrated circuit device package, warping of the package can cause the interface layer and the heat sink to delaminate from the package, for example, during the curing or reflow process, or during use, due to the heat generated by the integrated circuit device and the mechanical action that may occur when the integrated circuit device is moved.

[0037] Some integrated circuit device packages that can use the types of subject matter disclosed herein include multiple integrated circuit dies mounted to a base. In such implementations, in addition to the walls surrounding the perimeter of the integrated circuit devices, walls may also exist between individual integrated circuit devices or between groups of integrated circuit devices. In this description and figures, the base or substrate is designated as the “bottom” of the package regardless of its actual orientation, and all directional references in this description are based on this designation.

[0038] The walls surrounding or between the integrated circuit die of the integrated circuit device package may extend at least as high as the top surface of the integrated circuit die (e.g., the largest of two largest surfaces opposite the surface bonded to the base of the package structure), which remains exposed. In some implementations, the walls of the package structure may extend to the same height as the corresponding top surface of the integrated circuit die, such that the top surface of the wall is flush with, i.e., coplanar with, the corresponding top surface of the integrated circuit die. In other implementations, the walls may extend to a height greater than the top surface of the integrated circuit die. A thermally conductive cap or closure (referred to as a "heat sink") may cover the walls and exposed surfaces of the integrated circuit die to dissipate heat generated by the integrated circuit die during operation while protecting the die. The heat sink may be attached to the package via a thermally conductive interface layer to transfer heat from the integrated circuit die to the heat sink.

[0039] Traditionally, the interface layer consists only of a thermal interface material (TIM) applied over each of the wall and the integrated circuit die, serving both as an adhesive to hold the heatsink in place and as a heat transfer medium to conduct heat generated during the operation of the integrated circuit die to the heatsink. However, TIMs are primarily designed for their thermal conductivity, and their adhesive properties may be secondary.

[0040] Therefore, if warping occurs, for example due to a mismatch between the respective coefficients of thermal expansion (CTE) between the molded walls and the interface layer, or due to external mechanical disturbances, the adhesive properties of the TIM may be insufficient to prevent the heatsink from delaminating from the integrated circuit device package, thus creating voids in the interface layer where heat cannot be conducted to the heatsink. In some cases, voids in the interface layer can become the focus of further failures.

[0041] Larger integrated circuit device packages, such as ball grid array (BGA) packages and 2.5D or 3D packages, may be more prone to warping. 2.5D or multi-chip module (MCM) integrated circuit device packages may include multiple integrated circuit dies mounted on a package substrate, wherein the package is integral, and in some implementations, each integrated circuit die or group of dies is surrounded by walls of the package structure. 3D integrated circuit device packages may include one or more stacks of integrated circuit dies, wherein the package is integral, and in some implementations, each stack of integrated circuit dies or group of die stacks is surrounded by walls of the package structure.

[0042] According to the implementation of the subject matter of this disclosure, a typical TIM interface layer is replaced with an interface layer comprising one or more TIM portions and one or more adhesive portions. The adhesive portion of the interface layer is applied over the walls of the package structure (between the top of the wall and the heatsink), while the TIM portion of the interface layer is applied over each integrated circuit die in the integrated circuit die. Unlike the TIM interface layer portions, the adhesive interface layer portions are primarily designed as adhesive, offering superior adhesion compared to TIM. Compared to an interface layer comprising only TIM, the adhesive portion improves the bond between the heatsink and the walls of the package structure after curing, thereby better resisting heatsink delamination during integrated circuit package warpage.

[0043] In some implementations, the TIM portion can be any of the following: (a) a polymer TIM layer portion, (b) a graphite TIM layer portion, (c) a metal TIM layer portion, and (d) a liquid metal TIM film portion. The adhesive portion can be any suitable integrated circuit device package adhesive, which may include, but is not limited to, any of the following available from Dow Inc.: (a) DOWSIL ® EA-8700, (b)DOWSIL ® EA-8900, (c)DOWSIL ® SE 2304 and (d)DOWSIL ® SE4450. Each of the TIM portion and the adhesive portion may be applied to the respective top surface of each exposed integrated circuit die and each wall of the package structure by any of the following: (a) snowflake application pattern, (b) line application pattern, and (c) serpentine application pattern.

[0044] In some implementations, the thermal conductivity of the adhesive portion can be enhanced to allow for additional heat dissipation to the heat sink. For example, the adhesive can be impregnated or injected with particles of thermally conductive material, such as, for example, suitable metal particles.

[0045] In some implementations, as described above, the TIM portion of the interface layer can be a flowable TIM (e.g., a liquid metal TIM, or a metal TIM that is flowable during reflow operations). In this implementation, the adhesive portion of the interface layer acts as a dam to contain the flowable TIM portion. If the TIM portion is flowable during the application of the interface layer (e.g., it is a liquid metal TIM), the adhesive portion of the interface layer can be applied first, and then the flowable TIM portion of the interface layer can be applied within the dam formed by the adhesive portion of the interface layer.

[0046] By reference Figures 1 to 9 This will allow for a better understanding of the subject matter of this disclosure.

[0047] Figure 1 Different layers of an integrated circuit device package 100 are shown. The integrated circuit device package 100 includes a package structure 105 having a substrate 102 and walls 106. In some implementations, the package structure substrate 102 may be formed of multiple laminated dielectric layers (e.g., high-density interconnect (HDI) layers). The integrated circuit device package 100 includes an integrated circuit die 104 mounted to the substrate 102. In some implementations, the integrated circuit die 104 may be electrically coupled to the substrate 102 and bonded by an underfill bonding material.

[0048] In implementations of the subject matter of this disclosure, the wall 106 of the package structure 105 may surround the integrated circuit die 104. In some implementations, the wall 106 is formed of a molded package material (e.g., molding resin). In other implementations (not shown), the molded package material may extend below the integrated circuit die 104 and between the integrated circuit die 104 and the substrate 102. Each integrated circuit die 104 has a thickness measured along a line perpendicular to the substrate 102, which is at most equal to the height of the wall 106.

[0049] An interface layer 109, comprising one or more adhesive portions 108 and one or more thermal interface material (TIM) portions 110, is applied to the top surface of the wall 106 and the exposed top surface of the integrated circuit die 104. Specifically, one or more adhesive portions 108 are applied to the top surface of the wall 104, while one or more TIM portions 110 are applied to the exposed top surface of the integrated circuit die 104. A thermally conductive heat sink 112 is placed over each of the interface layers 109 comprising the adhesive portions 108 and the TIM portions 100 (in the orientation shown in the figure). The adhesive portion 108 bonds the heat sink 112 to the wall 106. The TIM portions 110 are applied between the heat sink 112 and the integrated circuit die 104 in a thermally conductive relationship to conduct heat generated during operation of the integrated circuit die 104 to the heat sink 112, which acts as a heat sink. The heat sink 112 can also act as a cover to protect the integrated circuit die 104 from mechanical damage.

[0050] As described above, the integrated circuit device package 100 may be prone to warping, which could cause the heat sink 112 to separate from the integrated circuit device package 100, reducing its heat absorption capacity and potentially leading to overheating and failure of the integrated circuit device 104. By replacing the TIM 110 with adhesive 108 above the wall 106, the adhesion between the heat sink 112 and the integrated circuit device package 100 is improved, thereby reducing the likelihood of the heat sink 112 separating due to warping. Furthermore, the improved adhesion between the heat sink 112 and the integrated circuit device package 100 can provide increased mechanical stiffness to help resist warping of the integrated circuit device package 100.

[0051] Figure 2 The diagram illustrates an implementation 200 of a method for manufacturing an integrated circuit device package 100 according to the subject matter of this disclosure. At 202, one or more (one shown) integrated circuit dies 104 are disposed over the base or substrate 102 of a package structure 105, wherein walls 106 in the package structure 105 are molded, for example, from epoxy resin surrounding the integrated circuit dies 104. The top surface of the integrated circuit die 104 remains exposed. Then at 204, an adhesive portion 108 is applied over the walls 106 of the package structure 105. Then at 206, a TIM portion 110 is applied over each integrated circuit die 104. The TIM portion 110 and the adhesive portion 108 are part of an interface layer 109, coplanar but laterally separated. At 208, a heat sink 112 is placed over the adhesive portion 108 and the TIM portion 110 of the interface layer 109. Although the adhesive portion 108 is shown to be applied prior to the TIM portion 110, the TIM portion 110 may also be applied prior to the adhesive portion 108 unless the TIM portion 110 is flowable during application (e.g., is liquid metal TIM), or the adhesive portion 108 and the TIM portion 110 may be applied simultaneously.

[0052] The TIM portion 110 is disposed between the integrated circuit die 104 and the heat sink 112 in a thermally conductive manner, thereby allowing heat from the operation of the integrated circuit die 104 to be dissipated to the heat sink 112 through the TIM portion 100.

[0053] In assembling integrated circuit device package 100 (e.g., such as Figure 2Following this (as shown), the interface layer 109 (e.g., adhesive portion 108 and TIM portion 110) can be cured to bond the heat sink 112 to the package structure wall 106. Depending on the nature of the adhesive portion 108, curing can be performed using heat, chemical reaction, or light of a suitable wavelength (e.g., ultraviolet light) for a predetermined curing duration, which can be delivered by a laser or other suitable source. In the case where the TIM portion 110 is a metallic TIM implementation, TIM reflow can be performed to bond the heat sink 112 to the integrated circuit die 104.

[0054] Figure 3 It shows the relationship with Figure 1 A similar structure to the three-dimensional (3D) integrated circuit device package 300 is used, but with at least one stack 302 of at least two integrated circuit dies 104 instead of individual integrated circuit dies 104. In some implementations, the stack 302 may include a third integrated circuit die (not shown). The wall 106 of the 3D integrated circuit device package may be molded (e.g., molded from epoxy resin), and in any case, its top surface is at least as high as the top surface of the topmost integrated circuit die 104 in the stack 302. As previously disclosed, an adhesive layer portion 108 of the interface layer 109 is applied over the wall 106, and a TIM portion 110 of the interface layer 108 is attached over the topmost integrated circuit die 104 in the stack 302. A heat sink 112 is positioned over the package 300, contacting each of the adhesive portion 108 and the TIM portion 110 of the interface layer 109.

[0055] Figure 4 A 2.5D / multi-chip module (MCM) integrated circuit device package 400, which is similar to an implementation of the subject matter of this disclosure, is shown. Figure 1 The 2.5D / MCM integrated circuit device package 400 includes a plurality of integrated circuit dies 104 disposed on a base or substrate 102. As shown, in this implementation, walls 106 are present not only around the periphery of the package 400 but also between the dies 104. As previously disclosed, adhesive portions 108 of an interface layer 109 are applied over the walls 106, including the walls 106 between the integrated circuit dies 104. TIM portions 110 of the interface layer 109 are attached above each respective top surface of each respective integrated circuit die 104 between the adhesive portions 108. A heat sink 112 is disposed over the adhesive portions 108 and TIM portions 110 of the interface layer 109 to bond the heat sink 112 to the integrated circuit device package 400.

[0056] Figure 5A 2.5D / MCM integrated circuit device package 500 according to some implementations of the subject matter of this disclosure is shown, having exposed integrated circuit dies 104 disposed on a base or substrate 102 of a package structure 105. As previously disclosed, walls 106 of the package structure 105 may surround the integrated circuit dies 104. The 2.5D / MCM integrated circuit device package 500 includes several integrated circuit dies 104 individually surrounded by walls 106, such as those in regions 502 of the integrated circuit device package 500, and other integrated circuit dies 104 combined together within the walls 106, such as those in regions 504 of the integrated circuit device package 500. Each integrated circuit die 104 has a thickness measured perpendicular to the base 102, which is at most equal to the height of the wall 106. That is, the walls 106 surrounding or between the integrated circuit dies 104 may extend at least as high as the top surfaces of the integrated circuit bodies 104, which remain exposed. Although not shown in the figure, as previously disclosed and in conjunction with other implementations described above, an adhesive portion 108 of the interface layer 109 is applied over walls 106, including walls 106 between or surrounding groups of integrated circuit dies 104. A TIM portion 110 of the interface layer 109 is attached over each respective top surface of each respective integrated circuit die 104 between the adhesive portions 108. A heat sink 112 is disposed over the adhesive portions 108 and TIM portions 110 of the interface layer 109 to bond the heat sink 112 to the integrated circuit device package 500.

[0057] Figure 6 and Figure 7 It is based on the implementation method of the subject matter disclosed herein and Figure 1 A vertical cross-sectional view of an embodiment of a similar integrated circuit device package, but with a different type of heat sink compared to the flat cap-type heat sink 112. For example, as... Figure 6 As depicted, the integrated circuit device package 600 includes a forged cap-type heat sink 602 disposed above an interface layer 109, the interface layer including an adhesive portion 108 and a TIM portion 110. Optionally, the forged cap-type heat sink 602 may be additionally bonded to the base 102 of the package structure 105 at 604 by an adhesive or bonding agent. In some such implementations, the adhesive 604 may be the same adhesive as the adhesive portion 108. Figure 7 Another implementation is shown, in which the integrated circuit device package 700 includes a stamped cap-shaped heat sink 702.

[0058] Figure 8Method 800, which implements the subject matter of this disclosure, is illustrated. Method 800 begins at 802, where an adhesive layer portion is applied over a wall. At 804, a thermal interface material (TIM) layer portion is applied coplanarly with and laterally displaced from the adhesive layer portion, the TIM layer portion being thermally conductive over each respective integrated circuit die in at least one integrated circuit die. At 806, a thermally conductive heat sink extending parallel to the base is placed over each of the adhesive layer portion and the TIM layer portion.

[0059] Figure 9 A method 900 implementing the subject matter of this disclosure is illustrated. Method 900 begins at 902, wherein an adhesive layer portion is applied over a wall. At 904, a flowable thermal interface material (TIM) layer portion is applied coplanarly with and laterally displaced from the adhesive layer portion, the flowable TIM layer portion being thermally conductive over each respective integrated circuit die in at least one integrated circuit die. At 906, a thermally conductive radiator extending parallel to the base is placed over each of the adhesive layer portion and the flowable TIM layer portion.

[0060] Among the alternative implementation methods ( Figure 8 and Figure 9 (Not shown in the diagram) Before the walls of the package structure are arranged around each integrated circuit die, each of at least one integrated circuit die can be mounted to the base of the package structure. The walls of the package structure are formed to have a height extending from the base of the package structure, wherein the thickness of the integrated circuit die is at most equal to the height of the walls of the package structure.

[0061] Therefore, it can be seen that an integrated circuit device package has been provided that provides heat dissipation and reduces the possibility of package layer delamination due to warping.

[0062] As used herein and in the appended claims, the syntactic phrase “one of A and B” shall refer to “A or B”.

[0063] It should be noted that the above description only illustrates the principles of the present invention, and the present invention can be practiced in other ways besides the described embodiments. The described embodiments are presented for illustrative purposes and not for limiting purposes, and the present invention is limited only by the appended claims.

Claims

1. An integrated circuit device package comprising: a package structure having a base and a wall extending from the base; at least one integrated circuit die mounted to the package structure base within the wall, each of the at least one integrated circuit die having a top surface parallel to the base and each of the at least one integrated circuit die having a thickness extending perpendicular to the top surface along an axis, the thickness being at most equal to a height of the wall; a thermally conductive heat spreader extending parallel to the base over the at least one integrated circuit die and over the wall; and an interface layer comprising: an adhesive layer portion disposed between the wall and the heat spreader; and a thermal interface material (TIM) layer portion coplanar with and laterally displaced from the adhesive layer portion, the TIM layer portion disposed in thermally conductive relation between the heat spreader and each respective integrated circuit die of the at least one integrated circuit die to dissipate heat from each respective integrated circuit die to the heat spreader, wherein: the adhesive layer portion adheres the heat spreader to the wall and is configured to form a barrier between each integrated circuit die and the heat spreader to contain the flowable TIM layer portion.

2. The integrated circuit device package of claim 1, wherein the package structure comprises a molded package material.

3. The integrated circuit device package of claim 1, wherein the adhesive layer portion is thermally conductive.

4. The integrated circuit device package of claim 1, wherein a die from the at least one integrated circuit die is arranged in a stack of integrated circuit dies having a stack thickness perpendicular to the top surface, the stack thickness being at most equal to the height of the wall.

5. The integrated circuit device package of claim 1, wherein the TIM layer portion comprises any one of: (a) a polymer TIM, (b) a graphite TIM, (c) a metal TIM, and (d) a liquid metal TIM.

6. The integrated circuit device package of claim 1, wherein the adhesive layer portion surrounds the TIM layer portion in the interface layer.

7. The integrated circuit device package of claim 1, wherein: the TIM layer portion is flowable; and the adhesive layer portion surrounds the TIM layer portion in the interface layer.

8. The integrated circuit device package of claim 1, wherein the heat spreader comprises a flat lid.

9. The integrated circuit device package of claim 1, wherein the heat spreader comprises a forged lid.

10. The integrated circuit device package of claim 1, wherein the heat spreader comprises a stamped, hat-shaped lid. ​

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