Embedded micro-channel FCBGA packaging structure of high-power chip

Abstract

The utility model provides an embedded microchannel FCBGA packaging structure of a high power chip, which comprises an upper heat dissipation cover and a lower heat dissipation cover, the lower heat dissipation cover is provided with a microchannel structure for a working medium to flow, the microchannel structure comprises an inflow port, an outflow port and a heat dissipation unit, the heat dissipation unit comprises M water inlet flow channels and M water outlet flow channels, the water inlet flow channel and the water outlet flow channel are arranged in the first direction, the water inlet flow channel is used for communicating with the flow inlet, the water outlet flow channel is used for communicating with the flow outlet, an array structure is further arranged between the water inlet flow channel and the water outlet flow channel and comprises columnar pin fin structures arranged in the first direction and the second direction, and M is a positive integer larger than or equal to 1. N1 and N2 are positive integers greater than or equal to 2; a water inlet communicated with the inflow port and a water outlet communicated with the outflow port are further formed in the upper heat dissipation cover; the micro-channel structure is designed for the working medium to flow, so that heat generated when the chip works is brought out of the chip, and the chip is cooled.

Description

Technical Field

[0001] This utility model relates to chip packaging, and more particularly to an embedded microchannel FCBGA packaging structure for high-power chips. Background Technology

[0002] With the continuous reduction in the size of high heat flux density devices and the increasing number of transistors, the demand for heat dissipation in high-density, small-volume packaging has significantly increased. To meet the high reliability and stability requirements of high heat flux density devices during service, especially in key fields such as defense, aerospace, and biomedicine, how to effectively improve heat dissipation performance within limited space has become an urgent technical challenge.

[0003] High heat flux density devices, due to their high heat flux density per unit area, have increasingly seen thermal management failures become a major cause of device damage. Statistics show that approximately 55% of integrated circuit failures originate from thermal management issues. Excessively high temperatures significantly increase chip failure rates and shorten their average lifespan. Typically, for every 10°C increase in junction temperature, the device failure rate doubles.

[0004] There are many types of heat dissipation technologies for chips, among which air cooling is the most widely used solution. However, with the continuous advancement of semiconductor technology, the heat dissipation capacity of air cooling technology has approached its limit.

[0005] Water is the most commonly used working fluid for convective heat transfer, but its heat dissipation efficiency is insufficient to meet the ever-increasing demand for heat dissipation.

[0006] Therefore, it is necessary to design a new chip heat dissipation packaging structure. Utility Model Content

[0007] This invention provides an embedded microchannel FCBGA package structure for high-power chips, which aims to improve the poor heat dissipation performance of high-power chips.

[0008] To achieve the above objectives, embodiments of this utility model provide an embedded microchannel FCBGA package structure for high-power chips, comprising:

[0009] The device includes an upper heat sink and a lower heat sink, with the upper heat sink bonded to the top of the lower heat sink. The lower heat sink has a microchannel structure for the flow of working fluid. The microchannel structure includes an inlet, an outlet, and a heat dissipation unit. The heat dissipation unit includes M inlet channels and M outlet channels. The inlet channels and outlet channels are arranged along a first direction. The inlet channels are used to connect the inlet, and the outlet channels are used to connect the outlet. An array structure is also provided between the inlet channels and the outlet channels. The array structure includes N1 columnar needle rib structures arranged along the first direction and N2 columnar needle rib structures arranged along a second direction perpendicular to the first direction, where M is a positive integer greater than or equal to 1, and N1 and N2 are both positive integers greater than or equal to 2.

[0010] The upper heat dissipation cover is also provided with a water inlet that communicates with the inlet and a water outlet that communicates with the outlet.

[0011] The lower heat sink is attached to the upper surface of the chip via a thermal interface material, and the chip is connected to the substrate via solder balls.

[0012] Preferably, the number M of the inlet and outlet channels is the same as the number of channels formed by N2 columnar needle rib structures in the second direction.

[0013] Preferably, the working fluid is a nanofluid, and the nanomaterial is CUO, AL2O3, or FE2O3.

[0014] Preferably, the volume fraction of nanomaterials in the nanofluid is 0-5%.

[0015] Preferably, the inlet and outlet are rounded.

[0016] Preferably, the upper heat dissipation cover and the lower heat dissipation cover are made of copper, aluminum or silicon.

[0017] Preferably, the upper heat sink and the lower heat sink are bonded by one of the following methods: metal bonding, direct bonding, or high-temperature bonding.

[0018] The above-mentioned solution of this utility model has the following beneficial effects:

[0019] In this application, a microchannel structure is designed to allow the working fluid to flow, thereby carrying away the heat generated during chip operation and cooling the chip. Furthermore, the microchannel structure is embedded within the lower heat sink, which shortens the distance between the working fluid and the chip, improving heat dissipation efficiency by reducing thermal resistance.

[0020] In addition, the microchannel structure in this application includes an array structure, which ensures a sufficiently large contact area between the working fluid and the heat source, optimizes the temperature distribution of the chip, makes the chip temperature more uniform, effectively avoids the temperature gradient problem of the chip, and also promotes the heat dissipation of the chip.

[0021] Other features and advantages of this invention will be described in detail in the following detailed description section. Attached Figure Description

[0022] Figure 1 This is a cross-sectional view of the present invention;

[0023] Figure 2 This is a top view of the microchannel structure.

[0024] [Explanation of Labels in the Attached Image]

[0025] 1-Upper heat sink cover, 2-Lower heat sink cover, 3-Microchannel structure, 4-Thermal interface material, 5-Chip, 6-Solder ball, 7-Substrate, 8-Water inlet, 9-Water outlet, 31-Inlet, 32-Outlet, 33-Inlet channel, 34-Outlet channel, 35-Columnar pin rib structure. Detailed Implementation

[0026] To make the technical problems, technical solutions and advantages of this utility model clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0027] like Figure 1 and 2 As shown, an embodiment of this utility model provides an embedded microchannel FCBGA packaging structure for a high-power chip, including an upper heat sink 1, a lower heat sink 2, a chip 5, and a substrate 7. The upper heat sink 1 is bonded above the lower heat sink 2. The lower heat sink 2 has a microchannel structure 3, which includes an inlet 31, an outlet 32, and a heat dissipation unit. Specifically, the heat dissipation unit includes M inlet channels 33 and M outlet channels 34. The inlet channels 33 and the outlet channels 34 are arranged along a first direction. The inlet channels 33 are connected to the inlet 31, and the outlet channels 34 are connected to the outlet 32. An array structure is arranged between the inlet channels 33 and the outlet channels 34. The array structure includes N1 columnar pin rib structures 35 arranged along the first direction and N2 columnar pin rib structures 35 arranged along a second direction, which is perpendicular to the first direction. In this application, M is a positive integer greater than or equal to 1, and N1 and N2 are both positive integers greater than or equal to 2. That is, in this application, the number of water outlet channel 34 and water inlet channel 33 is at least one, and the columnar needle rib structure 35 set in the first direction and the second direction is at least two respectively.

[0028] Furthermore, the upper heat sink 1 is also provided with a water inlet 8 and a water outlet 9, wherein the water inlet 8 is used to communicate with the inlet 31, and the water outlet 9 is used to communicate with the outlet 32. The lower heat sink 2 is attached to the upper surface of the chip 5 by means of a thermal interface material 4, and the chip 5 is connected to the substrate 7 by means of solder balls 6. The connection between the chip 5, the solder balls 6, and the substrate 7 is prior art and will not be described in detail here.

[0029] Because the microchannel structure 3 is embedded within the lower heat sink 2, the distance between the microchannel structure 3 and the chip 5 is shorter, thus reducing thermal resistance during the flow of the working fluid and improving heat dissipation efficiency. The working fluid flows out from the inlet 8 and sequentially flows through the inlet 31, the inlet channel 33, the array structure, the outlet channel 34, the outlet 32, and the outlet 9. The continuous flow of the working fluid dissipates the heat generated by the chip 5.

[0030] Since the array structure includes multiple columnar pin rib structures 35 arranged in an array, the working fluid will flow along the first or second direction when it flows to the array structure, ensuring that there is a sufficiently large contact area between the working fluid and the chip 5. At the same time, it also optimizes the temperature distribution of the chip 5, making the temperature of the chip 5 more uniform, avoiding the temperature gradient problem of the chip 5, and also playing a role in improving the heat dissipation effect.

[0031] Furthermore, in this application, the number M of the outlet flow channels 34 and the number M of the inlet flow channels 33 are the same as the number of flow channels formed by the N2 columnar needle rib structures 35 in the second direction.

[0032] Specifically, in this embodiment, the water outlet channel 34 is formed by two channel sidewalls, and the water outlet channel 34 is located between two adjacent channel sidewalls. The water inlet channel 33 is set with reference to the water outlet channel 34. There are N2 columnar needle rib structures 35 in the second direction. The N2 columnar needle rib structures 35 and the M+1 channel sidewalls are aligned one by one in the first direction, so that the water inlet channel 33, the water outlet channel 34 and the channel in the first direction are collinear.

[0033] In this embodiment, N2 = 9, that is, 8 flow channels are formed between the columnar needle rib structures 35 in the first direction.

[0034] Furthermore, N1 columnar pin rib structures 35 are provided in the first direction, meaning that a total of N1*N2 columnar pin rib structures 35 are provided between the water outlet channel 34 and the water inlet channel 33, and the N1*N2 columnar pin rib structures 35 are arranged in a rectangular array. The multiple arrays of spaced columnar pin rib structures 35 provide more flow paths for the working fluid, ensuring sufficient contact area between the working fluid and the chip 5. It is understood that the number of N1 and N2 is positively correlated with the heat dissipation effect. Preferably, the columnar pin rib structures 35 are arranged at equal intervals in the first and second directions.

[0035] In this application, the working fluid is a nanofluid, and the nanomaterial is one of CuO, Al2O3, or Fe2O3, with a volume fraction of 0-5% in the nanofluid. It is understood that when the volume fraction of the nanomaterial in the nanofluid is 0, it represents deionized water as the working fluid.

[0036] In this application, a highly thermally conductive nanofluid is used as the working fluid, which has better thermal conductivity than conventional deionized water. However, due to the high viscosity of the nanofluid, its flow can be affected in conventional heat dissipation channels. In this application, the microchannel structure 3 can overcome the limitation caused by the high viscosity of the nanofluid by reducing the flow rate, thus fully utilizing the thermal conductivity of the nanofluid.

[0037] Preferably, in this embodiment, the upper heat sink 1 and the lower heat sink 2 are made of copper, aluminum, or silicon. The bonding method between the upper heat sink 1 and the lower heat sink 2 is one of metal bonding, direct bonding, or high-temperature bonding.

[0038] Preferably, the inlet 8 and outlet 9 are rounded.

[0039] The above description is the preferred embodiment of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.

Claims

1. An embedded micro-channel FCBGA package structure for high power chips, characterized in that, The application relates to a heat dissipation cover, which comprises an upper heat dissipation cover (1) and a lower heat dissipation cover (2), the upper heat dissipation cover (1) is bonded above the lower heat dissipation cover (2), the lower heat dissipation cover (2) is provided with a micro-channel structure (3) for flowing of working medium, the micro-channel structure (3) comprises a flow inlet (31), a flow outlet (32) and a heat dissipation unit, the heat dissipation unit comprises M water inlet flow channels (33) and M water outlet flow channels (34), the water inlet flow channels (33) and the water outlet flow channels (34) are arranged along a first direction, the water inlet flow channels (33) are used for being connected with the flow inlet (31), the water outlet flow channels (34) are used for being connected with the flow outlet (32), and an array structure is further arranged between the water inlet flow channels (33) and the water outlet flow channels (34), the array structure comprises N1 columnar needle rib structures (35) arranged along the first direction and N2 columnar needle rib structures (35) arranged along a second direction perpendicular to the first direction, wherein M is a positive integer greater than or equal to 1, and N1 and N2 are positive integers greater than or equal to 2. The upper heat dissipation cover (1) is further provided with a water inlet (8) communicated with the flow inlet (31) and a water outlet (9) communicated with the flow outlet (32). The lower heat dissipation cover (2) is attached to the upper surface of a chip (5) through a thermal interface material (4), and the chip (5) is connected to a substrate (7) through tin balls (6). The number M of the water inlet flow channels (33) and the water outlet flow channels (34) is the same as the number of flow channels formed by the N2 columnar needle rib structures (35) in the second direction.

2. The embedded micro-channel FCBGA package structure for high power die of claim 1, wherein, The working medium is a nanofluid, and the nanomaterial is CUO, AL2O3 or FE2O3.

3. The embedded micro-channel FCBGA package structure for high power die of claim 1, wherein: The water inlet (8) and the water outlet (9) are chamfered.

4. The embedded micro-channel FCBGA package structure for high power die of claim 1, wherein: The upper heat dissipation cover (1) and the lower heat dissipation cover (2) are one of copper, aluminum and silicon.

5. The embedded micro-channel FCBGA package structure for high power die of claim 1, wherein: The bonding mode of the upper heat dissipation cover (1) and the lower heat dissipation cover (2) is one of metal bonding, direct bonding and high-temperature bonding.

6. The embedded micro-channel FCBGA package structure for high power die of claim 5, wherein: ​

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