Chip and replaceable accessory

Abstract

The utility model provides a chip and a replaceable accessory, the chip comprises a communication contact and a connecting part which are electrically connected with a port of host equipment, the connecting part comprises a resistive component, and the resistivity of the resistive component is greater than that of the communication contact; the first contact part is used for being electrically connected with a first port of host equipment and receiving a power signal output by the first port; the second contact part is used for being electrically connected with a second port of the host equipment and receiving a non-power signal output by the second port; the leading-out part is electrically connected with the first contact part and the second contact part respectively and outputs a superposed signal of the power supply signal and the non-power supply signal; the connecting part forms a first conductive path between the first contact part and the lead-out part, the connecting part forms a second conductive path between the second contact part and the lead-out part, and the first conductive path and the second conductive path are respectively provided with at least part of resistive components; wherein the length of the first conductive path is smaller than that of the second conductive path.

Description

[0001] This application claims priority to the following Chinese patent applications, the contents of which are incorporated herein by reference in their entirety.

[0002] 1. Application date: 2024-05-07; Application number: 202410558529.9; Application title: A consumable chip and a consumable box;

[0003] 2. Application date: 2024-05-15; Application number: 202410607700.0; Application title: A consumable chip and a consumable box;

[0004] 3. Application date: 2024-06-12; Application number: 202410756520.9; Application title: A consumable chip and a consumable box. TECHNICAL FIELD

[0005] The present application relates to the field of electronic technology, in particular to a chip and a replaceable accessory. BACKGROUND

[0006] In order to enrich the characteristics of the host device, the host device often uses some peripheral replaceable accessories. When the replaceable accessory is used on the host device, the host device often needs to authenticate the source of the replaceable accessory. On the replaceable accessory, a chip for identity authentication is often included, and authentication information is stored in the chip. In addition, the use history or service life of the replaceable accessory is also stored in the chip. The host device can be an image forming device, a mobile terminal, a computer, etc., and correspondingly, the replaceable accessory can be a consumable box, earphones, a battery, a peripheral device, etc., which contains a chip.

[0007] On the host device and the chip, corresponding communication ports are respectively configured. Specifically, the communication port can include a data port, a chip select port, a clock port, a power port and a ground port. When the replaceable accessory is installed on the host device, the data port, the chip select port, the clock port, the power port and the ground port on the host device are respectively electrically connected with the data port, the chip select port, the clock port, the power port and the ground port on the chip, so as to realize the transmission of data signals, chip select signals, clock signals, power signals and ground signals.

[0008] In some applications, the current output from the host device's power port may be insufficient to drive the chip, leading to host device malfunction. To address this issue, one solution involves electrically connecting the chip's power port not only to the host device's power port but also to other ports on the host device. Specifically, a connection portion is provided on the chip, simultaneously connecting multiple communication ports on the host device that include power ports. A point on this connection portion (referred to as a "lead-out") is electrically connected to the chip's power port. This connection method allows multiple communication ports on the host device to supply power to the chip's power port, thereby increasing the input current to the chip's power port.

[0009] However, if the position of the lead-out part in the connection part is not set properly, it may increase the voltage division ratio of the resistor on the power signal transmission path in the connection part, thereby increasing the voltage drop on the power signal transmission path and affecting the stability and reliability of the chip.

[0010] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0011] This application provides a chip and a replaceable accessory to solve the problem in the prior art where the unreasonable placement of the lead-out portion in the connection part may increase the voltage division ratio of the resistor in the power signal transmission path of the connection part, thereby increasing the voltage drop in the power signal transmission path and affecting the stability and reliability of the chip.

[0012] In a first aspect, embodiments of this application provide a chip for communication connection with a host device, characterized in that the chip includes communication contacts and a connection portion electrically connected to ports of the host device, the ports of the host device including a first port and a second port, and the connection portion including: a resistive component, the resistivity of the resistive component being greater than the resistivity of the communication contact; a first contact portion for electrically connecting to the first port and receiving a power signal output from the first port; a second contact portion for electrically connecting to the second port and receiving a non-power signal output from the second port; and a lead-out portion for electrically connecting to the first contact portion and the second contact portion, the lead-out portion being used to output a superimposed signal of the power signal and the non-power signal, and controlling a functional module in the chip to achieve a function matching the power signal and the non-power signal through the superimposed signal; the connection portion forming a first conductive path between the first contact portion and the lead-out portion, and the connection portion forming a second conductive path between the second contact portion and the lead-out portion, wherein at least a portion of the resistive component is respectively disposed on the first conductive path and the second conductive path; wherein the length of the first conductive path is less than the length of the second conductive path.

[0013] In one possible implementation, the communication contact has a contact portion that makes contact with a port of the host device; when viewed from above the chip substrate or the pin holder of the host device, with two orthogonal straight lines designated as a first imaginary line and a second imaginary line, the contact portions of all the communication contacts are projected onto the second imaginary line, the first imaginary line passes between the two farthest projection positions of all the contact portions, and when one region is designated as a first region and the other region as a second region relative to the first imaginary line, both the first contact portion and the second contact portion are located within the first region; the contact portion further includes a ground contact portion located within the second region.

[0014] In one possible implementation,

[0015] The first conductive path has a first equivalent width, and the second conductive path has a second equivalent width; wherein the ratio of the length of the first conductive path to the first equivalent width is less than the ratio of the length of the second conductive path to the second equivalent width. In one possible implementation, the first conductive path and the second conductive path are not collinear.

[0016] In one possible implementation, the connection portion includes: a conductive region, the resistive component located within the conductive region, and the first contact portion and the second contact portion located within the conductive region, with the lead-out portion located on one side of the conductive region; wherein the equivalent resistance of the first conductive path is less than the equivalent resistance of the second conductive path.

[0017] In one possible implementation, the connection portion includes: a conductive region, the resistive component being located within the conductive region, and the first contact portion, the second contact portion, and the lead-out portion being located within the conductive region; the conductive region includes: a first conductive sub-region having a first resistivity, the first contact portion and the second contact portion being located within the first conductive sub-region; and a second conductive sub-region having a second resistivity greater than the first resistivity, the lead-out portion being located within the second conductive sub-region; wherein the resistivity of the first conductive sub-region is less than the resistivity of the second conductive sub-region.

[0018] In one possible implementation,

[0019] The connecting portion includes: the first equivalent width is greater than or equal to the second equivalent width.

[0020] In one possible implementation, the non-power signal is a chip select signal, a clock signal, or a data signal.

[0021] Secondly, embodiments of this application provide a replaceable accessory, including the chip described above.

[0022] In this embodiment, by rationally designing the shape of the connection portion and the position of the lead-out portion, the voltage division ratio of the resistors on the power signal transmission path between the first contact portion and the lead-out portion is reduced. It is understood that by reducing the voltage division ratio of the resistors on the power signal transmission path, the voltage drop on the power signal transmission path can be reduced, ensuring that the functional module can obtain a more stable power supply, thereby improving the stability and reliability of the chip. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A structural block diagram of a communication system provided in an embodiment of this application;

[0025] Figure 2This application provides a schematic diagram illustrating the connection relationship between a host device and a chip, as shown in the embodiments of the present application.

[0026] Figure 3 This is a schematic diagram of the structure of a stylus holder for a host device provided in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of a replaceable accessory provided in an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0029] Figure 6 A partial structural diagram of a data stylus provided in an embodiment of this application;

[0030] Figure 7 This is a schematic diagram of the structure of the first type of chip provided in the embodiments of this application;

[0031] Figure 8 An equivalent circuit diagram of a connection portion provided in an embodiment of this application;

[0032] Figure 9 This is a schematic diagram of the structure of the third type of chip provided in the embodiments of this application;

[0033] Figure 10 This is a schematic diagram of the structure of the fourth type of chip provided in the embodiments of this application;

[0034] Figure 11 This is a schematic diagram of the structure of the fifth type of chip provided in the embodiments of this application;

[0035] Figure 12 This is a schematic diagram of the structure of the sixth type of chip provided in the embodiments of this application;

[0036] Figure 13 This is a schematic diagram of the structure of the seventh type of chip provided in the embodiments of this application;

[0037] Figure 14 This is a schematic diagram of the structure of the eighth type of chip provided in the embodiments of this application;

[0038] Figure 15 A schematic diagram of the circuit structure of the first type of chip provided in the embodiments of this application;

[0039] Figure 16 This is a schematic diagram of the circuit structure of the second type of chip provided in an embodiment of this application. Detailed Implementation

[0040] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0041] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0042] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0043] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0044] See Figure 1 This is a structural block diagram of a communication system provided in an embodiment of this application. Figure 1 As shown, the communication system includes a host device 10 and a replaceable accessory 20, with a chip 21 mounted on the replaceable accessory 20. Both the host device 10 and the chip 21 are equipped with corresponding communication ports. When the replaceable accessory 20 is installed on the host device 10, the communication ports of the host device 10 and the chip 21 are electrically connected, establishing a communication link between them. Information can be transmitted between the host device 10 and the chip 21 through this communication link. Specifically, when the host device 10 sends a signal to the chip 21, the host device 10 is the sender and the chip 21 is the receiver; conversely, when the chip 21 sends a signal to the host device 10, the chip 21 is the sender and the host device 10 is the receiver.

[0045] In a specific implementation, the host device 10 can be an image forming apparatus, a mobile terminal, a computer, or other similar devices, while the replaceable accessory 20 can be a consumable box, earphones, a battery, peripherals, or other similar modules. The chip 21 can store identity data, encrypted data, and remaining lifespan data. The host device 10 can authenticate the replaceable accessory 20 using the identity data, achieve encrypted communication between the host device 10 and the chip 21 using the encrypted data, and determine the remaining lifespan of the replaceable accessory 20 using the remaining lifespan data.

[0046] For example, the host device 10 is an image forming apparatus, and correspondingly, the replaceable accessory 20 is a consumable cartridge, with remaining service life data representing consumable reserves. See also Figure 2This is a schematic diagram illustrating the connection relationship between a host device and a chip, provided in an embodiment of this application. Figure 2 As shown, the communication ports on the host device 10 and chip 21 include a data port (SDA), a chip select port (RST), a clock port (SCL), a power port (VCC), and a ground port (GND), respectively. When the replaceable accessory 20 is installed on the host device 10, the data port, chip select port, clock port, power port, and ground port on the host device 10 are connected one-to-one with the data port, chip select port, clock port, power port, and ground port on the chip 21, thereby enabling the transmission of data signals, chip select signals, clock signals, power signals, and ground signals. Among them, the chip select signal is a key signal to ensure orderly communication in a multi-chip system, avoiding bus conflicts by selecting a specific chip; the clock signal is a periodic signal with alternating high and low levels; the power signal provides the operating voltage for the chip 21; and the ground signal provides a unified reference low level between the host device 10 and the chip 21, ensuring the correctness and stability of the communication process.

[0047] See Figure 3 This is a schematic diagram of the structure of a host device's pin holder provided in an embodiment of this application. For ease of description, in... Figure 3 The X, Y, and Z directions are defined as mutually perpendicular. For example... Figure 3 As shown, the pin holder 11 includes an upper pin holder surface 111 in the Y-axis arrow direction, a front pin holder surface 112 in the X-axis arrow direction, and data pins 1101, chip select pins 1102, clock pins 1103, power pins 1104, and ground pins 1105 staggered along the Z-axis direction. The data pins 1101, chip select pins 1102, clock pins 1103, power pins 1104, and ground pins 1105 are respectively connected to the data port, chip select port, clock port, power port, and ground port on the host device 10.

[0048] See Figure 4 This is a structural schematic diagram of a replaceable accessory provided in an embodiment of this application. Figure 4 As shown, the replaceable accessory 20 includes a replaceable accessory body 201, and a chip 21 is provided on the outer surface of the replaceable accessory body 201. It should be noted that... Figure 4 The structure of the replaceable accessory body 201 and the location of the chip 21 on the replaceable accessory body 201 shown in the replaceable accessory 20 are merely illustrative examples of embodiments of this application and should not be construed as limiting the scope of protection of this application.

[0049] See Figure 5 This is a schematic diagram of a chip structure provided in an embodiment of this application. Figure 5As shown, chip 21 includes a data contact 21011, a chip select contact 21012, a clock contact 21013, a power contact 21014, and a ground contact 21015. Additionally, chip 21 typically includes functional modules to implement data storage, processing, and other related functions. Specifically, these functional modules may include a control unit, a storage unit, etc. The control unit is used to control communication with the host device; it can be a microcontroller (MCU), microprocessor, FPGA, or ASIC. The storage unit can use common non-volatile storage units (e.g., EPROM, EEPROM, FLASH, ferroelectric storage units, phase-change storage units, etc.), or it can use volatile storage units combined with a power supply (e.g., SRAM with a battery or capacitor, DRAM with a battery or capacitor, etc.).

[0050] In this embodiment, the data port, chip select port, clock port, power port, and ground port on chip 21 specifically refer to the data port, chip select port, clock port, power port, and ground port on the functional module of chip 21. Data contact 21011, chip select contact 21012, clock contact 21013, power contact 21014, and ground contact 21015 are respectively connected to the data port, chip select port, clock port, power port, and ground port on the functional module; preferably, these contacts are disposed on communication contacts, and preferably, the communication contacts include copper plating.

[0051] When the replaceable accessory 20 is installed on the host device 10, the data pin 1101, chip select pin 1102, clock pin 1103, power pin 1104 and ground pin 1105 of the host device 10 make contact with the data contact 21011, chip select contact 21012, clock contact 21013, power contact 21014 and ground contact 21015 on the chip 21, respectively, thereby establishing a communication link between the host device 10 and the chip 21.

[0052] See Figure 6 The image provided is a partial structural diagram of a data stylus, exemplarily provided in an embodiment of this application. Figure 6As shown, the data pin 1101 includes a data pin tip 11011, a data pin front end 11012, a data pin bevel end 11013, and a data pin tip 11014. In specific implementations, the data pin tip 11014 typically forms contact with the data contact portion 21011 on the chip 21 to achieve electrical connection between the data pin 1101 and the data contact portion 21011. Of course, those skilled in the art can also form contact with the data contact portion 21011 on the chip 21 through the data pin tip 11011, the data pin front end 11012, or the data pin bevel end 11013 to achieve electrical connection between the data pin 1101 and the data contact portion 21011, depending on actual needs. This application embodiment does not impose specific limitations in this regard.

[0053] In some application scenarios, the current output through the power port of the host device 10 may not be able to drive the functional modules in the chip 21, thus causing the host device 10 to malfunction. To address this issue, one solution in the related technology is that the power port of the chip 21 is electrically connected not only to the power port of the host device 10, but also to other ports of the host device 10.

[0054] Specifically, a connection portion is provided on chip 21, through which multiple communication ports, including power ports, of the host device 10 are simultaneously connected. A point on the connection portion (referred to as the "lead-out portion" for ease of description) is electrically connected to the power port of a functional module in chip 21. It can be understood that through this connection method, the multiple communication ports, including power ports, of the host device 10 can supply power to the power port of the functional module, thereby increasing the input current of the power port of the functional module.

[0055] See Figure 7 This is a schematic diagram of a chip structure provided in an embodiment of this application. Figure 7 As shown, the chip 21 includes a substrate 210, and the substrate 210 includes a first plane 2101. A connection portion 21016 is provided on the first plane 2101. The connection portion 21016 includes a first contact portion 210161, a second contact portion 210162, and a lead-out portion 210163. The first contact portion 210161 and the second contact portion 210162 are electrically connected to the lead-out portion 210163, respectively.

[0056] In this embodiment, the connection portion 21016 includes a resistive component, such as a resistor or a carbon film, wherein the resistivity of the resistive component is greater than the resistivity of the communication contact provided on the substrate 210 that is electrically connected to the port of the host device 10.

[0057] In this embodiment, the first contact portion 210161 is electrically connected to the first port of the host device 10 to receive a first signal (power signal) output from the first port of the host device 10; the second contact portion 210162 is electrically connected to the second port of the host device 10 to receive a second signal (non-power signal) output from the second port of the host device 10. The first end of the lead-out portion 210163 is electrically connected to the first contact portion 210161 and the second contact portion 210162 respectively to obtain a superimposed signal composed of the first signal (power signal) and the second signal (non-power signal). Specifically, the first port is a power port, and the second port is a non-power port. That is, the superimposed signal is a signal composed of the power signal and the non-power signal output by the host device 10.

[0058] Furthermore, chip 21 also includes a functional module 21021 to implement data storage, processing, and other related functions. Specifically, the functional module may include a control unit, a storage unit, etc. The second end of lead-out portion 210163 is electrically connected to the first port (i.e., power port) of functional module 21021 so as to supply power to the power port of functional module 21021 through a superimposed signal. Since the superimposed signal includes current from both power and non-power signals, the current of the superimposed signal is larger. By supplying power to the power port of functional module 21021 through the superimposed signal, the input current of the power port of functional module 21021 can be increased.

[0059] In one possible implementation, the connecting portion 21016 includes a conductive region, and the first contact portion 210161 and the second contact portion 210162 are located within the conductive region; the lead-out portion 210163 may be located within the conductive region or on one side of the conductive region. It is understood that the conductive region enables the first contact portion 210161 and the second contact portion 210162 to be electrically connected to the lead-out portion 210163, respectively.

[0060] In practice, the conductive area can be formed from carbon materials, specifically carbon film or carbon oil. Carbon film or carbon oil is a thin-film resistive material that can be prepared using processes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Due to the relatively high resistivity of carbon film or carbon oil, if the position of the lead-out portion 210163 is not properly chosen, or if the shape of the carbon film or carbon oil causes an excessively large equivalent resistance on the power signal transmission path, a significant voltage drop may occur on the power signal transmission path (between the first contact portion 210161 and the lead-out portion 210163), thereby affecting the stability and reliability of the functional module 21021.

[0061] In the embodiments of this application, preferably, a carbon film or carbon oil of uniform material and thickness can be used, which facilitates the control of the equivalent resistance on the power signal transmission path by controlling the position of the lead-out portion 210163 during processing, and further controls the voltage drop generated on the power signal transmission path; those skilled in the art should understand that the equivalent resistance on the power signal transmission path can also be controlled by using a carbon film or carbon oil of non-uniform material and thickness, by combining resistivity and other factors.

[0062] It should be noted that, in addition to carbon materials, other conductive materials may also be used to prepare the conductive regions. This application does not impose specific restrictions on the materials used to prepare the conductive regions.

[0063] See Figure 8 This is an equivalent circuit diagram of a connection portion provided in an embodiment of this application. Figure 8As shown, in the connection portion 21016, the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 is the first resistance R1, and the equivalent resistance between the second contact portion 210162 and the lead-out portion 210163 is the second resistance R2. It is understood that the placement of the lead-out portion 210163 in the conductive region affects the resistance values ​​of the first resistance R1 and the second resistance R2. Those skilled in the art will understand that the equivalent resistance on the transmission path of the connection portion 21016 is generally affected by the length of the transmission path. When the carbon film or carbon oil thickness is uniform, the equivalent resistance is proportional to the length of the transmission path. If the position of the lead-out portion 210163 is unreasonable, or if the shape (width) of the carbon film or carbon oil is unreasonable, it may increase the resistance on the power signal transmission path (between the first contact portion 210161 and the lead-out portion 210163) in the connection portion 21016, i.e., the first resistance R1. It is understandable that when the first signal is high and the second signal is low, the larger the voltage division ratio of the first resistor R1 in the total resistance of the first resistor R1 and the second resistor R2, the larger the voltage drop on the power signal transmission path. A large voltage drop on the power signal transmission path may cause the voltage of the superimposed signal output by the lead-out section 210163 to be too low. If the voltage of the superimposed signal is less than the minimum operating voltage of the functional module 21021, the functional module 21021 may not work properly, resulting in poor stability and reliability of the functional module 21021. For example, when the first port of the host device 10 outputs a high level (voltage V1) and the second port outputs a low level (voltage is a reference voltage lower than the high level, generally considered to be between 0V and 1.5V; in some embodiments, this voltage approaches 0V. For the convenience of subsequent superimposed voltage calculation, we take 0V for the low level. Those skilled in the art will understand that treating the voltage as 0V in the low level in subsequent embodiments is for the convenience of illustrating the embodiments and should not be regarded as a limitation of this application), the voltage V of the superimposed signal output by the lead-out portion 210163 is V = (R2 / (R1+R2)) × V1. It can be understood that the larger the first resistor R1, the smaller the voltage V of the lead-out portion 210163. If the voltage V of the lead-out portion 210163 is lower than the minimum operating voltage of the functional module 21021, it may cause the functional module 21021 to malfunction.

[0064] To solve the above problems, in this embodiment of the application, by reasonably designing the position of the lead-out portion 210163, the connecting portion 21016 forms a first conductive path between the first contact portion 210161 and the lead-out portion 210163, and the connecting portion 21016 forms a second conductive path between the second contact portion 210162 and the lead-out portion 210163, wherein the length of the first conductive path is less than the length of the second conductive path.

[0065] In the embodiments of this application, by controlling the length of the conductive path, the equivalent resistance (first resistance R1) between the first contact 210161 and the lead-out portion 210163 is further controlled to be less than the equivalent resistance (second resistance R2) between the second contact 210162 and the lead-out portion 210163, thereby reducing the voltage division ratio of the resistors on the power signal transmission path and directly controlling the length of the conductive path, which is easy to implement in terms of technology. Preferably, in one embodiment, the thickness and width of the carbon film or carbon oil selected on the conductive path are uniform. In other embodiments, the thickness and width of the carbon film or carbon oil may also be non-uniform. In addition to controlling the length of the conductive path, other parameters are adjusted to control the relationship between the first resistance R1 and the second resistance R2.

[0066] Preferably, the equivalent resistance is also inversely proportional to the width of the transmission path, with the first conductive path having a first equivalent width and the second conductive path having a second equivalent width; wherein the ratio of the length of the first conductive path to the first equivalent width is less than the ratio of the length of the second conductive path to the second equivalent width.

[0067] In the embodiments of this application, the equivalent width refers to the width of the material in the direction of current transmission. When the material width is not uniform, the average width of the material in the direction of current transmission can be calculated.

[0068] In the embodiments of this application, by controlling the ratio of the length of the first conductive path to its equivalent width to be less than the ratio of the length of the second conductive path to its equivalent width, the equivalent resistance (first resistance R1) between the first contact 210161 and the lead-out portion 210163 is further controlled to be less than the equivalent resistance (second resistance R2) between the second contact 210162 and the lead-out portion 210163, thereby reducing the voltage division ratio of the resistors on the power signal transmission path. It can be understood that by reducing the voltage division ratio of the resistors on the power signal transmission path, the voltage drop on the power signal transmission path can be reduced, ensuring that the functional module 21021 can obtain a more stable power supply, thereby improving the stability and reliability of the functional module 21021.

[0069] For example, by rationally designing the position of the lead-out portion 210163, the resistance values ​​of the first resistor R1 and the second resistor R2 are 1kΩ and 3kΩ, respectively. When the first port of the host device 10 outputs a high level (voltage of 3.3V) and the second port outputs a low level (voltage of 0V), the voltage V of the superimposed signal output by the lead-out portion 210163 is approximately 2.5V (3 / (1+3))×3.3. If the minimum operating voltage of the functional module 21021 is 2.1V, the above-mentioned distribution of the resistance values ​​of the first resistor R1 and the second resistor R2 can ensure that the voltage of the lead-out portion 210163 is always greater than the minimum operating voltage of the functional module 21021, thereby improving the stability and reliability of the chip 21.

[0070] In this embodiment, the second port is a chip select port, and correspondingly, the second signal is a chip select signal. That is, the chip 21 can be connected to the power port of the host device 20 through the first contact 210161 of the connection part 21016, and connected to the chip select port of the host device 20 through the second contact 210162 of the connection part 21016.

[0071] As mentioned above, in addition to the power port and chip select port, the communication ports of the host device 20 also include a data port, a clock port, and a ground port. Figure 7 As shown, corresponding to the data port, clock port, and ground port of the host device, a data contact 21011, a clock contact 21013, and a ground contact 21015 are also provided on the first plane 2101 of the chip 21. The data contact 21011, the clock contact 21013, and the ground contact 21015 are respectively used for electrical connection with the data port, clock port, and ground port of the host device 10.

[0072] It is understandable that if the resistivity of the conductive region is uniform, then within the conductive region, the longer the distance between two points, the greater the equivalent resistance. Based on this principle, the distance between the first contact portion 210161 and the lead-out portion 210163 can be set to be smaller than the distance between the second contact portion 210162 and the lead-out portion 210163, so that the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 is less than the equivalent resistance between the second contact portion 210162 and the lead-out portion 210163.

[0073] For example, in Figure 7 In the first contact portion 210161 and the lead-out portion 210163, the distance between them is D1 (referred to as "first distance D1" for ease of description), and the distance between them is D2 (referred to as "second distance D2" for ease of description), wherein D1 < D2.

[0074] In the embodiments of this application, such as Figure 7 As shown, on the conductive path of segment D1, the equivalent width of the carbon film is greater than the equivalent width of the carbon film path on the conductive path of segment D2. Therefore, by ensuring that the ratio of the length of the first conductive path to the equivalent width is less than the ratio of the length of the second conductive path to the equivalent width, the equivalent resistance (first resistance R1) between the first contact 210161 and the lead-out portion 210163 is further controlled to be less than the equivalent resistance (second resistance R2) between the second contact 210162 and the lead-out portion 210163.

[0075] See Figure 7When viewing the chip substrate 210 or the pin holder 11 of the host device from above, with two orthogonal straight lines designated as the first imaginary line W1 and the second imaginary line W2, all communication contacts are projected onto the second imaginary line W2. The first imaginary line W1 passes through the midpoint between the two farthest projection positions of all communication contacts. Figure 7 As shown, the clock contact 21013 and the ground contact 21015 pass between them. When one region is designated as the first region and the other region as the second region relative to the first imaginary line W1, both the first contact 210161 and the second contact 210162 are located within the first region; the ground contact 21015 is located within the second region.

[0076] With the above arrangement, the connecting part 21016 is set on two contact parts in the same area. First, it can avoid the connecting part 21016 having too large a span, which would increase the difficulty of processing. Second, the connecting part 21016 is far away from the grounding contact part 21015 in the second area, which avoids the possibility of short circuit between the grounding contact part 21015 and the connecting part 21016 during processing or use.

[0077] In practical applications, the replaceable accessory 20 is typically installed or removed from the host device 10 by sliding. During this sliding process, the pins on the host device 10 rub against the contacts on the chip, which may cause the positions of the first contact 210161 and the second contact 210162 to shift. It is understood that this shift in position will cause changes in the resistance values ​​of the first resistor R1 and the second resistor R2, potentially affecting the voltage division ratio of the resistors along the power signal transmission path.

[0078] To reduce the impact of the positional shift of the first contact portion 210161 and the second contact portion 210162 on the voltage division ratio of the resistors along the power signal transmission path, embodiments of this application differentiate the resistivity of the first contact portion 210161 and / or the second contact portion 210162 themselves, or the resistivity of the conductive region where the first contact portion 210161 and / or the second contact portion 210162 are located. This will be described below in conjunction with the accompanying drawings.

[0079] See Figure 9 This is a schematic diagram of a chip structure provided in an embodiment of this application. In this embodiment, the resistivity of the first contact portion 210161 and / or the second contact portion 210162 is differentiated, such that the resistivity of the first contact portion 210161 and / or the second contact portion 210162 is less than the resistivity of the conductive region.

[0080] Since a smaller resistivity corresponds to a smaller resistance value per unit distance, configuring the first contact portion 210161 and / or the second contact portion 210162 with a smaller resistivity can reduce the resistance deviation of the first resistor R1 and / or the second resistor R2 caused by the positional offset of the first contact portion 210161 and / or the second contact portion 210162, thereby improving the stability of the voltage division ratio of the resistors on the power signal transmission path.

[0081] See Figure 10 This is a schematic diagram of a chip structure provided in an embodiment of this application. In this embodiment, the conductive region is divided into a first conductive sub-region 21016A and a second conductive sub-region 21016B. The first contact portion 210161 and the second contact portion 210162 are located within the first conductive sub-region 21016A, and the lead-out portion 210163 is located within the second conductive sub-region 21016B. The resistivity of the first conductive sub-region 21016A is less than the resistivity of the second conductive sub-region 21016B. In other words, the resistivity of the conductive region containing the first contact portion 210161 and the second contact portion 210162 is less than the resistivity of the conductive region containing the lead-out portion 210163.

[0082] In one embodiment of this application, as Figure 10 In one modified embodiment, region "21016B" is a non-conductive region, and lead-out portion 210163 is connected to the first conductive sub-region 21016A via a wire. That is, lead-out portion 210163 is disposed on one side of the first conductive sub-region 21016A, and a first distance D1 and a second distance D2 are formed on the transmission path. In this case, when considering the first conductive path, only the length of the first contact portion 210161 and the second contact portion 210162 extending out of the first conductive sub-region 21016A to lead-out portion 210163 should be considered, without considering the length of the wire. Therefore, the conductive path referred to in this embodiment refers to the formation at the connection portion 21016.

[0083] Since a smaller resistivity corresponds to a smaller resistance value per unit distance, configuring the conductive areas where the first contact portion 210161 and the second contact portion 210162 are located with a smaller resistivity can reduce the resistance value deviation of the first resistor R1 and / or the second resistor R2 caused by the positional offset of the first contact portion 210161 and / or the second contact portion 210162, thereby improving the stability of the voltage division ratio of the resistors on the power signal transmission path.

[0084] See Figure 11 This is a schematic diagram of a chip structure provided in an embodiment of this application. This embodiment is related to... Figure 10The difference in the illustrated embodiment lies in that the first conductive electronic region 21016A is further divided into a third conductive electronic region 21016A1 and a fourth conductive electronic region 21016A2. Specifically, the first contact portion 210161 is located within the third conductive electronic region 21016A1, and the second contact portion 210162 is located within the fourth conductive electronic region 21016A2. In other words, the first contact portion 210161 and the second contact portion 210162 are located within different conductive electronic regions. Therefore, the resistivity of the conductive regions containing the first contact portion 210161 and the second contact portion 210162 can be configured more flexibly to meet the resistivity configuration requirements of different application scenarios.

[0085] Specifically, the third conductive electronic region 21016A1 and the fourth conductive electronic region 21016A2 can be configured with different resistivities. For example, the resistivity of the third conductive electronic region 21016A1 is less than the resistivity of the fourth conductive electronic region 21016A2. In this embodiment, since the first contact portion 210161 is located within the third conductive electronic region 21016A1, configuring the resistivity of the third conductive electronic region 21016A1 to be less than the resistivity of the fourth conductive electronic region 21016A2 can minimize the equivalent resistance (first resistance R1) between the first contact portion 210161 and the lead-out portion 210163, thereby reducing the voltage division ratio of the resistors on the power signal transmission path.

[0086] Of course, those skilled in the art can also configure the resistivity of the third conductive region 21016A1 to be greater than that of the fourth conductive region 21016A2, or configure the third conductive region 21016A1 and the fourth conductive region 21016A2 to have the same resistivity, and the embodiments of this application do not impose specific limitations on this.

[0087] See Figure 12 This is a schematic diagram of a chip structure provided in an embodiment of this application. This embodiment is related to... Figure 7 - Figure 11 The difference in the illustrated embodiment is that the connecting portion 21016 includes a first conductive path and a second conductive path. The first contact portion 210161 is electrically connected to the lead-out portion 210163 through the first conductive path; the second contact portion 210162 is electrically connected to the lead-out portion 210163 through the second conductive path. That is, the electrical connection between the first contact portion 210161 and the second contact portion 210162 and the lead-out portion 210163 is achieved through the conductive paths.

[0088] In practice, the first and second conductive paths can be formed of carbon materials, specifically carbon film or carbon oil. Since the resistivity (resistance per unit distance on the surface of the carbon film or carbon oil) of the carbon film or carbon oil is relatively high, if the position of the lead-out portion 210163 is not properly selected, a large voltage drop may occur on the power signal transmission path (the first conductive path), thereby affecting the stability and reliability of the functional module 21021.

[0089] It should be noted that, in addition to carbon materials, the first and second conductive paths may also be prepared using other conductive materials. This application does not impose specific restrictions on the materials used to prepare the first and second conductive paths.

[0090] In one possible implementation, the length L1 of the first conductive path is less than the length L2 of the second conductive path. It is understood that when the width of the conductive path is relatively uniform, the longer the conductive path, the greater its equivalent resistance. Therefore, by setting the length L1 of the first conductive path to be less than the length L2 of the second conductive path, the equivalent resistance between the first contact 210161 and the lead-out 210163 can be made less than the equivalent resistance between the second contact 210162 and the lead-out 210163.

[0091] In practical applications, when the length L1 of the first conductive path is less than the length L2 of the second conductive path, the distance (straight-line distance, i.e., the first distance D1) between the first contact 210161 and the lead-out portion 210163 may also be greater than or equal to the distance (straight-line distance, i.e., the second distance D2) between the second contact 210162 and the lead-out portion 210163.

[0092] For example, in Figure 12 In this context, L1 < L2, and D1 > D2. It can be understood that, with the width of the conductive path roughly fixed, the resistance of the conductive path is mainly affected by its length and resistivity. Therefore, although the first distance D1 is greater than the second distance D2, because the length of the first conductive path L1 is less than the length of the second conductive path L2, when the resistivity of the first and second conductive paths is the same, the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 is less than the equivalent resistance between the second contact portion 210162 and the lead-out portion 210163.

[0093] In embodiments not illustrated in this application, the equivalent width (material width in the current transmission direction) of the first conductive path is greater than or equal to the equivalent width of the second conductive path. Alternatively, by coordinating the length-to-width ratio of the first and second conductive paths, the equivalent resistance between the first contact 210161 and the lead-out portion 210163 is further made less than the equivalent resistance between the second contact 210162 and the lead-out portion 210163.

[0094] It should be further noted that when the resistivity of the first conductive path and the second conductive path are different, by setting the length L1 of the first conductive path to be less than the length L2 of the second conductive path, it is still possible to achieve an equivalent resistance between the first contact 210161 and the lead-out portion 210163 that is less than the equivalent resistance between the second contact 210162 and the lead-out portion 210163. This application embodiment does not impose specific limitations on this.

[0095] In one possible implementation, the resistivity of the first conductive path is less than the resistivity of the second conductive path. It is understood that the higher the resistivity of a conductive path, the higher its equivalent resistance. Therefore, by setting the resistivity of the first conductive path to be less than the resistivity of the second conductive path, the equivalent resistance between the first contact 210161 and the lead-out 210163 can be made less than the equivalent resistance between the second contact 210162 and the lead-out 210163.

[0096] Understandable, Figure 7 - Figure 11 In the conductive region shown, the conductive path between the first contact portion 210161 and the lead-out portion 210163 is equivalent to a straight path between the first contact portion 210161 and the lead-out portion 210163; the conductive path between the second contact portion 210162 and the lead-out portion 210163 is equivalent to a straight path between the second contact portion 210162 and the lead-out portion 210163. In this embodiment, since the first and second conductive paths can be bent, a larger difference in conductive path length (the difference between the length L1 of the first conductive path and the length L2 of the second conductive path) can be obtained within a limited area, thereby minimizing the voltage division ratio of the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163. Of course, those skilled in the art can also set the first and second conductive paths as straight lines according to actual needs, and this embodiment does not impose specific limitations on this.

[0097] In the embodiments of this application, such as Figure 7As shown in Figure 9-13, the first conductive path and the second conductive path are not arranged on a straight line. That is to say, the first conductive path and the second conductive path are not arranged along the connecting line between the first contact portion 210161 and the second contact portion 210162. This allows the connecting portion 21016 to have more arrangement space between the first contact portion 210161 and the second contact portion 210162, and the position of the lead-out portion 210163 can also be set more flexibly.

[0098] See Figure 13 This is a schematic diagram of a chip structure provided in an embodiment of this application. This embodiment is related to... Figure 12 The difference in the illustrated embodiment is that the connection portion 21016 further includes an insulating region 210164 surrounding the first conductive path and the second conductive path. This insulating region 210164 can be an insulating coating. The insulating region 210164 prevents interference between the first and second conductive paths, thereby obtaining a more stable superimposed signal and improving the stability and reliability of the chip 21.

[0099] See Figure 14 This is a schematic diagram of a chip structure provided in an embodiment of this application. The embodiments of this application are related to... Figure 7 The difference in the illustrated embodiment is that, in this embodiment, the second port is a clock port, and correspondingly, the second signal is a clock signal. That is, the chip 21 can be connected to the power port of the host device 20 through the first contact 210161 of the connection part 21016, and connected to the clock port of the host device 20 through the second contact 210162 of the connection part 21016. By superimposing the power signal and the clock signal, the current input to the power port of the chip 21 is increased.

[0100] As mentioned above, in addition to the power port and clock port, the communication ports of the host device 20 also include a data port, a chip select port, and a ground port. Figure 14 As shown, corresponding to the data port, chip select port, and ground port of the host device, a data contact 21011, a chip select contact 21012, and a ground contact 21015 are also provided on the first plane 2101 of the chip 21. The data contact 21011, the chip select contact 21012, and the ground contact 21015 are respectively used for electrical connection with the data port, the chip select port, and the ground port of the host device 10.

[0101] In some possible implementations, the second port can also be a data port, and correspondingly, the second signal is a data signal. That is, by superimposing the power signal and the data signal, the current input to the power port of chip 21 is increased. For details regarding the embodiments of this application, please refer to the description above; for the sake of brevity, further elaboration will not be repeated here.

[0102] In some applications, the chip select signal is active high. That is, when chip 21 is operating, the chip select signal is always high, while the clock and data signals typically consist of high-to-low level signals. Therefore, superimposing the chip select signal and the power signal, compared to the clock and data signals, can produce a more stable superimposed signal when chip 21 is operating, thereby improving the stability and reliability of chip 21.

[0103] In practical applications, chip 21 may have a multi-layer structure, that is, chip 21 includes multiple layers. It is understood that when chip 21 includes multiple layers, the connection part 21016 and the functional module 21021 may be located on the same layer of chip 21 or on different layers of chip 21.

[0104] In one possible implementation, the connection portion 21016 and the functional module 21021 are disposed on the same layer of the chip 21. In this case, the connection portion 21016 can be directly electrically connected to the functional module 21021 via a wire. Specifically, the lead-out portion 210163 of the connection portion 21016 is directly electrically connected to the functional module 21021 via a wire.

[0105] For example, in Figure 7 and Figure 14 In this chip 21, the connecting part 21016 is disposed on the first plane 2101 of the chip 21 (or it can be disposed on the back side), and the functional module 21021 is also disposed on the first plane 2101 of the chip 21, that is, the connecting part 21016 and the functional module 21021 are disposed on the same layer of the chip 21. The connecting part 21016 can be directly electrically connected to the functional module 21021 through a wire (not shown in the figure).

[0106] In one possible implementation, the connection portion 21016 and the functional module 21021 are disposed on different layers of the chip 21. In this case, the connection portion 21016 can be electrically connected to the functional module 21021 via a via. Specifically, the lead-out portion 210163 of the connection portion 21016 is electrically connected to the functional module 21021 via a via. When the lead-out portion 210163 is electrically connected to the functional module 21021 via a via, the lead-out portion 210163 can be disposed on the back side of the connection portion 21016, i.e., on the side facing the substrate 210.

[0107] It is understood that each signal output by the host device 10 has a specific function. Superimposing the first and second signals generally does not affect the functions that the first and second signals should perform. In other words, by superimposing the signals, the functional module 21021 in the chip 21 can be controlled to perform functions matching the first and second signals.

[0108] See Figure 15This is a schematic diagram of the circuit structure of a chip provided in an embodiment of this application. Figure 15 As shown, chip 21 includes a first resistor R1, a second resistor R2, a parsing circuit, and a functional module 21021. The first resistor R1 is the equivalent resistance between the first contact portion 210161 and the lead-out portion 210163 in the connection portion 21016; the second resistor R2 is the equivalent resistance between the second contact portion 210162 and the lead-out portion 210163 in the connection portion 21016. The first contact portion 210161 is used to connect to the first port (power port) of the host device 10 and receive the first signal (power signal) sent by the host device 10; the second contact portion 210162 is used to connect to the second port (non-power port) of the host device 10 and receive the second signal (non-power signal) sent by the host device 10; the lead-out portion 210163 is used to output a superimposed signal composed of the first signal and the second signal.

[0109] The input terminal of the parsing circuit is electrically connected to the lead-out section 210163. The parsing circuit is used to parse the superimposed signal and outputs a first parsed signal at its first output terminal and a second parsed signal at its second output terminal. It can be understood that the first parsed signal is the parsed power supply signal, and the second parsed signal is the parsed non-power supply signal. Specifically, when the second port is a chip select port, the second parsed signal is the parsed chip select signal; when the second port is a clock port, the second parsed signal is the parsed clock signal; and when the second port is a data port, the second parsed signal is the parsed data signal.

[0110] The first port (power port) of functional module 21021 is electrically connected to the first output terminal of the parsing circuit. The first port of functional module 21021 receives the first parsing signal output from the first output terminal of the parsing circuit and performs a matching function with the first signal through the first parsing signal. Specifically, in order to perform a matching function with the first signal through the first parsing signal, it is necessary to ensure that the first parsing signal and the first signal have the same level (i.e., when the first signal is high, the first parsing signal should also be high; when the first signal is low, the first parsing signal should also be low). Furthermore, since functional module 21021 typically has a minimum operating voltage, when the first signal is high, the voltage of the first parsing signal should be greater than or equal to the minimum operating voltage of functional module 21021.

[0111] The second port (non-power port) of functional module 21021 is electrically connected to the second output terminal of the parsing circuit. The second port of functional module 21021 is used to receive the second parsing signal output from the second output terminal of the parsing circuit, and to achieve a matching function with the second signal through the second parsing signal. Specifically, in order to achieve the matching function with the second signal through the second parsing signal, it is necessary to ensure that the second parsing signal and the second signal have the same level state (i.e., when the second signal is high, the second parsing signal should also be high; when the second signal is low, the second parsing signal should also be low).

[0112] See Figure 16 This is a schematic diagram of the circuit structure of a chip provided in an embodiment of this application. The embodiments of this application are similar to... Figure 15 The difference in the illustrated embodiment is that the input terminal of the parsing circuit is electrically connected to the first output terminal of the parsing circuit. It can be understood that, according to this connection, the first parsed signal output from the first output terminal of the parsing circuit is the superimposed signal. In other words, the function of matching the first signal is achieved through the superimposed signal.

[0113] Understandably, in order to achieve a function matching the first signal through signal superposition, the voltage of the superimposed signal should be greater than or equal to the minimum operating voltage of the functional module 21021 when it is in the working state. Furthermore, since the first signal is a power signal, it is typically high when the functional module 21021 is in the working state. However, the second signal may be high or low. Therefore, there are two possibilities when the functional module 21021 is in the working state: one is that both the first and second signals are high; the other is that both signals are high and low.

[0114] Further analysis reveals that when both the first and second signals are at a high level, there is typically no voltage drop or only a small voltage drop along the power signal transmission path. In this case, the voltage of the superimposed signal consisting of the first and second signals is usually relatively high.

[0115] Furthermore, the parsing circuit also includes a comparison circuit. The input terminal of the comparison circuit (i.e., the input terminal of the parsing circuit) is electrically connected to the lead-out portion 210163 for receiving the superimposed signal; the output terminal of the comparison circuit (i.e., the second output terminal of the parsing circuit) is electrically connected to the second port of the functional module 21021 for outputting the second parsing signal.

[0116] In this embodiment, the comparison circuit is configured such that when the first signal is high and the second signal is low, the second analytical signal is low; and when the first signal is high and the second signal is high, the second analytical signal is high. That is, when the first signal is high (at which time, functional module 21021 can operate normally), the second analytical signal and the second signal have the same level, thus enabling the function of matching the second signal to be achieved through the second analytical signal.

[0117] It should be added that, Figure 16 This is merely one possible implementation provided for an embodiment of this application and should not be construed as limiting the scope of protection of this application. For example, those skilled in the art can further process the superimposed signal according to actual needs (e.g., amplification, filtering, etc.), and then obtain a first analytical signal and a second analytical signal that meet the above requirements through the processed superimposed signal.

[0118] For details regarding the embodiments of this application, please refer to the descriptions of other embodiments above. For the sake of brevity, these details will not be repeated here.

[0119] According to the embodiments of this application, Figure 16 The comparison circuit of the illustrated embodiment may further include a comparator B1 (not shown). Specifically, the comparator B1 has a first input terminal and a second input terminal. The first input terminal of the comparator B1 (i.e., the input terminal of the comparison circuit) is electrically connected to the lead-out portion 210163, the second input terminal of the comparator B1 is used to receive the second target voltage RE, and the output terminal of the comparator B1 (i.e., the output terminal of the comparison circuit) is electrically connected to the second port of the functional module 21021.

[0120] In this embodiment, the first contact portion 210161 and the second contact portion 210162 receive a first signal and a second signal, respectively, and the lead-out portion 210163 transmits the superimposed signal composed of the first signal and the second signal to the first input terminal of the comparator B1. The comparator B1 compares the voltage of the superimposed signal with a set second target voltage RE. The magnitude of the second target voltage RE satisfies the condition: "when the first signal is high and the second signal is low, the voltage of the superimposed signal" < the second target voltage RE < "when the first signal is high and the second signal is high".

[0121] Furthermore, when the voltage of the superimposed signal is less than the second target voltage RE, the output of comparator B1 is low; that is, when the first signal is high and the second signal is low, the second analytical signal is low. When the voltage of the superimposed signal is greater than the second target voltage RE, the output of comparator B1 is high; that is, when the first signal is high and the second signal is high, the second analytical signal is high. In other words, by setting the second target voltage RE as described above, it can be ensured that the second analytical signal and the second signal have the same level state, and thus the function of matching the second signal can be achieved through the second analytical signal. In addition, when the first signal is low, the functional module 21021 usually does not work, therefore, no judgment is required.

[0122] If the structure of the connecting part 21016 is as follows Figure 7 As shown, the first distance D1 between the lead-out portion 210163 and the first contact portion 210161 is 1 mm, the second distance D2 between the lead-out portion 210163 and the second contact portion 210162 is 3 mm, and the resistivity α is 1 kΩ / mm. Therefore, the resistance values ​​of the first resistor R1 and the second resistor R2 are 1 kΩ and 3 kΩ, respectively, and the total resistance R' is 1 kΩ + 3 kΩ = 4 kΩ.

[0123] The first contact 210161 and the second contact 210162 receive the power signal and the chip select signal, respectively. The lead-out section 210163 transmits the superimposed signal composed of the power signal and the chip select signal to the first input terminal of the comparator B1. When the voltage of the power signal is 3.3V and the voltage of the chip select signal is 0V, since the proportion of the second resistor R2 to the total resistance is 3kΩ / 4kΩ = 0.75, the voltage of the superimposed signal is 3.3V * 0.75, which is approximately 2.5V. When the voltage of the power signal is 3.3V and the voltage of the chip select signal is 3.3V, the voltage of the superimposed signal is 3.3V. Therefore, the second target voltage RE can be selected from a value between 2.5V and 3.3V.

[0124] For example, the second target voltage RE is 2.6V. When the power supply signal voltage is 3.3V and the chip select signal voltage is 0V, the voltage of the superimposed signal is 3.3V * 0.75, which is approximately 2.5V. Therefore, the voltage of the superimposed signal is less than the second target voltage RE, and the output of comparator B1 outputs a low level, meaning the second resolution signal is low. When the power supply signal voltage is 3.3V and the chip select signal voltage is 3.3V, the voltage of the superimposed signal is 3.3V. Therefore, the voltage of the superimposed signal is greater than the second target voltage RE, and the output of comparator B1 outputs a high level, meaning the second resolution signal is high.

[0125] For details regarding the embodiments of this application, please refer to the descriptions of other embodiments above. For the sake of brevity, these details will not be repeated here.

[0126] In some possible implementations, the parsing circuit can be integrated inside the functional module 21021 or set outside the functional module 21021 as a peripheral circuit. This application embodiment does not impose specific limitations on this.

[0127] Corresponding to the above embodiments, this application also provides a replaceable accessory, which includes the chip 21 described in any of the above embodiments.

[0128] For details regarding the embodiments of this application, please refer to the description of the embodiments above. For the sake of brevity, these details will not be repeated here.

[0129] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A chip for communicating with a host device, characterized in that, The chip includes communication contacts and a connection portion that are electrically connected to ports of the host device, the ports of the host device including a first port and a second port, and the connection portion including: A resistive component, wherein the resistivity of the resistive component is greater than the resistivity of the communication contact; The first contact portion is used to be electrically connected to the first port and to receive the power signal output from the first port; The second contact portion is used to be electrically connected to the second port and to receive non-power signals output by the second port; The lead-out portion is electrically connected to the first contact portion and the second contact portion respectively. The lead-out portion is used to output a superimposed signal of the power signal and the non-power signal, and to control the functional module in the chip to realize the function matching the power signal and the non-power signal through the superimposed signal. The connecting portion forms a first conductive path between the first contact portion and the lead-out portion, and the connecting portion forms a second conductive path between the second contact portion and the lead-out portion. At least a portion of the resistive component is respectively provided on the first conductive path and the second conductive path; wherein, the length of the first conductive path is less than the length of the second conductive path.

2. The chip according to claim 1, characterized in that, The communication contact has a contact portion that is connected to a port of the host device. Viewed from above the chip substrate or the pin holder of the host device, with two orthogonal straight lines designated as the first and second imaginary lines, the contact portions of all the communication contacts are projected onto the second imaginary line. The first imaginary line passes through the midpoint between the two farthest projection positions of all the contact portions. When one region is designated as the first region and the other region as the second region relative to the first imaginary line, both the first and second contact portions are located within the first region. The contact portion also includes a grounding contact portion, which is located within the second region.

3. The chip according to claim 2, characterized in that, The first conductive path has a first equivalent width, and the second conductive path has a second equivalent width; The ratio of the length of the first conductive path to the first equivalent width is less than the ratio of the length of the second conductive path to the second equivalent width.

4. The chip according to claim 3, characterized in that, The first conductive path and the second conductive path are not on the same straight line.

5. The chip according to claim 3, characterized in that, The connecting part includes: A conductive region, wherein the resistive component is located within the conductive region, and the first contact portion and the second contact portion are located within the conductive region, and the lead-out portion is located on one side of the conductive region; wherein the equivalent resistance of the first conductive path is less than the equivalent resistance of the second conductive path.

6. The chip according to claim 3, characterized in that, The connecting part includes: A conductive region, wherein the resistive component is located within the conductive region, and the first contact portion, the second contact portion, and the lead-out portion are located within the conductive region; The conductive region includes: A first conductive electronic region having a first resistivity, wherein the first contact portion and the second contact portion are located within the first conductive electronic region; A second conductive region having a second resistivity greater than the first resistivity, wherein the lead-out portion is located within the second conductive region; The resistivity of the first conductive region is less than that of the second conductive region.

7. The chip according to claim 3, characterized in that, The connecting part includes: The first equivalent width is greater than or equal to the second equivalent width.

8. The chip according to any one of claims 1-7, characterized in that, The non-power signal is a chip select signal, a clock signal, or a data signal.

9. A replaceable accessory, characterized in that, Includes the chip described in any one of claims 1-8.

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