Power module

Abstract

The utility model proposes a power module, the power module comprises a lining plate and a power circuit arranged on the lining plate, the power circuit comprises a Vienna rectification circuit and a three-phase full-bridge circuit, and the output end of the Vienna rectification circuit is connected with the input end of the three-phase full-bridge circuit; wherein the power chips in the Vienna rectifier circuit and the three-phase full-bridge circuit are silicon carbide power chips. The power factor of the power module can be improved by adopting the Vienna rectifying circuit, and meanwhile, the silicon carbide-based chip is adopted to replace an existing silicon-based chip, so that the size of the chip can be reduced, and the size of the power module is prevented from being increased under the condition that higher output power is set.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of semiconductor, especially a kind of power module. BACKGROUND

[0002] The output power of existing PIM2 package is low, and the highest specification is only 1200V, 35A. If a chip with higher output power is directly used, the volume of the obtained power module will increase, which is unacceptable. Therefore, how to improve the output power without increasing the volume of the existing power module is a problem that needs to be solved urgently. SUMMARY

[0003] The utility model discloses a kind of power modules, to solve the problem of improving the output power without increasing the volume of the existing power module in prior art.

[0004] To achieve the above object, the utility model provides a kind of power module, the power module includes backing plate and the power circuit of setting on the backing plate, the power circuit includes Vienna rectifier circuit and three-phase full bridge circuit, the output end of the Vienna rectifier circuit is connected with the input end of the three-phase full bridge circuit;Wherein:

[0005] The power chip in the Vienna rectifier circuit and the three-phase full bridge circuit uses silicon carbide power chip.

[0006] Optionally, the power module further includes a lead frame and a plurality of pins; the Vienna rectifier circuit includes a first silicon carbide diode chip, a second silicon carbide diode chip, a third silicon carbide diode chip, a fourth silicon carbide diode chip, a fifth silicon carbide diode chip, a sixth silicon carbide diode chip to form a three-phase rectifier bridge, and a first silicon carbide MOS tube chip, a second silicon carbide MOS tube chip, a third silicon carbide MOS tube chip, a fourth silicon carbide MOS tube chip, a fifth silicon carbide MOS tube chip, and a sixth silicon carbide MOS tube chip to form a three-phase bidirectional switch; the three-phase full bridge circuit is composed of a seventh silicon carbide MOS tube chip, an eighth silicon carbide MOS tube chip, a ninth silicon carbide MOS tube chip, a tenth silicon carbide MOS tube chip, an eleventh silicon carbide MOS tube chip, and a twelfth silicon carbide MOS tube chip; wherein:

[0007] The electrodes of the silicon carbide diode chip and the silicon carbide MOS tube chip are led out to the pins through the lead frame.

[0008] Optionally, the anode electrodes of the first silicon carbide diode chip, the second silicon carbide diode chip, and the third silicon carbide diode chip are led out to the first pin through the lead frame.

[0009] the cathode electrode of the first silicon carbide diode die, the anode electrode of the fourth silicon carbide diode die, and the drain electrode of the first silicon carbide MOS transistor die are led out to a second pin through the lead frame;

[0010] the cathode electrode of the second silicon carbide diode die, the anode electrode of the fifth silicon carbide diode die, and the drain electrode of the second silicon carbide MOS transistor die are led out to a third pin through the lead frame;

[0011] the cathode electrode of the third silicon carbide diode die, the anode electrode of the sixth silicon carbide diode die, and the drain electrode of the third silicon carbide MOS transistor die are led out to a fourth pin through the lead frame;

[0012] the cathode electrodes of the fourth silicon carbide diode die, the fifth silicon carbide diode die, the sixth silicon carbide diode die are led out to a twenty-ninth pin through the lead frame;

[0013] the drain electrode of the seventh silicon carbide MOS transistor die, the drain electrode of the eighth silicon carbide MOS transistor die, the drain electrode of the ninth silicon carbide MOS transistor die are led out to a fifth pin through the lead frame;

[0014] the source electrode of the seventh silicon carbide MOS transistor die, the drain electrode of the tenth silicon carbide MOS transistor die are led out to a sixth pin through the lead frame;

[0015] the gate electrode of the seventh silicon carbide MOS transistor die is led out to a seventh pin through the lead frame;

[0016] the source electrode of the eighth silicon carbide MOS transistor die, the drain electrode of the eleventh silicon carbide MOS transistor die are led out to an eighth pin through the lead frame;

[0017] the gate electrode of the eighth silicon carbide MOS transistor die is led out to a ninth pin through the lead frame;

[0018] the source electrode of the ninth silicon carbide MOS transistor die, the drain electrode of the twelfth silicon carbide MOS transistor die are led out to a tenth pin through the lead frame;

[0019] the gate electrode of the ninth silicon carbide MOS transistor die is led out to an eleventh pin through the lead frame;

[0020] the source electrode of the twelfth silicon carbide MOS transistor die is led out to a fourteenth pin through the lead frame;

[0021] the gate electrode of the twelfth silicon carbide MOS transistor die is led out to a fifteenth pin through the lead frame;

[0022] the source electrode of the eleventh silicon carbide MOS transistor die is led out to the sixteenth pin through the lead frame;

[0023] the gate electrode of the eleventh silicon carbide MOS transistor die is led out to the seventeenth pin through the lead frame;

[0024] the source electrode of the tenth silicon carbide MOS transistor die is led out to the eighteenth pin through the lead frame;

[0025] the gate electrode of the tenth silicon carbide MOS transistor die is led out to the nineteenth pin through the lead frame;

[0026] the gate electrode of the third silicon carbide MOS transistor die is led out to the twentieth pin through the lead frame;

[0027] the source electrode of the third silicon carbide MOS transistor die, the source electrode of the sixth silicon carbide MOS transistor die are led out to the twenty-first pin through the lead frame;

[0028] the gate electrode of the sixth silicon carbide MOS transistor die is led out to the twenty-second pin through the lead frame;

[0029] the gate electrode of the fifth silicon carbide MOS transistor die is led out to the twenty-third pin through the lead frame;

[0030] the source electrode of the second silicon carbide MOS transistor die, the source electrode of the fifth silicon carbide MOS transistor die are led out to the twenty-fourth pin through the lead frame;

[0031] the gate electrode of the second silicon carbide MOS transistor die is led out to the twenty-fifth pin through the lead frame;

[0032] the gate electrode of the first silicon carbide MOS transistor die is led out to the twenty-sixth pin through the lead frame;

[0033] the source electrode of the first silicon carbide MOS transistor die, the source electrode of the fourth silicon carbide MOS transistor die are led out to the twenty-seventh pin through the lead frame;

[0034] the gate electrode of the fourth silicon carbide MOS transistor die is led out to the twenty-eighth pin through the lead frame;

[0035] the drain electrode of the fourth silicon carbide MOS transistor die, the fifth silicon carbide MOS transistor die, the sixth silicon carbide MOS transistor die are led out to the thirtieth pin through the lead frame.

[0036] Optionally, the lead frame comprises a plurality of setting lead frames and a plurality of connecting lead frames; wherein:

[0037] The setting lead frame is provided with a plurality of silicon carbide power chips, and the silicon carbide MOS tube chip drain is welded on the setting lead frame; the setting lead frame leads out the electrodes of the set silicon carbide power chips to the same pin, the same setting lead frame or the same silicon carbide power chip.

[0038] The connecting lead frame is connected with the drain or source of the silicon carbide MOS tube chip through a bonding wire, and leads out the drain or source of the silicon carbide MOS tube chip to the corresponding pin.

[0039] Optionally, the setting lead frame includes a first setting lead frame, a second setting lead frame, a third setting lead frame and a fourth setting lead frame; the first setting lead frame is provided with the first silicon carbide diode chip and the first silicon carbide MOS tube chip, the second setting lead frame is provided with the second silicon carbide diode chip and the second silicon carbide MOS tube chip, the third setting lead frame is provided with the fourth silicon carbide diode chip, and the fourth setting lead frame is provided with the second silicon carbide diode chip and the fifth silicon carbide diode chip; wherein:

[0040] The first setting lead frame and the second setting lead frame are half work types, so that the straight edge of the first setting lead frame is oppositely arranged with the straight edge of the second setting lead frame.

[0041] The third setting lead frame is arranged at the concave edge of the first setting lead frame, and the fourth setting lead frame is arranged at the concave edge of the second setting lead frame.

[0042] The third setting lead frame and the fourth setting lead frame are connected through a bonding wire across the concave edges of the first setting lead frame and the second setting lead frame.

[0043] Optionally, the setting lead frame further includes a fifth setting lead frame, a sixth setting lead frame, a seventh setting lead frame, an eighth setting lead frame, a ninth setting lead frame, a tenth setting lead frame and an eleventh setting lead frame.

[0044] The fifth setting lead frame is provided with the fourth silicon carbide MOS tube chip, the fifth silicon carbide MOS tube chip and the sixth silicon carbide MOS tube chip, the sixth setting lead frame is provided with the third silicon carbide diode chip, the seventh setting lead frame is provided with the third silicon carbide MOS tube chip, and the sixth setting lead frame and the seventh setting lead frame are connected through a bonding wire.

[0045] The eighth setting lead frame is provided with the tenth silicon carbide MOS tube core chip, the ninth setting lead frame is provided with the eleventh silicon carbide MOS tube core chip, and the tenth setting lead frame is provided with the twelfth silicon carbide MOS tube core chip;

[0046] The eleventh setting lead frame is provided with the seventh silicon carbide MOS tube core chip, the eighth silicon carbide MOS tube core chip and the ninth silicon carbide MOS tube core chip;

[0047] Wherein:

[0048] The first setting lead frame is connected with the anode electrode of the fourth silicon carbide diode core chip through a bonding wire, the second setting lead frame is connected with the anode electrode of the fifth silicon carbide diode core chip through a bonding wire, and the sixth setting lead frame is connected with the anode electrode of the sixth silicon carbide diode core chip through a bonding wire;

[0049] The eighth setting lead frame is connected with the source electrode of the seventh silicon carbide MOS tube core chip through a bonding wire, the ninth setting lead frame is connected with the source electrode of the eighth silicon carbide MOS tube core chip through a bonding wire, and the tenth setting lead frame is connected with the source electrode of the ninth silicon carbide MOS tube core chip through a bonding wire.

[0050] Optionally, the connecting lead frame comprises six first connecting lead frames, three second connecting lead frames, one third connecting lead frame, six fourth connecting lead frames and six fifth connecting lead frames; wherein:

[0051] The first connecting lead frame is connected with the gate electrode of the silicon carbide MOS tube core chip in the Vienna rectifier circuit through a bonding wire and led out to the corresponding pin, and the first connecting lead frame is arranged between the setting lead frame where the corresponding silicon carbide MOS tube core chip is arranged and the corresponding pin;

[0052] The second connecting lead frame is connected with the source electrode of two silicon carbide MOS tube core chips of the same phase in the Vienna rectifier circuit through a bonding wire respectively and led out to the corresponding pin, and the second connecting lead frame is arranged between the setting lead frames where the two silicon carbide MOS tube core chips are arranged;

[0053] The third connecting lead frame is connected with the anode electrode of the first silicon carbide diode core chip, the second silicon carbide diode core chip and the third silicon carbide diode core chip through a bonding wire respectively and led out to the corresponding pin, and the third connecting lead frame is arranged between the setting lead frame where the corresponding silicon carbide diode core chip is arranged and the corresponding pin;

[0054] The fourth connecting lead frame is connected with the gate electrodes of the silicon carbide MOS tube chips in the three-phase full-bridge circuit through bonding wires respectively and led out to corresponding pins, and the fourth connecting lead frame is arranged between the setting lead frame where the corresponding silicon carbide MOS tube chip is arranged and the corresponding pin.

[0055] The fifth connecting lead frame is connected with the source electrodes of the silicon carbide MOS tube chips in the three-phase full-bridge circuit through bonding wires respectively and led out to corresponding pins, and the fifth connecting lead frame is arranged between the setting lead frame where the corresponding silicon carbide MOS tube chip is arranged and the corresponding pin.

[0056] Optionally, the backing plate comprises a first backing plate and a second backing plate; wherein:

[0057] The first to sixth setting lead frames and the third connecting lead frame are arranged on the first backing plate;

[0058] The seventh to eleventh setting lead frames and the fourth to fifth connecting lead frames are arranged on the second backing plate;

[0059] The first connecting lead frame corresponding to the first silicon carbide MOS tube chip, the second silicon carbide MOS tube chip, the fourth silicon carbide MOS tube chip, the fifth silicon carbide MOS tube chip and the sixth silicon carbide MOS tube chip is arranged on the first backing plate;

[0060] The first connecting lead frame corresponding to the third silicon carbide MOS tube chip is arranged on the second backing plate;

[0061] The second connecting lead frame corresponding to the first silicon carbide MOS tube chip, the second silicon carbide MOS tube chip, the fourth silicon carbide MOS tube chip and the fifth silicon carbide MOS tube chip is arranged on the first backing plate;

[0062] The second connecting lead frame corresponding to the third silicon carbide MOS tube chip and the sixth silicon carbide MOS tube chip is arranged on the second backing plate.

[0063] Optionally, the backing plate is a ceramic backing plate.

[0064] Optionally, the power module further comprises a packaging side frame, a substrate and a packaging cover plate; wherein:

[0065] The side edge of the packaging side frame is provided with pins, the substrate is arranged in the packaging side frame, the backing plate is arranged on the substrate, and the packaging cover plate is arranged on the power circuit.

[0066] The utility model provides a kind of power module, the power module includes lining plate and is arranged on the lining plate power circuit, the power circuit includes Vienna rectifier circuit and three-phase full bridge circuit, the output of Vienna rectifier circuit is connected with the input of three-phase full bridge circuit;Wherein: the power chip in Vienna rectifier circuit with three-phase full bridge circuit adopts silicon carbide power chip.By adopting Vienna rectifier circuit can improve the power factor of power module, simultaneously adopt silicon carbide base chip to replace existing silicon base chip, so that chip volume can be reduced, to avoid the volume increase of power module in the case of setting higher output power. BRIEF DESCRIPTION OF DRAWINGS

[0067] The accompanying drawings incorporated in and forming a part of the specification, illustrate embodiments consistent with the present utility model, and together with the description serve to explain the principles of the utility model.

[0068] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or prior art, below will be to the drawing needed to be used in the embodiment or prior art description simple introduction, obviously, for those skilled in the art, without incurring creative labor, can also obtain other drawings according to these drawings.

[0069] One or more embodiments are exemplified by the pictures in the drawings corresponding thereto, which do not constitute a limitation on the embodiments, and elements with the same reference numerals in the drawings represent similar elements, unless otherwise specified, and the figures in the drawings do not constitute a proportional limitation.

[0070] Figure 1 It is the structural schematic diagram of the utility model power module one embodiment;

[0071] Figure 2 It is the circuit structure diagram of the utility model power module power circuit;

[0072] Figure 3 It is the pin schematic diagram of the utility model power module power circuit;

[0073] Figure 4 It is the lead frame schematic diagram of the utility model power module one embodiment;

[0074] Figure 5 It is the bonding wire lead-out schematic diagram of the utility model power module;

[0075] Figure 6 It is the structural schematic diagram of the utility model power module another embodiment;

[0076] Figure 7It is the lead frame schematic view of another embodiment of the power module of the utility model;

[0077] Figure 8 It is the appearance schematic view of the power module of the utility model;

[0078] Explanation of reference numerals:

[0079]

[0080]

[0081] Specific embodiments

[0082] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor shall fall within the scope of protection of the present application.

[0083] The following disclosure provides many different embodiments or examples for implementing different structures of the utility model. In order to simplify the disclosure of the utility model, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the utility model. In addition, the utility model can refer to numbers and / or letters repeatedly in different examples. Such repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed.

[0084] It should be understood that the specific embodiments described herein are only used to explain the utility model, and are not used to limit the utility model. In order to enable those skilled in the art to better understand the present application, the technical scheme in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor shall fall within the scope of protection of the present application.

[0085] The utility model provides a kind of power module, refer to Figure 1 , Figure 1The utility model provides a power module structure schematic diagram of one embodiment, the power module includes the lining plate 100 and sets up on the lining plate 100 power circuit 200, power circuit 200 includes Vienna rectifier circuit 210 and three -phase full bridge circuit 220, the output of Vienna rectifier circuit 210 is connected with the input of three -phase full bridge circuit 220, wherein:

[0086] The power chip 230 in Vienna rectifier circuit 210 and three -phase full bridge circuit 220 adopts silicon carbide power chip 230.

[0087] Vienna rectifier circuit 210 is used to rectify three -phase alternating current input to power module, to output direct current to three -phase full bridge circuit 220, and three -phase full bridge circuit 220 is used to drive three -phase motor PMSM to run.

[0088] It can be understood that, compared with the existing power conversion circuit, the power module with Vienna rectification has higher power factor and lower total harmonic distortion, so that the power performance can be significantly improved.

[0089] It can be understood that the power chip 230 in Vienna rectifier circuit 210 and three -phase full bridge circuit 220 includes but is not limited to diode, MOS tube, IGBT.

[0090] Compared with silicon SI base chip, silicon carbide SIC base chip has the advantages of smaller volume, high band gap, high thermal conductivity, low on-resistance, low switching loss, high switching speed, low reverse recovery loss, high voltage resistance, high temperature resistance, excellent heat dissipation capacity and reliability.

[0091] Under the same output power, silicon carbide base chip has smaller volume, so under the same volume, silicon carbide base chip can output higher power, so in the embodiment, the effect of increasing output power without increasing module volume is realized.

[0092] The embodiment adopts Vienna rectifier circuit 210 to improve the power factor of the power module, and replaces the existing silicon base chip with silicon carbide base chip to reduce the chip volume, so that the volume of the power module is not increased under the condition of setting higher output power.

[0093] Further, the power module further comprises a lead frame and a plurality of pins P; the Vienna rectifier circuit 210 comprises a three-phase full-bridge rectifier composed of a first silicon carbide diode chip D1, a second silicon carbide diode chip D2, a third silicon carbide diode chip D3, a fourth silicon carbide diode chip D4, a fifth silicon carbide diode chip D5, and a sixth silicon carbide diode chip D6, and a three-phase bidirectional switch composed of a first silicon carbide MOS chip S1, a second silicon carbide MOS chip S2, a third silicon carbide MOS chip S3, a fourth silicon carbide MOS chip S4, a fifth silicon carbide MOS chip S5, and a sixth silicon carbide MOS chip S6; the three-phase full-bridge circuit 220 is composed of a seventh silicon carbide MOS chip S7, an eighth silicon carbide MOS chip S8, a ninth silicon carbide MOS chip S9, a tenth silicon carbide MOS chip S10, an eleventh silicon carbide MOS chip S11, and a twelfth silicon carbide MOS chip S12.

[0094] The electrodes of the silicon carbide diode chips and the silicon carbide MOS chips are led out to the pins P through the lead frame.

[0095] The pins P are connections of the power module and external circuits, the power module is integrated with a plurality of chips, and the chips realize electrical signal transmission with external circuits through the pins P.

[0096] The lead frame serves as a chip carrier of the integrated circuit, and electrical connections between chips and between a chip and an external lead are realized by means of a bonding material. The specific type of the bonding material can be set based on actual needs, such as gold wire, aluminum wire, or copper wire.

[0097] The Vienna rectifier circuit 210 comprises a rectifying unit corresponding to three phases, a first bus capacitor C1, and a second bus capacitor C2; each phase rectifying unit comprises an inductor L, two silicon carbide diodes, and two silicon carbide MOS transistors; wherein the bus capacitors and the inductor L are arranged outside the power module, and the silicon carbide diodes and the silicon carbide MOS transistors are electrically connected to corresponding bus capacitors and inductors through the pins P.

[0098] For ease of illustration, refer to Figure 2 The first silicon carbide diode D1, the fourth silicon carbide diode D4, the first silicon carbide MOS transistor, and the fourth silicon carbide MOS transistor are taken as a U-phase rectifying unit; the second silicon carbide diode D2, the fifth silicon carbide diode D5, the second silicon carbide MOS transistor, and the fifth silicon carbide MOS transistor are taken as a V-phase rectifying unit; and the third silicon carbide diode D3, the sixth silicon carbide diode D6, the third silicon carbide MOS transistor, and the sixth silicon carbide MOS transistor are taken as a W-phase rectifying unit.

[0099] Similarly, the three-phase full-bridge circuit 220 also corresponds to three-phase bridge arms, for the convenience of description, the seventh silicon carbide MOS tube and the tenth silicon carbide MOS tube are taken as the U-phase bridge arm; the eighth silicon carbide MOS tube and the eleventh silicon carbide MOS tube are taken as the V-phase bridge arm; and the ninth silicon carbide MOS tube and the twelfth silicon carbide MOS tube are taken as the W-phase bridge arm.

[0100] Further, the anode electrodes of the first silicon carbide diode chip D1, the second silicon carbide diode chip D2 and the third silicon carbide diode chip D3 are led out to the first pin P through the lead frame;

[0101] The cathode electrode of the first silicon carbide diode chip D1, the anode electrode of the fourth silicon carbide diode chip D4 and the drain electrode of the first silicon carbide MOS tube chip S1 are led out to the second pin P through the lead frame;

[0102] The cathode electrode of the second silicon carbide diode chip D2, the anode electrode of the fifth silicon carbide diode chip D5 and the drain electrode of the second silicon carbide MOS tube chip S2 are led out to the third pin P through the lead frame;

[0103] The cathode electrode of the third silicon carbide diode chip D3, the anode electrode of the sixth silicon carbide diode chip D6 and the drain electrode of the third silicon carbide MOS tube chip S3 are led out to the fourth pin P through the lead frame;

[0104] The cathode electrodes of the fourth silicon carbide diode chip D4, the fifth silicon carbide diode chip D5 and the sixth silicon carbide diode chip D6 are led out to the twenty-ninth pin P through the lead frame;

[0105] The drain electrode of the seventh silicon carbide MOS tube chip S7, the drain electrode of the eighth silicon carbide MOS tube chip S8 and the drain electrode of the ninth silicon carbide MOS tube chip S9 are led out to the fifth pin P through the lead frame;

[0106] The source electrode of the seventh silicon carbide MOS tube chip S7 and the drain electrode of the tenth silicon carbide MOS tube chip S10 are led out to the sixth pin P through the lead frame;

[0107] The gate electrode of the seventh silicon carbide MOS tube chip S7 is led out to the seventh pin P through the lead frame;

[0108] The source electrode of the eighth silicon carbide MOS tube chip S8 and the drain electrode of the eleventh silicon carbide MOS tube chip S11 are led out to the eighth pin P through the lead frame;

[0109] The gate electrode of the eighth silicon carbide MOS transistor chip S8 is led out to a ninth pin P through the lead frame;

[0110] The source electrode of the ninth silicon carbide MOS transistor chip S9, the drain electrode of the twelfth silicon carbide MOS transistor chip S12 are led out to a tenth pin P through the lead frame;

[0111] The gate electrode of the ninth silicon carbide MOS transistor chip S9 is led out to an eleventh pin P through the lead frame;

[0112] The source electrode of the twelfth silicon carbide MOS transistor chip S12 is led out to a fourteenth pin P through the lead frame;

[0113] The gate electrode of the twelfth silicon carbide MOS transistor chip S12 is led out to a fifteenth pin P through the lead frame;

[0114] The source electrode of the eleventh silicon carbide MOS transistor chip S11 is led out to a sixteenth pin P through the lead frame;

[0115] The gate electrode of the eleventh silicon carbide MOS transistor chip S11 is led out to a seventeenth pin P through the lead frame;

[0116] The source electrode of the tenth silicon carbide MOS transistor chip S10 is led out to an eighteenth pin P through the lead frame;

[0117] The gate electrode of the tenth silicon carbide MOS transistor chip S10 is led out to a nineteenth pin P through the lead frame;

[0118] The gate electrode of the third silicon carbide MOS transistor chip S3 is led out to a twentieth pin P through the lead frame;

[0119] The source electrode of the third silicon carbide MOS transistor chip S3, the source electrode of the sixth silicon carbide MOS transistor chip S6 are led out to a twenty-first pin P through the lead frame;

[0120] The gate electrode of the sixth silicon carbide MOS transistor chip S6 is led out to a twenty-second pin P through the lead frame;

[0121] The gate electrode of the fifth silicon carbide MOS transistor chip S5 is led out to a twenty-third pin P through the lead frame;

[0122] The source electrode of the second silicon carbide MOS transistor chip S2, the source electrode of the fifth silicon carbide MOS transistor chip S5 are led out to a twenty-fourth pin P through the lead frame;

[0123] The gate electrode of the second silicon carbide MOS transistor chip S2 is led out to the twenty-fifth pin P through the lead frame;

[0124] The gate electrode of the first silicon carbide MOS transistor chip S1 is led out to the twenty-sixth pin P through the lead frame;

[0125] The source electrode of the first silicon carbide MOS transistor chip S1, the source electrode of the fourth silicon carbide MOS transistor chip S4 are led out to the twenty-seventh pin P through the lead frame;

[0126] The gate electrode of the fourth silicon carbide MOS transistor chip S4 is led out to the twenty-eighth pin P through the lead frame;

[0127] The drain electrode of the fourth silicon carbide MOS transistor chip S4, the fifth silicon carbide MOS transistor chip S5, the sixth silicon carbide MOS transistor chip S6 are led out to the thirtieth pin P through the lead frame.

[0128] The power module further comprises a thermistor, the two ends of the thermistor are connected to the twelfth pin P and the thirteenth pin P through the bonding material respectively.

[0129] Referring to Figure 3 , the first pin P in the embodiment connects the cathode of the three-phase rectifier bridge, the second pin P connects the U-phase inductor, the third pin P connects the V-phase inductor, the fourth pin P connects the W-phase inductor, the fifth pin P connects the positive input of the three-phase full-bridge circuit 220, and the sixth pin P connects the U-phase output;

[0130] The seventh pin P connects the gate control of the seventh silicon carbide MOS transistor chip S7, the eighth pin P connects the V-phase output, the ninth pin P connects the gate control of the eighth silicon carbide MOS transistor chip S8, the tenth pin P connects the W-phase output, and the eleventh pin P connects the gate control of the ninth silicon carbide MOS transistor chip S9;

[0131] The twelfth pin P connects the first end of the thermistor, and the thirteenth pin P connects the second end of the thermistor;

[0132] The fourteenth pin P connects the source input of the twelfth silicon carbide MOS transistor chip S12, the fifteenth pin P connects the gate control of the twelfth silicon carbide MOS transistor chip S12, the sixteenth pin P connects the source input of the eleventh silicon carbide MOS transistor chip S11, the seventeenth pin P connects the gate control of the eleventh silicon carbide MOS transistor chip S11, the eighteenth pin P connects the source input of the tenth silicon carbide MOS transistor chip S10, and the nineteenth pin P connects the gate control of the tenth silicon carbide MOS transistor chip S10;

[0133] The twenty-first pin P is connected with the W-phase voltage detection, the twenty-second pin P is connected with the gate control of the sixth silicon carbide MOS tube chip S6, the twenty-third pin P is connected with the gate control of the fifth silicon carbide MOS tube chip S5, the twenty-fourth pin P is connected with the V-phase voltage detection, the twenty-fifth pin P is connected with the gate control of the second silicon carbide MOS tube chip S2, the twenty-sixth pin P is connected with the gate control of the first silicon carbide MOS tube chip S1, the twenty-seventh pin P is connected with the U-phase voltage detection, and the twenty-eighth pin P is connected with the gate control of the fourth silicon carbide MOS tube chip S4;

[0134] The twenty-ninth pin P is connected with the cathode of the three-phase rectifier bridge, and the thirtieth pin P is connected with the zero point.

[0135] It can be understood that the existing PIM2 package contains 30 pins P, and the size and shape of the power module can be maintained the same as the existing PIM2 package in the application, and the electrodes of the Vienna circuit and the power chip 230 in the three-phase full-bridge circuit 220 are correspondingly arranged to the 30 pins P, and the definition of each pin P is the same as that of the corresponding pin P in the existing PIM2, so that the customer drive end of the power module using the existing PIM2 package can be directly compatible without secondary development of the customer drive end.

[0136] Further, referring to Figure 1 , Figure 4 and Figure 5 , the lead frame comprises a plurality of setting lead frames and a plurality of connecting lead frames; wherein:

[0137] The setting lead frame is provided with a plurality of silicon carbide power chips 230, and the drain electrode of the silicon carbide MOS tube chip is welded on the setting lead frame. The setting lead frame leads out the electrodes of the set silicon carbide power chip 230 to the same pin P, the same setting lead frame or the same electrode of the silicon carbide power chip 230.

[0138] The connecting lead frame is connected with the drain electrode or the source electrode of the silicon carbide MOS tube chip through the bonding wire 400, and leads out the drain electrode or the source electrode of the silicon carbide MOS tube chip to the corresponding pin P.

[0139] The setting lead frame is provided with a silicon carbide diode or a silicon carbide MOS tube, and the setting lead frame conducts the electrodes welded on the power chip 230 arranged thereon and leads them out to the pin P, the lead frame or the electrodes of other power chips 230 which need to be connected.

[0140] The connecting lead frame is not provided with a power chip 230, and is simply a bridge for electrical connection.

[0141] It can be understood that the height of the PIN of the pin P is higher than the surface of the power chip 230, so if the electrode of the power chip 230 is directly bonded to the corresponding pin P, it will cause excessive arc, which is easy to damage the bonding point and the power chip 230; In order to avoid this problem, the connecting lead frame is set in the embodiment, and the electrode of the power chip 230 is first bonded to the connecting lead frame, and then bonded to the corresponding pin P from the connecting lead frame, so as to avoid damage to the bonding point and the power chip 230 caused by arc, and ensure the reliability of the power module.

[0142] Specifically, part of the electrode of the silicon carbide diode, the drain electrode of the silicon carbide MOS tube can be led out to the corresponding pin P through the welding of the setting lead frame, and part of the electrode of the silicon carbide diode, the gate electrode and the source electrode of the silicon carbide MOS tube can be led out to the corresponding pin P through the corresponding connecting lead frame.

[0143] Further, the setting lead frame includes a first setting lead frame 211, a second setting lead frame 212, a third setting lead frame 213 and a fourth setting lead frame 214; The first silicon carbide diode chip D1 and the first silicon carbide MOS tube chip S1 are arranged on the first setting lead frame 211, the second silicon carbide diode chip D2 and the second silicon carbide MOS tube chip S2 are arranged on the second setting lead frame 212, the fourth silicon carbide diode chip D4 is arranged on the third setting lead frame 213, and the second silicon carbide diode chip D2 and the fifth silicon carbide diode chip D5 are arranged on the fourth setting lead frame 214; Wherein:

[0144] The first setting lead frame 211 and the second setting lead frame 212 are half working type, so the straight edge of the first setting lead frame 211 is arranged opposite to the straight edge of the second setting lead frame 212;

[0145] The third setting lead frame 213 is arranged on the concave edge of the first setting lead frame 211, and the fourth setting lead frame 214 is arranged on the concave edge of the second setting lead frame 212;

[0146] The third setting lead frame 213 and the fourth setting lead frame 214 are connected through the bonding wire 400 across the concave edges of the first setting lead frame 211 and the second setting lead frame 212.

[0147] It can be understood that the longer the current transmission path is, the higher the parasitic resistance and parasitic inductance will be, which affects the normal operation of the power module; therefore, in order to reduce the influence of parasitic resistance and parasitic inductance, in the embodiment, the first setting lead frame 211 and the second setting lead frame 212 are set as a half-working type, the half-working type frame has a straight edge on the bottom edge, and the opposite bottom edge has a concave edge, and two platforms on which the power chips 230 can be arranged are formed at both ends.

[0148] The straight edges of the first setting lead frame 211 and the second setting lead frame 212 are arranged opposite to each other, and the third setting lead frame 213 and the fourth setting lead frame 214 are arranged at the concave edge positions of the first setting lead frame 211 and the second setting lead frame 212 respectively, so that the third setting lead frame 213 and the fourth setting lead frame 214 are only separated by the concave bottom of the first setting lead frame 211 and the second setting lead frame 212, greatly shortening the length of the bonding wire 400 between the third setting lead frame 213 and the fourth setting lead frame 214, thereby reducing the parasitic resistance and parasitic inductance.

[0149] Further, the setting lead frame further comprises a fifth setting lead frame 215, a sixth setting lead frame 216, a seventh setting lead frame 217, an eighth setting lead frame 218, a ninth setting lead frame 219, a tenth setting lead frame 21A and an eleventh setting lead frame 21B;

[0150] The fourth silicon carbide MOS tube chip S4, the fifth silicon carbide MOS tube chip S5 and the sixth silicon carbide MOS tube chip S6 are arranged on the fifth setting lead frame 215, the third silicon carbide diode chip D3 is arranged on the sixth setting lead frame 216, and the third silicon carbide MOS tube chip S3 is arranged on the seventh setting lead frame 217, and the sixth setting lead frame 216 and the seventh setting lead frame 217 are connected through the bonding wire 400;

[0151] The tenth silicon carbide MOS tube chip S10 is arranged on the eighth setting lead frame 218, the eleventh silicon carbide MOS tube chip S11 is arranged on the ninth setting lead frame 219, and the twelfth silicon carbide MOS tube chip S12 is arranged on the tenth setting lead frame 21A;

[0152] The seventh silicon carbide MOS tube chip S7, the eighth silicon carbide MOS tube chip S8 and the ninth silicon carbide MOS tube chip S9 are arranged on the eleventh setting lead frame 21B;

[0153] Wherein:

[0154] The first setting lead frame 211 is connected with the anode electrode of the fourth silicon carbide diode chip D4 through the bonding wire 400, the second setting lead frame 212 is connected with the anode electrode of the fifth silicon carbide diode chip D5 through the bonding wire 400, and the sixth setting lead frame 216 is connected with the anode electrode of the sixth silicon carbide diode chip D6 through the bonding wire 400;

[0155] The eighth setting lead frame 218 is connected with the source electrode of the seventh silicon carbide MOS tube chip S7 through the bonding wire 400, the ninth setting lead frame 219 is connected with the source electrode of the eighth silicon carbide MOS tube chip S8 through the bonding wire 400, and the tenth setting lead frame 21A is connected with the source electrode of the ninth silicon carbide MOS tube chip S9 through the bonding wire 400.

[0156] In the embodiment, the cathode electrode of the silicon carbide diode, part of the anode electrode, and the drain electrode of the silicon carbide MOS tube are led out to the corresponding pin P by the setting lead frame;

[0157] Specifically, the cathode electrode of the first silicon carbide diode D1 and the drain electrode of the first silicon carbide MOS tube are welded on the first setting lead frame 211 and led out to the pin P2 by the first setting lead frame 211;

[0158] The cathode electrode of the second silicon carbide diode D2 and the drain electrode of the second silicon carbide MOS tube are welded on the second setting lead frame 212 and led out to the pin P3 by the second setting lead frame 212;

[0159] The cathode electrode of the fourth silicon carbide diode D4 is welded on the third setting lead frame 213 and led out to the pin P29 by the third setting lead frame 213;

[0160] The cathode electrodes of the fifth silicon carbide diode D5 and the sixth silicon carbide diode D6 are welded on the third setting lead frame 213 and led out to the pin P29 by the third setting lead frame 213; the anode of the fifth silicon carbide diode D5 is first bonded to the second setting lead frame 212 and then led out to the pin P3; and the anode of the sixth silicon carbide diode D6 is first bonded to the sixth setting lead frame 216 and then led out to the pin P4;

[0161] The drain electrode of the fourth silicon carbide MOS tube, the drain electrode of the fifth silicon carbide MOS tube, and the drain electrode of the sixth silicon carbide MOS tube are welded on the fifth setting lead frame 215 and led out to the pin P30 by the fifth setting lead frame 215;

[0162] The cathode electrode of the third silicon carbide diode D3 is welded on the sixth setting lead frame 216 and led out to the pin P4 by the sixth setting lead frame 216;

[0163] The drain electrode of the third silicon carbide MOS tube is welded on the seventh setting lead frame 217, which is first bonded to the sixth setting lead frame 216 and then led out to the pin P4;

[0164] The drain electrode of the tenth silicon carbide MOS tube is welded on the eighth setting lead frame 218, which is bonded to the source electrode of the seventh silicon carbide MOS tube;

[0165] The drain electrode of the eleventh silicon carbide MOS tube is welded on the ninth setting lead frame 219, which is bonded to the source electrode of the eighth silicon carbide MOS tube;

[0166] The drain electrode of the twelfth silicon carbide MOS tube is welded on the tenth setting lead frame 21A, which is bonded to the source electrode of the ninth silicon carbide MOS tube;

[0167] The drains of the seventh, eighth and ninth silicon carbide MOS tubes are welded on the eleventh setting lead frame 21B, which is led out to the pin P5.

[0168] Further, the connection lead frames include six first connection lead frames 221, three second connection lead frames 222, one third connection lead frame 223, six fourth connection lead frames 224 and six fifth connection lead frames 225; wherein:

[0169] The first connection lead frame 221 is connected to the gate electrode of the silicon carbide MOS tube chip in the Vienna rectifier circuit 210 through the bonding wire 400 and led out to the corresponding pin P, and the first connection lead frame 221 is arranged between the setting lead frame where the corresponding silicon carbide MOS tube chip is located and the corresponding pin P;

[0170] The second connection lead frame 222 is connected to the source electrode of two silicon carbide MOS tube chips of the same phase in the Vienna rectifier circuit 210 through the bonding wire 400 respectively, and led out to the corresponding pin P, and the second connection lead frame 222 is arranged between the setting lead frames where the two silicon carbide MOS tube chips are located;

[0171] The third connection lead frame 223 is connected to the anode electrode of the first, second and third silicon carbide diode chips D1, D2 and D3 through the bonding wire 400 respectively, and led out to the corresponding pin P, and the third connection lead frame 223 is arranged between the setting lead frame where the corresponding silicon carbide diode chip is located and the corresponding pin P;

[0172] The fourth connection lead frame 224 is connected with the gate electrodes of the silicon carbide MOS tube chips in the three-phase full-bridge circuit 220 through the bonding wires 400 respectively and led out to the corresponding pins P, and the fourth connection lead frame 224 is arranged between the arranged lead frame where the corresponding silicon carbide MOS tube chip is arranged and the corresponding pin P.

[0173] The fifth connection lead frame 225 is connected with the source electrodes of the silicon carbide MOS tube chips in the three-phase full-bridge circuit 220 through the bonding wires 400 respectively and led out to the corresponding pins P, and the fifth connection lead frame 225 is arranged between the arranged lead frame where the corresponding silicon carbide MOS tube chip is arranged and the corresponding pin P.

[0174] Specifically, the anode electrodes of the partial first silicon carbide diode D1, the source electrodes and the gate electrodes of the first silicon carbide MOS tube are led out to the corresponding pins P through the connection lead frame.

[0175] Specifically, the anode electrodes of the first silicon carbide diode chip D1, the second silicon carbide diode chip D2 and the third silicon carbide diode chip D3 are led out to the pin P1 through a third connection lead frame 223.

[0176] The source electrodes of the first silicon carbide MOS tube chip S1 and the fourth silicon carbide MOS tube chip S4 are led out to the pin P27 through a second connection lead frame 222; the source electrodes of the second silicon carbide MOS tube chip S2 and the fifth silicon carbide MOS tube chip S5 are led out to the pin P24 through a second connection lead frame 222; the source electrodes of the third silicon carbide MOS tube chip S3 and the sixth silicon carbide MOS tube chip S6 are led out to the pin P21 through a second connection lead frame 222.

[0177] The gates of the first to sixth silicon carbide MOS tube chips S6 are led out to the pins P26, 25, 20, 28, 23 and 22 respectively through the corresponding first connection lead frame 221; the gates of the seventh to twelfth silicon carbide MOS tube chips S12 are led out to the pins P7, 9, 11, 19, 17 and 15 respectively through the corresponding fourth connection lead frame 224.

[0178] The source electrodes of the seventh to twelfth silicon carbide MOS tube chips S12 are led out to the pins P6, 8, 10, 18, 16 and 14 respectively through the corresponding fifth connection lead frame 225.

[0179] The specific type of the bonding wire 400 can be set based on actual needs; see Figure 1 、 Figure 4For example, the gate bonding wire 400 of a silicon carbide MOSFET is an 8-mil diameter aluminum wire, while the other bonding wires 400 are 12-mil diameter aluminum wires. The electrodes of a silicon carbide MOSFET are connected by four bonding wires 400, and the electrodes of a silicon carbide diode are connected by six bonding wires 400. (See also...) Figure 6 , Figure 7 For example, the gate bonding wire 400 of a silicon carbide MOSFET is an 8-mil diameter aluminum wire, while the other bonding wires 400 are 20-mil diameter aluminum wires. The electrodes on a silicon carbide MOSFET are connected by two bonding wires 400, and the electrodes on a silicon carbide diode are connected by four bonding wires 400. It is understandable that a smaller diameter and more bonding wires 400 can shorten the process time and use less material, saving costs, but increasing the bonding difficulty. Conversely, a larger diameter and fewer bonding wires 400 can increase the process time and use more material, but reduce the bonding difficulty. Therefore, the number of bonding wires 400 can be set based on actual needs.

[0180] Further, the liner 100 includes a first liner 100 and a second liner 100; wherein:

[0181] The first liner 100 is provided with the first to sixth lead wire frames 211 to 216 and the third connecting lead wire frame 223;

[0182] The second liner 100 is provided with the seventh to eleventh lead wire frames 217 to 21B and the fourth to fifth connecting lead wire frames 225;

[0183] The first connecting lead frame 221 corresponding to the first silicon carbide MOSFET chip S1, the second silicon carbide MOSFET chip S2, the fourth silicon carbide MOSFET chip S4, the fifth silicon carbide MOSFET chip S5, and the sixth silicon carbide MOSFET chip S6 is disposed on the first substrate 100.

[0184] The first connection lead frame 221 corresponding to the third silicon carbide MOS transistor chip S3 is disposed on the second substrate 100;

[0185] The second connecting lead frame 222 corresponding to the first silicon carbide MOSFET chip S1, the second silicon carbide MOSFET chip S2, the fourth silicon carbide MOSFET chip S4, and the fifth silicon carbide MOSFET chip S5 is disposed on the first substrate 100.

[0186] The second connecting lead frame 222 corresponding to the third silicon carbide MOS transistor chip S3 and the sixth silicon carbide MOS transistor chip S6 is disposed on the second substrate 100.

[0187] In the embodiment, the Vienna rectifier circuit 210 and the three-phase full-bridge circuit 220 topology are integrated on the first substrate 100 and the second substrate 100 with equal areas, and on this basis, the lead frame is arranged to realize the compatibility of the existing pins P.

[0188] Further, the substrate 100 is a ceramic substrate 100.

[0189] The substrate 100 in the embodiment is a ceramic substrate 100, which comprises a three-layer structure, the upper and lower layers are copper-clad layers, and the middle layer is a ceramic layer.

[0190] Further, referring to Figure 8 , the power module further comprises a packaging side frame 500, a substrate 600 and a packaging cover plate 700, wherein:

[0191] The side edge of the packaging side frame 500 is provided with a pin P, the substrate 600 is arranged in the packaging side frame 500, the substrate 100 is arranged on the substrate 600, and the packaging cover plate 700 is arranged on the power circuit 200.

[0192] The packaging side frame 500 is used for arranging the pin P, the substrate 600 is used for carrying the substrate 100 and the power circuit 200 on the substrate 100, and the packaging side frame 500, the substrate 600 and the packaging cover plate 700 jointly form a packaging space, and the substrate 100 and the power circuit 200 are arranged in the packaging space.

[0193] After the bonding process is completed, the parts are assembled, and the assembled power module is subjected to glue pouring treatment to isolate water vapor and improve the reliability of the power module.

[0194] In the utility model, the terms "first", "second", "third", "fourth", "fifth" are only used for the purpose of description, and cannot be understood as indicating or implying relative importance, and for ordinary skilled in the art, the specific meaning of the above terms in the utility model can be understood according to specific circumstances.

[0195] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. Furthermore, different embodiments or examples described in the present specification and the features of different embodiments or examples can be combined and modified by those skilled in the art without contradiction, and the combinations and modifications are included in the scope of the present application.

[0196] Although the embodiments of the present application have been shown and described above, the scope of the present application is not limited thereto. It is understood that the above-described embodiments are exemplary, and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications and replacements to the above-described embodiments within the scope of the present application. These changes, modifications and replacements should be included in the scope of the present application. Therefore, the scope of the present application should be determined by the scope of the claims.

Claims

1. A power module, characterized by The power module comprises a backing plate and a power circuit arranged on the backing plate, the power circuit comprises a Vienna rectifier circuit and a three-phase full-bridge circuit, an output end of the Vienna rectifier circuit is connected with an input end of the three-phase full-bridge circuit; wherein: The power chips in the Vienna rectifier circuit and the three-phase full-bridge circuit adopt silicon carbide power chips.

2. The power module of claim 1, wherein, The power module further comprises a lead frame and a plurality of pins; the Vienna rectifier circuit comprises a three-phase rectifier bridge composed of a first silicon carbide diode chip, a second silicon carbide diode chip, a third silicon carbide diode chip, a fourth silicon carbide diode chip, a fifth silicon carbide diode chip and a sixth silicon carbide diode chip, and a three-phase bidirectional switch composed of a first silicon carbide MOS tube chip, a second silicon carbide MOS tube chip, a third silicon carbide MOS tube chip, a fourth silicon carbide MOS tube chip, a fifth silicon carbide MOS tube chip and a sixth silicon carbide MOS tube chip; the three-phase full-bridge circuit is composed of a seventh silicon carbide MOS tube chip, an eighth silicon carbide MOS tube chip, a ninth silicon carbide MOS tube chip, a tenth silicon carbide MOS tube chip, an eleventh silicon carbide MOS tube chip and a twelfth silicon carbide MOS tube chip; wherein: The electrodes of the silicon carbide diode chips and the silicon carbide MOS tube chips are led out to the pins through the lead frame.

3. The power module of claim 2, wherein: The anode electrodes of the first silicon carbide diode chip, the second silicon carbide diode chip and the third silicon carbide diode chip are led out to a first pin through the lead frame; The cathode electrode of the first silicon carbide diode chip, the anode electrode of the fourth silicon carbide diode chip and the drain electrode of the first silicon carbide MOS tube chip are led out to a second pin through the lead frame; The cathode electrode of the second silicon carbide diode chip, the anode electrode of the fifth silicon carbide diode chip and the drain electrode of the second silicon carbide MOS tube chip are led out to a third pin through the lead frame; The cathode electrode of the third silicon carbide diode chip, the anode electrode of the sixth silicon carbide diode chip and the drain electrode of the third silicon carbide MOS tube chip are led out to a fourth pin through the lead frame; The cathode electrodes of the fourth silicon carbide diode chip, the fifth silicon carbide diode chip and the sixth silicon carbide diode chip are led out to a twenty-ninth pin through the lead frame; The drain electrode of the seventh silicon carbide MOS tube chip, the drain electrode of the eighth silicon carbide MOS tube chip and the drain electrode of the ninth silicon carbide MOS tube chip are led out to a fifth pin through the lead frame; The source electrode of the seventh silicon carbide MOS tube chip and the drain electrode of the tenth silicon carbide MOS tube chip are led out to a sixth pin through the lead frame; The gate electrode of the seventh silicon carbide MOS tube chip is led out to a seventh pin through the lead frame; The source electrode of the eighth silicon carbide MOS tube chip and the drain electrode of the eleventh silicon carbide MOS tube chip are led out to an eighth pin through the lead frame; The gate electrode of the eighth silicon carbide MOS tube core piece is led out to a ninth pin through the lead frame; The source electrode of the ninth silicon carbide MOS tube core piece, the drain electrode of the twelfth silicon carbide MOS tube core piece are led out to a tenth pin through the lead frame; The gate electrode of the ninth silicon carbide MOS tube core piece is led out to an eleventh pin through the lead frame; The source electrode of the twelfth silicon carbide MOS tube core piece is led out to a fourteenth pin through the lead frame; The gate electrode of the twelfth silicon carbide MOS tube core piece is led out to a fifteenth pin through the lead frame; The source electrode of the eleventh silicon carbide MOS tube core piece is led out to a sixteenth pin through the lead frame; The gate electrode of the eleventh silicon carbide MOS tube core piece is led out to a seventeenth pin through the lead frame; The source electrode of the tenth silicon carbide MOS tube core piece is led out to an eighteenth pin through the lead frame; The gate electrode of the tenth silicon carbide MOS tube core piece is led out to a nineteenth pin through the lead frame; The gate electrode of the third silicon carbide MOS tube core piece is led out to a twentieth pin through the lead frame; The source electrode of the third silicon carbide MOS tube core piece, the source electrode of the sixth silicon carbide MOS tube core piece are led out to a twenty-first pin through the lead frame; The gate electrode of the sixth silicon carbide MOS tube core piece is led out to a twenty-second pin through the lead frame; The gate electrode of the fifth silicon carbide MOS tube core piece is led out to a twenty-third pin through the lead frame; The source electrode of the second silicon carbide MOS tube core piece, the source electrode of the fifth silicon carbide MOS tube core piece are led out to a twenty-fourth pin through the lead frame; The gate electrode of the second silicon carbide MOS tube core piece is led out to a twenty-fifth pin through the lead frame; The gate electrode of the first silicon carbide MOS tube core piece is led out to a twenty-sixth pin through the lead frame; The source electrode of the first silicon carbide MOS tube core piece, the source electrode of the fourth silicon carbide MOS tube core piece are led out to a twenty-seventh pin through the lead frame; The gate electrode of the fourth silicon carbide MOS tube core piece is led out to a twenty-eighth pin through the lead frame; The drain electrodes of the fourth silicon carbide MOS tube core piece, fifth silicon carbide MOS tube core piece, sixth silicon carbide MOS tube core piece are led out to a thirtieth pin through the lead frame.

4. The power module of claim 2, wherein, The lead frame comprises a plurality of setting lead frames and a plurality of connecting lead frames; wherein: The setting lead frame is provided with a plurality of silicon carbide power core pieces, and the drain electrode of the silicon carbide MOS tube core piece is welded on the setting lead frame, and the setting lead frame leads out the electrodes of the set silicon carbide power core pieces to the same pin, the same setting lead frame or the electrodes of the same silicon carbide power core piece; The connecting lead frame is connected with the drain electrode or the source electrode of the silicon carbide MOS tube core piece through a bonding wire, and leads out the drain electrode or the source electrode of the silicon carbide MOS tube core piece to the corresponding pin.

5. The power module of claim 4, wherein, The setting lead frame includes a first setting lead frame, a second setting lead frame, a third setting lead frame and a fourth setting lead frame; the first setting lead frame is provided with the first silicon carbide diode chip and the first silicon carbide MOS tube chip, the second setting lead frame is provided with the second silicon carbide diode chip and the second silicon carbide MOS tube chip, the third setting lead frame is provided with the fourth silicon carbide diode chip, and the fourth setting lead frame is provided with the second silicon carbide diode chip and the fifth silicon carbide diode chip; wherein: The first setting lead frame and the second setting lead frame are half work type, so that the straight edge of the first setting lead frame is oppositely arranged with the straight edge of the second setting lead frame; The third setting lead frame is arranged on the concave edge of the first setting lead frame, and the fourth setting lead frame is arranged on the concave edge of the second setting lead frame; The third setting lead frame and the fourth setting lead frame are connected through the bonding wire across the concave edges of the first setting lead frame and the second setting lead frame.

6. The power module of claim 5, wherein, The setting lead frame further includes a fifth setting lead frame, a sixth setting lead frame, a seventh setting lead frame, an eighth setting lead frame, a ninth setting lead frame, a tenth setting lead frame and an eleventh setting lead frame; The fifth setting lead frame is provided with the fourth silicon carbide MOS tube chip, the fifth silicon carbide MOS tube chip and the sixth silicon carbide MOS tube chip, the sixth setting lead frame is provided with the third silicon carbide diode chip, the seventh setting lead frame is provided with the third silicon carbide MOS tube chip, and the sixth setting lead frame and the seventh setting lead frame are connected through the bonding wire; The eighth setting lead frame is provided with the tenth silicon carbide MOS tube chip, the ninth setting lead frame is provided with the eleventh silicon carbide MOS tube chip, and the tenth setting lead frame is provided with the twelfth silicon carbide MOS tube chip; The eleventh setting lead frame is provided with the seventh silicon carbide MOS tube chip, the eighth silicon carbide MOS tube chip and the ninth silicon carbide MOS tube chip; Wherein: The first setting lead frame and the anode electrode of the fourth silicon carbide diode chip are connected through the bonding wire, the second setting lead frame and the anode electrode of the fifth silicon carbide diode chip are connected through the bonding wire, and the sixth setting lead frame and the anode electrode of the sixth silicon carbide diode chip are connected through the bonding wire; The eighth setting lead frame and the source electrode of the seventh silicon carbide MOS tube chip are connected through the bonding wire, the ninth setting lead frame and the source electrode of the eighth silicon carbide MOS tube chip are connected through the bonding wire, and the tenth setting lead frame and the source electrode of the ninth silicon carbide MOS tube chip are connected through the bonding wire.

7. The power module of claim 4, wherein, The connecting lead frame comprises six first connecting lead frames, three second connecting lead frames, one third connecting lead frame, six fourth connecting lead frames and six fifth connecting lead frames; wherein: The first connecting lead frame is connected with the gate electrode of the silicon carbide MOS tube chip in the Vienna rectifier circuit through a bonding wire and is led out to the corresponding pin, and the first connecting lead frame is arranged between the setting lead frame where the corresponding silicon carbide MOS tube chip is arranged and the corresponding pin; The second connecting lead frame is respectively connected with the source electrode of two silicon carbide MOS tube chips of the same phase in the Vienna rectifier circuit through a bonding wire and is led out to the corresponding pin, and the second connecting lead frame is arranged between the setting lead frames where the two silicon carbide MOS tube chips are arranged; The third connecting lead frame is respectively connected with the anode electrode of the first silicon carbide diode chip, the second silicon carbide diode chip and the third silicon carbide diode chip through a bonding wire and is led out to the corresponding pin, and the third connecting lead frame is arranged between the setting lead frame where the corresponding silicon carbide diode chip is arranged and the corresponding pin; The fourth connecting lead frame is respectively connected with the gate electrode of the silicon carbide MOS tube chip in the three-phase full-bridge circuit through a bonding wire and is led out to the corresponding pin, and the fourth connecting lead frame is arranged between the setting lead frame where the corresponding silicon carbide MOS tube chip is arranged and the corresponding pin; The fifth connecting lead frame is respectively connected with the source electrode of the silicon carbide MOS tube chip in the three-phase full-bridge circuit through a bonding wire and is led out to the corresponding pin, and the fifth connecting lead frame is arranged between the setting lead frame where the corresponding silicon carbide MOS tube chip is arranged and the corresponding pin.

8. The power module of any of claims 5 to 7, wherein, The backing plate comprises a first backing plate and a second backing plate; wherein: The first to sixth setting lead frames and the third connecting lead frame are arranged on the first backing plate; The seventh to eleventh setting lead frames and the fourth to fifth connecting lead frames are arranged on the second backing plate; The first connecting lead frame corresponding to the first silicon carbide MOS tube chip, the second silicon carbide MOS tube chip, the fourth silicon carbide MOS tube chip, the fifth silicon carbide MOS tube chip and the sixth silicon carbide MOS tube chip is arranged on the first backing plate; The first connecting lead frame corresponding to the third silicon carbide MOS tube chip is arranged on the second backing plate; The second connecting lead frame corresponding to the first silicon carbide MOS tube chip, the second silicon carbide MOS tube chip, the fourth silicon carbide MOS tube chip and the fifth silicon carbide MOS tube chip is arranged on the first backing plate; The second connecting lead frame corresponding to the third silicon carbide MOS tube chip and the sixth silicon carbide MOS tube chip is arranged on the second backing plate.

9. The power module of claim 1, wherein, The power module further comprises a packaging side frame, a substrate and a packaging cover plate; wherein: The side edge of the packaging side frame is provided with a pin, the substrate is arranged in the packaging side frame, the backing plate is arranged on the substrate, and the packaging cover plate is arranged on the power circuit.

10. The power module of claim 1, wherein, The backing plate is a ceramic backing plate.

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