Earphone circuit for eliminating POP sound, earphone system and earphone

Abstract

The utility model relates to an earphone circuit for eliminating POP sound, an earphone system and an earphone. The earphone circuit comprises a codec, a first control circuit, a second control circuit and a master control circuit or a time delay circuit. The first control circuit is connected with the codec, and the codec and the second control circuit are also connected to an earphone jack; the first control circuit and the second control circuit are also connected with the main control circuit or the time delay circuit; the codec is used for outputting a first level signal according to the state of the earphone jack, the first control circuit is used for outputting a second level signal according to the first level signal, and the main control circuit or the time delay circuit is used for controlling time delay according to the second level signal so as to keep an audio signal in a mute state and outputting a third level signal; the second control circuit is used for controlling the earphone jack to be released according to the third level signal so as to output an audio signal; the earphone can accurately control the release of the audio signal so as to enable the mute state to be kept for a proper time length, thereby effectively eliminating the POP sound in the earphone.

Description

TECHNICAL FIELD

[0001] The utility model relates to earphone technical field more specifically, relate to earphone circuit, earphone system and earphone of eliminating POP sound. BACKGROUND

[0002] In prior art, in order to eliminate the POP sound in earphone, the conventional method is that EC / MCU identifies the insertion / withdrawal state of earphone through the jack identification pin of earphone jack, and then outputs mute signal to control the earphone audio signal to be in "control" or "release" state, which has certain effect, but this method still cannot eliminate the earphone POP sound during the process of starting with earphone plugged in or waking up, when the earphone is plugged in and the above-mentioned operation is performed, the jack identification pin of earphone jack has no level state change, so that EC / MCU has no accurate reference point, and then cannot further accurately output mute signal, and when affected by system, drive and hardware performance and other factors, the time point of loading audio drive during starting process is inaccurate, which leads to longer control time, and the earphone is released before entering desktop, so that the earphone is silent for a long time after waking up. UTILITY MODEL CONTENT

[0003] The utility model solves the technical problem in prior art, and provides earphone circuit, earphone system and earphone for eliminating POP sound.

[0004] The utility model adopts the technical scheme that:

[0005] On the one hand, the utility model provides earphone circuit for eliminating POP sound, including codec, first control circuit, second control circuit and main control circuit or delay circuit, the first control circuit is connected with codec, and the codec and second control circuit are also connected to earphone jack, and the first control circuit and second control circuit are also connected with main control circuit or delay circuit,

[0006] The codec is used to output first level signal to the first control circuit according to the state of earphone jack, the first control circuit is used to output second level signal to the main control circuit or delay circuit according to the first level signal, the main control circuit or delay circuit is used to control delay according to the second level signal to make audio signal keep mute state and output third level signal to the second control circuit, and the second control circuit is used to control earphone jack to release to output audio signal according to the third level signal.

[0007] In some embodiments, the first control circuit comprises a first resistor, a second resistor and a first MOS tube, one end of the first resistor is connected with the codec, the other end of the first resistor is connected with the gate of the first MOS tube; the drain of the first MOS tube is connected with one end of the second resistor and the master control circuit or the delay circuit respectively, the other end of the second resistor is connected to the power supply end, and the source of the first MOS tube is grounded.

[0008] In some embodiments, a first parasitic diode is connected between the drain and the source of the first MOS tube; and the first MOS tube is an N-type MOS tube.

[0009] In some embodiments, the delay circuit comprises a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a capacitor, a second MOS tube and a third MOS tube; one end of the third resistor is connected with the first control circuit, the other end of the third resistor is connected with one end of the fourth resistor and the gate of the second MOS tube respectively; the drain of the second MOS tube is connected with one end of the fifth resistor, one end of the sixth resistor, one end of the capacitor and the gate of the third MOS tube respectively; the drain of the third MOS tube is connected with one end of the seventh resistor and the second control circuit respectively; the other end of the fifth resistor and the other end of the seventh resistor are both connected to the power supply end; the other end of the fourth resistor, the other end of the sixth resistor, the other end of the capacitor, the source of the second MOS tube and the source of the third MOS tube are all grounded.

[0010] In some embodiments, a second parasitic diode is connected between the drain and the source of the second MOS tube and the third MOS tube respectively; and the second MOS tube and the third MOS tube are both N-type MOS tubes.

[0011] In some embodiments, the second control circuit comprises an eighth resistor, a ninth resistor, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube; one end of the eighth resistor is connected with the master control circuit or the delay circuit, the other end of the eighth resistor is connected with one end of the ninth resistor, the gate of the fourth MOS tube, the gate of the fifth MOS tube, the gate of the sixth MOS tube and the gate of the seventh MOS tube respectively; the drain of the fourth MOS tube, the drain of the fifth MOS tube, the drain of the sixth MOS tube and the drain of the seventh MOS tube are all connected to the earphone jack; the other end of the ninth resistor is grounded; the source of the fourth MOS tube, the source of the fifth MOS tube, the source of the sixth MOS tube and the source of the seventh MOS tube are all connected to the ground wire.

[0012] In some embodiments, a third parasitic diode is connected between the drain and the source of each of the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor; and each of the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor is an N-type MOS transistor.

[0013] In some embodiments, the master control circuit comprises an EC unit or an MCU unit.

[0014] In another aspect, the utility model also provides a earphone system, including the earphone circuit of eliminating POP sound of any above.

[0015] In another aspect, the utility model also provides a earphone, including the earphone system of above.

[0016] The utility model has the advantages that, different from the prior art, in the earphone circuit of eliminating POP sound of the utility model, the codec is used for outputting a first level signal according to the state of the earphone jack, the first control circuit is used for outputting a second level signal according to the first level signal, the master control circuit or the delay circuit is used for controlling the delay according to the second level signal to make the audio signal keep the mute state and output a third level signal, and the second control circuit is used for controlling the earphone jack to be released to output the audio signal according to the third level signal, which can accurately control the release of the audio signal to make the mute state keep for a proper time length, thereby effectively eliminating the POP sound in the earphone. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a principle block diagram of the earphone circuit of eliminating POP sound in the utility model embodiment;

[0018] Figure 2 is a link schematic view of the earphone circuit of eliminating POP sound in the utility model embodiment;

[0019] Figure 3 is another principle block diagram of the earphone circuit of eliminating POP sound in the utility model embodiment;

[0020] Figure 4 is a circuit schematic view of the first control circuit in the utility model embodiment;

[0021] Figure 5 is a circuit schematic view of the delay circuit in the utility model embodiment;

[0022] Figure 6 is a circuit schematic view of the second control circuit in the utility model embodiment;

[0023] Figure 7 is a connection schematic view of the master control circuit in the utility model embodiment;

[0024] Figure 8 is a control timing diagram of the earphone circuit for eliminating the POP sound in the embodiments of the utility model;

[0025] The names and serial numbers in the figure are as follows: codec-10; first control circuit-20; second control circuit-30; main control circuit-40; delay circuit-50; earphone jack-60. DETAILED DESCRIPTION

[0026] The terms "first", "second", "third", and "fourth" and the like in the description and claims of the utility model and the accompanying drawings are used to distinguish different objects, and are not used to describe a particular order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0027] In this paper, the "embodiment" means that the specific features, structures or characteristics described in conjunction with the embodiment can be included in at least one embodiment of the utility model. The appearance of this phrase in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is not mutually exclusive with other embodiments. The skilled person in the art explicitly and implicitly understands that the embodiments described herein can be combined with other embodiments.

[0028] "Multiple" means two or more. "And / or", which describes the relationship between the associated objects, means that there can be three relationships, for example, A and / or B, which can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after are in an "or" relationship.

[0029] Moreover, the terms "up, down, front, back, left, right, upper end, lower end" and the like indicating the orientation are all based on the attitude position of the device or equipment described in the scheme in normal use.

[0030] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be described clearly and completely below. Obviously, the described embodiments are part of the embodiments of the utility model, not all. Based on the embodiments of the utility model, all other embodiments obtained by the person skilled in the art without creative labor belong to the protection scope of the utility model.

[0031] Embodiment one: the utility model embodiment provides a kind of earphone circuit for eliminating the POP sound, such as Figure 1As shown in the earphone circuit for eliminating the POP sound in the above embodiment, the earphone circuit comprises a codec 10, a first control circuit 20, a second control circuit 30 and a master control circuit 40; the first control circuit 20 is connected to the codec 10, and the codec 10 and the second control circuit 30 are both connected to an earphone jack 60; the first control circuit 20 and the second control circuit 30 are both connected to the master control circuit 40; the codec 10 is configured to output a first level signal to the first control circuit 20 according to a state of the earphone jack 60, the first control circuit 20 is configured to output a second level signal to the master control circuit 40 according to the first level signal, the master control circuit 40 is configured to control a delay time to keep the audio signal in a mute state and output a third level signal to the second control circuit 30 according to the second level signal, and the second control circuit 30 is configured to control the earphone jack 60 to release to output the audio signal according to the third level signal. The signal is HP_MUTE. For details, see Figure 2 After the codec 10 identifies the Jack Detect signal or the signal of starting to load the audio driver with the earphone plugged in, the codec 10 outputs the MIC_VREF, which rises from 0V to the maximum 3.2V (defined according to the datasheet of the codec 10), then pulls down the MUTE_CTL to the master control circuit 40 through the first control circuit 20, the master control circuit 40 controls the delay time, for example, 1s, and pulls down the HP_MUTE to the second control circuit 30, and the second control circuit 30 releases the earphone audio signal RING2 / SLEEVE / HPR / HPL to make the earphone work normally. Before the HP_MUTE is pulled down, the HP_MUTE keeps high level, and the second control circuit 30 controls the audio signal to GND and keeps the mute state without the POP sound. By controlling the delay time through the master control circuit 40, the delay time can be accurately adjusted according to the actual application needs.

[0032] In this embodiment, the master control circuit 40 comprises an EC unit or an MCU unit (EC / MCU). It should be noted that, in the case where the EC / MCU is not used, a delay circuit 50 can be used to replace the EC / MCU to control the delay time, for example, see Figure 3 This layout has low cost and good application effect.

[0033] For details, see Figure 4 The first control circuit 20 comprises a first resistor R1, a second resistor R2 and a first MOS tube Q1, one end of the first resistor R1 is connected to the codec 10, the other end of the first resistor R1 is connected to the gate of the first MOS tube Q1; the drain of the first MOS tube Q1 is connected to one end of the second resistor R2 and the master control circuit 40 or the delay circuit 50 respectively, the other end of the second resistor R2 is connected to a power supply end +V3P3A_EC, and the source of the first MOS tube Q1 is grounded.

[0034] The first parasitic diode is connected between the drain and the source of the first MOS tube Q1.

[0035] When the delay circuit 50 is used to replace the EC / MCU to make delay control, please refer to Figure 5 , the delay circuit 50 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a capacitor C1, a second MOS tube Q2 and a third MOS tube Q3; one end of the third resistor R3 is connected with the first control circuit 20, and the other end of the third resistor R3 is connected with one end of the fourth resistor R4 and the gate of the second MOS tube Q2 respectively; the drain of the second MOS tube Q2 is connected with one end of the fifth resistor R5, one end of the sixth resistor R6, one end of the capacitor C1 and the gate of the third MOS tube Q3 respectively; the drain of the third MOS tube Q3 is connected with one end of the seventh resistor R7 and the second control circuit 30 respectively; the other end of the fifth resistor R5 and the other end of the seventh resistor R7 are connected to the power supply end +V3P3A_EC; the other end of the fourth resistor R4, the other end of the sixth resistor R6, the other end of the capacitor C1, the source of the second MOS tube Q2 and the source of the third MOS tube Q3 are grounded.

[0036] The second parasitic diode is connected between the drain and the source of the second MOS tube Q2 and the third MOS tube Q3 respectively; the second MOS tube Q2 and the third MOS tube Q3 are N-type MOS tubes.

[0037] When the delay circuit 50 is used to replace the EC / MCU to make delay control, please refer to Figure 6 , the second control circuit 30 includes an eighth resistor R8, a ninth resistor R9, a fourth MOS tube Q4, a fifth MOS tube Q5, a sixth MOS tube Q6 and a seventh MOS tube Q7; one end of the eighth resistor R8 is connected with the main control circuit 40 or the delay circuit 50, and the other end of the eighth resistor R8 is connected with one end of the ninth resistor R9, the gate of the fourth MOS tube Q4, the gate of the fifth MOS tube Q5, the gate of the sixth MOS tube Q6 and the gate of the seventh MOS tube Q7 respectively; the drain of the fourth MOS tube Q4, the drain of the fifth MOS tube Q5, the drain of the sixth MOS tube Q6 and the drain of the seventh MOS tube Q7 are connected to the earphone jack 60; the other end of the ninth resistor R9 is grounded; the source of the fourth MOS tube Q4, the source of the fifth MOS tube Q5, the source of the sixth MOS tube Q6 and the source of the seventh MOS tube Q7 are connected with the ground wire.

[0038] The third parasitic diode is connected between the drain and the source of the fourth MOS tube Q4, the fifth MOS tube Q5, the sixth MOS tube Q6 and the seventh MOS tube Q7 respectively; the fourth MOS tube Q4, the fifth MOS tube Q5, the sixth MOS tube Q6 and the seventh MOS tube Q7 are N-type MOS tubes.

[0039] It can be understood that when the EC / MCU is used, the delay circuit 50 is replaced between the first control circuit 20 and the second control circuit 30. The connection mode of the EC / MCU is shown in the figure, for example. Figure 7 The specific circuit structure of the EC / MCU can adopt any suitable one in the prior art, and the embodiment is not limited specifically.

[0040] The following describes the earphone circuit for eliminating the POP sound in the embodiment, and the working principle in actual application is specifically explained:

[0041] When the earphone is plugged in and the machine is started, awakened or the earphone is plugged in the starting state, the codec 10 outputs the MIC_VREF high level (from low to high), and the first MOS tube Q1 pulls down the MUTE_CTL (from high to low). In the case of using the EC / MCU, the delay circuit 50 is not needed, and the MUTE_CTL is directly input to the EC / MCU. The EC / MCU pulls down the HP_MUTE (from high to low) after receiving the MUTE_CTL low level with a delay of 1s, and the fourth MOS tube Q4, the fifth MOS tube Q5, the sixth MOS tube Q6 and the seventh MOS tube Q7 are closed, the earphone audio signal HPR / HPL / SLEEVE / RING2 is released, and the earphone works normally.

[0042] In the case of not using the EC / MCU, the delay circuit 50 is needed to replace the EC / MCU to delay, for example, the MUTE_CTL is low, the second MOS tube Q2 is closed, the MUTE_CTL_R is slowly pulled up (slowly from low to high) through the RC circuit composed of the fifth resistor R5, the capacitor C1 and the sixth resistor R6, and when the MUTE_CTL_R is high enough, the HP_MUTE is pulled down through the third MOS tube Q3, so that the fourth MOS tube Q4, the fifth MOS tube Q5, the sixth MOS tube Q6 and the seventh MOS tube Q7 are closed, and the earphone works normally.

[0043] It should be noted that, first, the time length of the delay for eliminating the POP sound is preferably 1s, because the POP sound occurs almost within 1s of the audio driver loading, the codec 10 powering on, or the earphone being inserted, and abnormal fluctuations in the left and right channels HPR / HPL of the earphone or abnormal fluctuations in the SLEEVE / RING2 are directly introduced into the left and right channels. Therefore, before the HP_MUTE is pulled low, the HP_MUTE always remains high, and then the audio signal is pressed to GND by the fourth MOS tube Q4, the fifth MOS tube Q5, the sixth MOS tube Q6, and the seventh MOS tube Q7, that is, in the mute state, the abnormal fluctuations are pressed to GND to be eliminated. Of course, the control delay can also be adjusted according to the actual situation, for example, by adjusting the EC / MCU setting or the value of the capacitor C1 in the delay circuit 50. Second, +V3P3A_EC can be zero or exist in the shutdown state, and needs to exist in other states, such as hibernation and startup. Third, in actual application, whether the fourth MOS tube Q4, the fifth MOS tube Q5, the sixth MOS tube Q6, and the seventh MOS tube Q7 all need to be turned on can be determined according to the actual source of the POP sound. If the POP sound only comes from the GND fluctuations caused by the switching of the RING2 / SLEEVE, only the sixth MOS tube Q6 and the seventh MOS tube Q7 are needed.

[0044] In the embodiment, the circuit designs of the first control circuit 20, the second control circuit 30, and the delay circuit 50 are relatively simple, the development and manufacturing costs are low, and the application effect is good. Precise control can be achieved, mainly because the MIC bias level MIC_VREF of the codec 10 meets the characteristics that the MIC_VREF high level is immediately output when the operations such as startup with earphone recognition, earphone insertion, earphone recognition after driver loading, and earphone recognition when waking up are performed, so that the earphone can be precisely positioned when it needs to work normally, and the earphone can be completely muted before that. Taking the MIC_VREF as a reference control point, the POP sound can be effectively eliminated, and the control time length can be better grasped, so that adverse effects such as long-time silence are avoided.

[0045] Please refer to Figure 8 wherein t is the set delay 1s, which can be adjusted as needed. Within 1s after the MIC_VREF is output without the scheme of the embodiment of the utility model (without 2 / 3 / 4 / 5 in the timing diagram), the earphone audio signal HPR / HPL itself fluctuates or the SLEEVE / RING2 fluctuation is introduced into the HPR / HPL, so that the POP sound occurs. When the scheme of the embodiment of the utility model is controlled, the HPR / HPL / SLEEVE / RING2 are all controlled to maintain 0V, and there is no POP.

[0046] It should be understood that modifications or variations can be made to the above described embodiments by those of ordinary skill in the art, and that all such modifications and variations are intended to be within the scope of the present application as defined by the following claims.

Claims

1. A headphone circuit for eliminating POP sounds, characterized by: The audio codec, the first control circuit, the second control circuit, and the master control circuit or the delay circuit; the first control circuit is connected with the audio codec, the audio codec and the second control circuit are both connected to the earphone jack; the first control circuit and the second control circuit are both connected with the master control circuit or the delay circuit; The audio codec is used for outputting a first level signal to the first control circuit according to the state of the earphone jack, the first control circuit is used for outputting a second level signal to the master control circuit or the delay circuit according to the first level signal, the master control circuit or the delay circuit is used for controlling the delay according to the second level signal to keep the audio signal in a mute state and output a third level signal to the second control circuit, and the second control circuit is used for controlling the earphone jack to be opened to output the audio signal according to the third level signal.

2. The earphone circuit for eliminating a POP sound according to claim 1, characterized by: The first control circuit comprises a first resistor, a second resistor and a first MOS tube, one end of the first resistor is connected with the audio codec, and the other end of the first resistor is connected with the gate of the first MOS tube; the drain of the first MOS tube is connected with one end of the second resistor and the master control circuit or the delay circuit respectively, the other end of the second resistor is connected to the power supply end, and the source of the first MOS tube is grounded.

3. The earphone circuit for eliminating a POP sound according to claim 2, wherein: A first parasitic diode is connected between the drain and the source of the first MOS tube; the first MOS tube is an N-type MOS tube.

4. The earphone circuit for eliminating a POP sound according to claim 1, wherein: The delay circuit comprises a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a capacitor, a second MOS tube and a third MOS tube; one end of the third resistor is connected with the first control circuit, and the other end of the third resistor is connected with one end of the fourth resistor and the gate of the second MOS tube respectively; the drain of the second MOS tube is connected with one end of the fifth resistor, one end of the sixth resistor, one end of the capacitor and the gate of the third MOS tube respectively; the drain of the third MOS tube is connected with one end of the seventh resistor and the second control circuit respectively; the other end of the fifth resistor and the other end of the seventh resistor are both connected to the power supply end; the other end of the fourth resistor, the other end of the sixth resistor, the other end of the capacitor, the source of the second MOS tube and the source of the third MOS tube are all grounded.

5. The earphone circuit for eliminating a POP sound according to claim 4, wherein: A second parasitic diode is connected between the drain and the source of the second MOS tube and the third MOS tube respectively; the second MOS tube and the third MOS tube are both N-type MOS tubes.

6. The earphone circuit that eliminates POP sound according to claim 1, characterized in that: The second control circuit comprises an eighth resistor, a ninth resistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor; one end of the eighth resistor is connected with the master control circuit or the delay circuit, and the other end of the eighth resistor is connected with one end of the ninth resistor, the gate of the fourth MOS transistor, the gate of the fifth MOS transistor, the gate of the sixth MOS transistor and the gate of the seventh MOS transistor respectively; the drain of the fourth MOS transistor, the drain of the fifth MOS transistor, the drain of the sixth MOS transistor and the drain of the seventh MOS transistor are all connected with the earphone jack; the other end of the ninth resistor is grounded; the source of the fourth MOS transistor, the source of the fifth MOS transistor, the source of the sixth MOS transistor and the source of the seventh MOS transistor are all connected with the ground wire.

7. The earphone circuit for eliminating a POP sound according to claim 6, wherein: A third parasitic diode is connected between the drain and the source of the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor respectively; the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor are all N-type MOS transistors.

8. The earphone circuit for eliminating a POP sound according to any one of claims 1 to 3, 6 and 7, characterized by: The master control circuit comprises an EC unit or an MCU unit.

9. An earphone system, characterized by: The earphone circuit for eliminating the POP sound comprises the earphone circuit as claimed in any one of claims 1-8.

10. An earphone, characterized by: The earphone system comprises the earphone system as claimed in claim 9.

Images