Multi-level storage circuit based on core particles and electronic equipment
By designing a multi-level storage circuit, memory dies are connected to computing dies using different packaging methods, solving the problem of balancing capacity and bandwidth requirements for memory dies, and achieving the goal of meeting the diverse needs of computing dies without increasing package size.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-24
- Publication Date
- 2026-04-10
AI Technical Summary
In the current use of memory dies, it is difficult to simultaneously meet the capacity and bandwidth requirements of computing dies. When using memory dies with higher bandwidth, the capacity can only be reduced, and when using memory dies with higher capacity, the bandwidth can only be lower.
Design a chip-based multi-level memory circuit, including a packaging substrate and computing dies, as well as multiple sets of memory dies. The memory dies adopt different packaging methods, such as 2D, 2.5D, 3D and independent packaging, and are connected to the computing dies through an interposer or printed circuit board to meet different needs.
It achieves the balance between the capacity and bandwidth requirements of the computing die without increasing the package size, thus meeting the needs of different application scenarios.
Smart Images
Figure CN224111564U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of electronics, and more particularly, to a multi-level storage circuit based on core particles and an electronic device. BACKGROUND
[0002] The memory die is a temporary data storage medium for assisting the operation of the computing die, and plays a crucial role in ensuring the stable and efficient operation of the computing die.
[0003] At present, in the use process of the memory die, when a memory die with a larger bandwidth is used, only the capacity of the memory die can be reduced, and when a memory die with a larger capacity is used, only a memory die with a lower bandwidth can be used. CONTENT OF THE UTILITY MODEL
[0004] The present application provides a multi-level storage circuit based on core particles and an electronic device, which can balance the capacity demand and bandwidth demand of the computing die.
[0005] In a first aspect, a multi-level storage circuit based on core particles is provided, comprising: a packaging substrate and a computing die, and a plurality of groups of memory dies; the computing die is mounted on the packaging substrate; the plurality of groups of memory dies are respectively connected with the computing die, and the plurality of groups of memory dies are respectively packaged by different packaging methods.
[0006] In the present application, the multi-level storage circuit based on core particles comprises a packaging substrate and a computing die, and a plurality of groups of memory dies, the computing die is mounted on the packaging substrate, the plurality of groups of memory dies are respectively connected with the computing die, and the plurality of groups of memory dies are respectively packaged by different packaging methods. In the manufacturing process of the multi-level storage circuit based on core particles, the corresponding memory dies can be set in the circuit according to the actual demand, so as to balance the capacity demand and bandwidth demand of the computing die.
[0007] Optionally, the circuit further comprises an interposer; the interposer is mounted on the packaging substrate, the computing die is indirectly mounted on the packaging substrate through the interposer, and part of the plurality of groups of memory dies are connected with the computing die through the interposer.
[0008] Optionally, the plurality of groups of memory dies comprise a first group of memory dies, the memory dies in the first group of memory dies are packaged by a 2.5D packaging method; the memory dies in the first group of memory dies are mounted on the interposer, and the memory dies in the first group of memory dies are connected with the computing die through the interposer.
[0009] Optionally, the plurality of memory die groups comprises a second memory die group, memory dies in the second memory die group are packaged in a 2D package; the memory dies in the second memory die group are mounted on the package substrate, and the memory dies in the second memory die group are connected to the computing die through the interposer and the package substrate.
[0010] Optionally, the circuit further comprises a printed circuit board, and the package substrate is mounted on the printed circuit board; the plurality of memory die groups comprises a third memory die group, memory dies in the third memory die group are packaged in a separate package; the memory dies in the third memory die group are mounted on the printed circuit board, and the memory dies in the third memory die group are connected to the computing die through the printed circuit board, the package substrate and the interposer in sequence.
[0011] Optionally, the circuit further comprises a printed circuit board, and the package substrate is mounted on the printed circuit board.
[0012] Optionally, the plurality of memory die groups comprises a third memory die group, memory dies in the third memory die group are packaged in a separate package; the memory dies in the third memory die group are mounted on the printed circuit board, and the memory dies in the third memory die group are connected to the computing die through the package substrate and the printed circuit board.
[0013] Optionally, the plurality of memory die groups comprises a fourth memory die group; memory dies in the fourth memory die group are packaged in a 3D package, and the memory dies in the fourth memory die group are stacked above the computing die.
[0014] Optionally, the memory dies in the fourth memory die group are connected to the computing die through hybrid bonding.
[0015] In a second aspect, an electronic device is provided, comprising the core particle-based multi-level memory circuit according to the first aspect. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 A composition diagram of a core particle-based multi-level memory circuit is shown;
[0017] Figure 2 A composition diagram of a core particle-based multi-level memory circuit is shown Figure 1 A top view of the circuit is shown;
[0018] Figure 3 A composition diagram of another core particle-based multi-level memory circuit is shown;
[0019] Figure 4 A composition diagram of another core particle-based multi-level memory circuit is shownFigure 3 a top view of the circuit shown;
[0020] Figure 5 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown;
[0021] Figure 6 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown; Figure 5 a top view of the circuit shown;
[0022] Figure 7 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown;
[0023] Figure 8 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown; Figure 7 a top view of the circuit shown;
[0024] Figure 9 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown;
[0025] Figure 10 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown; Figure 9 a top view of the circuit shown;
[0026] Figure 11 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown;
[0027] Figure 12 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown; Figure 11 a top view of the circuit shown;
[0028] Figure 13 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown;
[0029] Figure 14 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown; Figure 13 a top view of the circuit shown;
[0030] Figure 15 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown;
[0031] Figure 16 Another composition schematic diagram of the multi-level storage circuit based on the core particle provided by the embodiment of the application is shown; Figure 15 a top view of the circuit shown. DETAILED DESCRIPTION
[0032] The technical solutions in the present application will be clearly and completely described below with reference to the drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " represents the meaning of or, for example, A / B can represent A or B: "and / or" in the text only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.
[0033] Hereinafter, the terms "first" and "second" are only used for description purposes, and cannot be understood as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more features.
[0034] A die, also known as a chiplet, refers to a chip including one complete functional unit or a group of related functional units, and an unpackaged chip. A die also refers to a bare die. A complete functional unit including a memory and an unpackaged memory chip is referred to as a memory die, also known as a memory bare die. The memory bare die is used to support the operation of a computing die (also referred to as a logic computing die) such as a Graphic Processing Unit (GPU), a Central Processing Unit (CPU) and a System on Chip (SoC).
[0035] For a computing die, the higher the capacity and bandwidth of the memory die provided for the computing die, the better the performance of the computing die. However, when a memory die with a larger bandwidth is used, the memory die needs to be as close as possible to the computing die and packaged together with the computing die. Limited by the package size, the capacity of the memory die can only be reduced at this time. Conversely, when a memory die with a larger capacity is needed, the distance between the memory die and the computing die needs to be increased accordingly. At this time, a memory die with a lower bandwidth can only be used. Therefore, it is difficult to balance the capacity requirement and bandwidth requirement of the computing die.
[0036] To solve the above technical problems, the present application provides a multi-level memory circuit based on a chiplet, which includes a packaging substrate and a computing die, and a plurality of groups of memory dies; the computing die is mounted on the packaging substrate; the plurality of groups of memory dies are respectively connected with the computing die, and the plurality of groups of memory dies are respectively packaged by different packaging methods, and each group of memory dies includes one or more memory dies.
[0037] The packaging methods of the plurality of memory dies can include at least two of 2D packaging, 2.5D packaging, 3D packaging, and independent packaging. The 2D packaging, also referred to as traditional packaging or standard packaging, refers to packaging of a bare chip on a horizontal surface of a package substrate. The 2.5D packaging, also referred to as advance packaging, is a technology between 2D packaging and 3D packaging, in which the bare chips are connected through an interposer. The 3D packaging refers to packaging of two or more bare chips stacked in a vertical direction in one package, in which the bare chips are stacked together and connected through a through-silicon via. The independent packaging refers to packaging of a bare chip alone.
[0038] Optionally, the circuit further includes an interposer, and the interposer is mounted on the package substrate, and the computing die is indirectly mounted on the package substrate through the interposer. Some of the plurality of memory dies are connected to the computing die through the interposer.
[0039] In an embodiment, the plurality of memory dies includes a second group of memory dies, and the memory dies (hereinafter referred to as second memory dies) in the second group of memory dies are packaged in a 2D packaging manner. One or more second memory dies included in the second group of memory dies are mounted on the package substrate, and the second memory dies are connected to the computing die through the interposer and the package substrate. The plurality of memory dies further includes a fourth group of memory dies, and one or more memory dies (hereinafter referred to as fourth memory dies) included in the fourth group of memory dies are packaged in a 3D packaging manner, and the fourth memory dies are stacked on the computing die.
[0040] Referring to Figure 1 and Figure 2 , Figure 1 a schematic diagram of a multi-level memory circuit based on a core particle is shown, Figure 2 a top view of the circuit shown in Figure 1 is shown. The circuit includes a package substrate 11, an interposer 12, and a computing die 13, a second group of memory dies composed of at least one second memory die 22, and a fourth group of memory dies composed of at least one fourth memory die 24.
[0041] As Figure 1 and Figure 2As shown, the interposer 12 is mounted on the package substrate 11, and the computing die 13 is mounted on the interposer 12. The second memory dies 22 can be single Dynamic Random-Access Memory (DRAM), and each of the second memory dies 22 is directly mounted on the package substrate 11. The second memory dies 22 are connected to the computing die 13 through bumps at the bottom of the second memory dies 22, wirings in the package substrate 11, wirings in the interposer 12, and bumps at the bottom of the computing die 13. Since the second memory dies 22 are mounted on the package substrate 11 and connected to the computing die 13 through the interposer 12, each of the second memory dies 22 can be packaged by 2D packaging when the circuit is packaged.
[0042] The fourth memory dies 24 can be Three-Dimensional Dynamic Random-Access Memory (3D DRAM), and each of the fourth memory dies 24 includes a plurality of memory dies 241 stacked on each other, and each of the memory dies 241 includes a certain number of storage units for storing data. The plurality of memory dies 241 are stacked on the computing die 13 in sequence, and each of the memory dies 241 is connected to the computing die 13 through a through silicon via and a bump. Since the fourth memory dies 24 are mounted on the package substrate 11, the fourth memory dies 24 and the computing die 13 can be packaged by 3D packaging when the circuit is packaged.
[0043] Alternatively, the fourth memory dies 24 can also be High Bandwidth Memory (HBM), and each of the fourth memory dies 24 includes a plurality of memory dies and a base die. The memory dies are also referred to as Dynamic Random Access Memory (DRAM) dies, and the base die is also referred to as a logic die. The plurality of memory dies are stacked on the base die in sequence, and the base die is stacked on the computing die 13. The memory dies and the base die are connected to the computing die 13 through a through silicon via.
[0044] Alternatively, when the circuit includes an interposer, the plurality of groups of memory dies include a first group of memory dies, and memory dies (hereinafter referred to as first memory dies) in the first group of memory dies are packaged by 2.5D packaging. The memory dies in the first group of memory dies are mounted on the interposer, and the memory dies in the first group of memory dies are connected to the computing die through the interposer.
[0045] Referring to Figure 3 and Figure 4 , Figure 3Another composition diagram of the multi-level memory circuit based on the core particle is shown, Figure 4 A top view of the circuit is shown. The circuit includes a packaging substrate 11, an interposer 12, and a computing die 13, a first memory die group composed of at least one first memory die 21, a second memory die group composed of at least one second memory die 22, and a fourth memory die group composed of at least one fourth memory die 24. Figure 3 A top view of the circuit is shown. The circuit includes a packaging substrate 11, an interposer 12, and a computing die 13, a first memory die group composed of at least one first memory die 21, a second memory die group composed of at least one second memory die 22, and a fourth memory die group composed of at least one fourth memory die 24.
[0046] As shown in Figure 3 and Figure 4 The first memory die 21 can be a high-bandwidth memory, including a plurality of memory dies 211 and a base die 212, the base die 212 being stacked on the interposer 12, and the plurality of memory dies 211 being stacked on the base die 212 in sequence. An interface module is integrated in the base die 212, and the interface module is composed of one or more physical layer (Physical, PHY) modules. A corresponding interface module is integrated in each of the computing dies 13, and the interface module matches the interface module in the base die 212. The interface module integrated in the base die 212 is connected to the corresponding interface module in the computing die 13 through bumps on the bottom of the base die 212, wiring in the interposer 12, and bumps on the bottom of the computing die 13, to realize the communication connection between the first memory die 21 and the computing die 13. Since the first memory die 21 is mounted on the packaging substrate 11 and connected to the computing die 13 through the interposer 12, when the circuit is packaged, the first memory die 21 can be packaged by using 2.5D packaging.
[0047] Alternatively, the first memory die 21 can also be a 3D DRAM, including a plurality of memory dies stacked on the interposer 12 in sequence, each memory die including a certain number of storage units for storing data, and each memory die being connected to the computing die through a through-silicon via and a bump.
[0048] As shown in Figure 3 When the fourth memory die 24 is a high-bandwidth memory or a three-dimensional dynamic random access memory, the fourth memory die 24 can be connected to the computing die 13 by hybrid bonding, or the fourth memory die 24 can be connected to the computing die 13 by a through-silicon via.
[0049] Optionally, when the interposer is included in the circuit, a printed circuit board is further included in the circuit, and the package substrate is mounted on the printed circuit board. The plurality of memory die groups includes a third memory die group, and the memory die in the third memory die group (hereinafter referred to as a third memory die) is independently packaged in a package mode. The memory die in the third memory die group is mounted on the printed circuit board, and the memory die in the third memory die group is connected to the compute die in sequence through the printed circuit board, the package substrate, and the interposer.
[0050] Referring to Figure 5 and Figure 6 , Figure 5 shows a composition schematic diagram of another multi-level memory circuit based on a core particle provided by an embodiment of the present application, Figure 6 shows Figure 5 a top view of the circuit. The circuit includes a printed circuit board (PCB) 10, a package substrate 11, an interposer 12, and a compute die 13, a first memory die group composed of at least one first memory die 21, a second memory die group composed of at least one second memory die 22, a third memory die group composed of at least one third memory die 23, and a fourth memory die group composed of at least one fourth memory die 24.
[0051] As shown in Figure 5 and Figure 6 , the third memory die 23 can be a single DRAM or a dual in-line memory module (DIMM). The third memory die 23 is independently packaged as a memory chip 25 in a 2D package mode, and the memory chip 25 has a memory plug (not shown in the figure), also known as a gold finger. The printed circuit board 10 is provided with a memory slot 26 corresponding to the memory chip 25, and the memory chip 25 is connected to the printed circuit board 10 through the plug-in cooperation between the memory plug and the memory slot 26. The package substrate 11 is mounted on the printed circuit board 10, and for each third memory die 23, a corresponding interface module is integrated in the compute die 13, and the interface module is connected to the memory slot 26 corresponding to the third memory die 23. The memory slot 26 corresponding to the third memory die 23 is connected to a corresponding interface module in the compute die 13 through the bump on the bottom of the third memory die 23, the wiring in the printed circuit board 10, the bump and the wiring on the bottom of the package substrate 11, and the wiring in the interposer 12 and the bump on the bottom of the compute die 13, to realize the communication connection between the third memory die 23 and the compute die 13. Since the third memory die 23 is directly mounted on the package substrate 11, when the circuit is packaged, the third memory die 23 can be independently packaged in an independent packaging mode.
[0052] AsFigure 5 and Figure 6 As shown in FIG. 6, the fourth memory die 24 can be a single DRAM, the fourth memory die 24 is connected with the computing die 13 through a through silicon via, or the fourth memory die 24 is connected with the computing die 13 through a hybrid bonding.
[0053] In an embodiment, the circuit can include the printed circuit board 10, the packaging substrate 11, the computing die 13, the second memory die group, the third memory die group, and the fourth memory die group.
[0054] Referring to Figure 7 and Figure 8 , Figure 7 FIG. 7 shows a composition schematic diagram of another multi-level memory circuit based on a core particle provided by an embodiment of the present application, Figure 8 FIG. 7 shows a composition schematic diagram of another multi-level memory circuit based on a core particle provided by an embodiment of the present application, Figure 7 FIG. 7 shows a composition schematic diagram of another multi-level memory circuit based on a core particle provided by an embodiment of the present application,
[0055] In the manufacturing process of the circuit, the second memory die 22 can be packaged by 2D packaging, the fourth memory die 241 can be packaged by 3D packaging, and the third memory die 23 can be independently packaged by independent packaging.
[0056] In an embodiment, the multi-level memory circuit based on a core particle can include the printed circuit board 10, the packaging substrate 11, the interposer 12, the computing die 13, the first memory die group, and the fourth memory die group. Referring to Figure 9 and Figure 10 , Figure 9 FIG. 7 shows a composition schematic diagram of another multi-level memory circuit based on a core particle provided by an embodiment of the present application, Figure 10 FIG. 7 shows a composition schematic diagram of another multi-level memory circuit based on a core particle provided by an embodiment of the present application, Figure 9The top view of the circuit shown. The package substrate 11 is mounted on the printed circuit board 10, the interposer 12 is mounted on the package substrate 11, the computing die 13 is mounted on the interposer 12, the first memory die 21 is high bandwidth memory, and the fourth memory die 24 is a single DRAM. The understanding of the first memory die and the fourth memory die can refer to the above examples, and this embodiment will not be repeated here. In the manufacturing process of the circuit, the first memory die 21 can be packaged by using 2.5D packaging, and the fourth memory die 24 can be packaged by using 3D packaging.
[0057] In an embodiment, the core particle-based multi-level storage circuit can include a printed circuit board 10, a package substrate 11, an interposer 12, a computing die 13, a first memory die group, a second memory die group, and a third memory die group.
[0058] Referring to Figure 11 and Figure 12 , Figure 11 shows another core particle-based multi-level storage circuit provided by an embodiment of the application, Figure 12 shows Figure 11 The top view of the circuit shown. The package substrate 11 is mounted on the printed circuit board 10, the interposer 12 is mounted on the package substrate 11, the computing die 13 is mounted on the interposer 12, a plurality of first memory dies 21 are mounted on the interposer 12, the first memory die 21 is a single DRAM, and each first memory die 21 is connected to the computing die 13 through the interposer 12. A plurality of second memory dies 22 in the second memory die group are mounted on the package substrate 11, the second memory die 22 is a single DRAM, and the second memory die 22 is connected to the computing die 13 through the package substrate 11 and the interposer 12. The third memory die 23 is independently packaged as a memory chip 25 in a 2D packaging manner, and the memory chip 25 is connected to the printed circuit board 10 through the plug-in cooperation between the memory plug and the memory slot 26, to realize the connection between the third memory die 23 and the computing die 13. The understanding of the first memory die, the second memory die, and the third memory die can refer to the above examples, and this embodiment will not be repeated here.
[0059] Referring to Figure 13 and Figure 14 , Figure 13 shows another core particle-based multi-level storage circuit provided by an embodiment of the application, Figure 14 shows Figure 13 The top view of the circuit shown. The first memory die 21 is high bandwidth memory ， The second memory die 22 is a single DRAM, and the third memory die 23 is an independently packaged single DRAM. The understanding of the first memory die, the second memory die, and the third memory die can refer to the above examples, and this embodiment will not be repeated here.
[0060] In one embodiment, the circuit may include: a printed circuit board 10, a package substrate 11, a computing die 13, a second memory die set, and a third memory die set. See also... Figure 15 and Figure 16 , Figure 15 This illustration shows a schematic diagram of another chip-based multilevel memory circuit provided in an embodiment of this application. Figure 16 It shows Figure 15 The circuit shown is a top view. A package substrate 11 is mounted on a printed circuit board 10. A computing die 13 is mounted on the package substrate 11. Multiple second memory dies 22 from the second memory die group are mounted on the package substrate 11, and the second memory dies 22 are connected to the computing die 13 via the package substrate 11. Multiple third memory dies 23 from the third memory die group are mounted on the printed circuit board 10, and the third memory dies 23 are connected to the computing die 13 via the printed circuit board 10 and the package substrate 11. The understanding of the second and third memory dies can be found in the examples above; this implementation will not be elaborated upon here.
[0061] like Figures 1-12 As shown, the circuit may include at least two of a first memory die group, a second memory die group, a third memory die group, and a fourth memory die group, with each memory die group including one or more memory dies.
[0062] Typically, the packaging method of a memory die is related to its bandwidth. The bandwidth of a memory die increases progressively from discrete packaging to 2D packaging, 2.5D packaging, and 3D packaging. When a circuit includes multiple sets of memory dies with different packaging methods, some dies can be selected as low-capacity, high-bandwidth dies, while others can be selected as high-capacity, low-bandwidth dies. This ensures that the bandwidth requirements of the computing die are met while also guaranteeing the capacity requirements, thus balancing both capacity and bandwidth needs.
[0063] For example, when the circuit includes a first memory die, a second memory die, a third memory die, and a fourth memory die, the bandwidth of each group of memory dies can be gradually increased and the capacity gradually decreased (i.e., the number of memory dies gradually decreases) by ordering the third memory die, the second memory die, the first memory die, and the fourth memory die. Specifically, the fourth memory die has the lowest capacity and the highest bandwidth, while the third memory die has the largest capacity and the lowest bandwidth. This allows for configuring a small number of memory dies with higher bandwidth to meet the bandwidth requirements of the computing dies, and configuring a large number of memory dies with lower bandwidth to meet the capacity requirements of the computing dies.
[0064] Moreover, when the circuit includes multiple groups of memory dies in different packaging manners, different application requirements of the computing die can be met. For example, when the circuit includes the first memory die, the second memory die, the third memory die, and the fourth memory die, the fourth memory die can meet the application requirement of high bandwidth, the third memory die can meet the application requirement of large capacity, the first memory die can be compatible with the application requirement of large capacity and high bandwidth, and the second memory die can be compatible with the application requirement of large capacity and low bandwidth.
[0065] In the embodiments of the present application, the multi-level memory circuit based on the core particle includes a packaging substrate and a computing die, and multiple groups of memory dies. The computing die is mounted on the packaging substrate, and the multiple groups of memory dies are connected with the computing die respectively. The multiple groups of memory dies are packaged by using different packaging manners respectively. In the manufacturing process of the circuit, the corresponding memory dies can be set in the circuit according to actual requirements, so as to take into account the capacity requirement and the bandwidth requirement of the computing die.
[0066] The embodiments of the present application also provide an electronic device, which includes Figures 1-12 The multi-level memory circuit based on the core particle shown in the embodiments of the present application.
[0067] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A multi-level storage circuit based on a core particle, characterized by, Comprising: a package substrate and a compute die, and a plurality of groups of memory dies and an interposer; the interposer is mounted on the package substrate, the compute die is indirectly mounted on the package substrate through the interposer; the plurality of groups of memory dies comprises a first group of memory dies, the first group of memory dies adopts a 2.5D packaging manner; the memory dies in the first group of memory dies are mounted on the interposer, the memory dies in the first group of memory dies are connected with the compute die through the interposer; the plurality of groups of memory dies comprises a fourth group of memory dies; the memory dies in the fourth group of memory dies adopt a 3D packaging manner, the memory dies in the fourth group of memory dies are stacked above the compute die.
2. The core particle based multi-tier storage circuit of claim 1, wherein, the plurality of groups of memory dies comprises a second group of memory dies, the second group of memory dies adopts a 2D packaging manner; the memory dies in the second group of memory dies are mounted on the package substrate, the memory dies in the second group of memory dies are connected with the compute die through the interposer and the package substrate.
3. The core particle based multi-tier storage circuit of claim 1, wherein, further comprising a printed circuit board, the package substrate is mounted on the printed circuit board; the plurality of groups of memory dies comprises a third group of memory dies, the memory dies in the third group of memory dies adopt a separate packaging manner; the memory dies in the third group of memory dies are mounted on the printed circuit board, the memory dies in the third group of memory dies are connected with the compute die through the printed circuit board, the package substrate and the interposer in sequence.
4. The core particle based multi-tier storage circuit of claim 1, wherein, further comprising a printed circuit board, the package substrate is mounted on the printed circuit board.
5. The core particle based multi-tier storage circuit of claim 4, wherein, the plurality of groups of memory dies comprises a third group of memory dies, the memory dies in the third group of memory dies adopt a separate packaging manner; the memory dies in the third group of memory dies are mounted on the printed circuit board, the memory dies in the third group of memory dies are connected with the compute die through the package substrate and the printed circuit board.
6. The core particle based multi-tier storage circuit of claim 1, wherein, the memory dies in the fourth group of memory dies are connected with the compute die through a hybrid bonding manner.
7. An electronic device, comprising: A core particle-based multi-level memory circuit as claimed in any one of claims 1-6.