Trench oxide layer structure and shield gate trench type semiconductor
By setting a trench oxide layer structure with step differences in the shielded gate trench semiconductor, the gate leakage and short circuit problems caused by insufficient inter-electrode oxide thickness are solved, thereby improving the reliability of the device and reducing capacitance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 捷捷微电(南通)科技有限公司
- Filing Date
- 2025-04-21
- Publication Date
- 2026-04-10
AI Technical Summary
In the prior art, when conventional shielded gate trench power metal-oxide-semiconductor transistors react with the oxide and polysilicon field plate, the thickness of the inter-electrode oxide is much smaller than the thickness of the shielding oxide layer, which leads to the risk of gate leakage and short-circuit leakage between the gate and the source polysilicon.
By setting a first polysilicon layer, a second polysilicon layer, and an oxide layer in the trench, including a first oxide layer, a second oxide layer, and an isolation layer, a trench oxide layer structure with a step difference is formed, the morphology of the polysilicon layer is adjusted, the gate polysilicon is prevented from entering the void, and the thickness of the inter-electrode oxide is increased.
It effectively reduces the risk of gate leakage and short-circuit leakage between the gate and source polysilicon, improves gate reliability, and reduces gate input capacitance.
Smart Images
Figure CN224111565U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a semiconductor technical field especially, it is a kind of trench oxide layer structure and shielded gate trench type semiconductor. BACKGROUND
[0002] The switching tube of semiconductor power device constitutes the core of modern power converter, and the commonly used power device is formed by metal, oxide and semiconductor material processing. The commonly used shielded gate trench type power metal oxide semiconductor transistor is usually controlled by the additional bias of gate polysilicon to control the switching of the device. When the gate is positively biased, the gate electric field forms a reverse-type layer conductive channel on the surface of the oxide and semiconductor, so that the device is in conduction. Conversely, when the gate is connected to zero potential or negative potential, the device is in off state.
[0003] In the conventional preparation process, when the oxygen element reacts with the polysilicon field plate to form inter-poly oxide (IPO), the thickness of the inter-poly oxide after the oxidation of polysilicon is much smaller than the thickness of the shielding oxide layer, which causes the inter-poly oxide to be unable to fill the voids of the sidewall, forming a gate polysilicon sharp corner. This sharp corner of gate polysilicon can cause the isolation layer between the gate polysilicon and the polysilicon field plate to thin, increase the gate leakage, and even cause the risk of short circuit leakage between the gate and the source polysilicon.
[0004] Therefore, there is an urgent need for a semiconductor solution that can improve the risk of gate leakage and improve the reliability of the gate. INVENTION CONTENTS
[0005] The utility model aims at providing a kind of trench oxide layer structure and shielded gate trench type semiconductor, which can overcome the technical problems caused by the fact that the thickness of inter-poly oxide is much smaller than the thickness of shielding oxide layer in the prior art, such as the risk of gate leakage and even short circuit leakage between the gate and the source polysilicon, improve the risk of gate leakage and improve the reliability of the gate.
[0006] In the first aspect, the present application provides a kind of trench oxide layer structure, which includes:
[0007] An epitaxial layer, wherein the epitaxial layer is provided with a trench;
[0008] A first polysilicon layer, a second polysilicon layer and an oxide layer filled in the trench; the oxide layer includes a first oxide layer, a second oxide layer and an isolation layer; the first polysilicon layer is located below the second polysilicon layer; the second oxide layer is arranged around the second polysilicon layer; the isolation layer is arranged between the first polysilicon layer and the second polysilicon layer; the first oxide layer is arranged around the first polysilicon layer and part of the isolation layer;
[0009] The surface of the first oxide layer is higher than the surface of the first polysilicon layer, so that a step difference exists between the first oxide layer and the first polysilicon layer.
[0010] Optionally, the isolation layer comprises a stepped structure; a contact surface between the stepped structure and the first polysilicon layer is a first contact surface; a contact surface between the stepped structure and the second polysilicon layer is a second contact surface; a projection area of the first contact surface on a plane where the epitaxial layer is located is smaller than a projection area of the second contact surface on the plane where the epitaxial layer is located.
[0011] Optionally, the stepped structure comprises at least two layers, and the two layers are a first layer and a second layer in sequence from bottom to top along a direction away from the surface of the first polysilicon layer.
[0012] The width of the second layer is greater than the width of the first layer.
[0013] Optionally, a ratio between the thickness of the first layer and the width of the first layer is greater than or equal to 1.
[0014] Optionally, the thickness of the first layer is greater than or equal to 0.2 microns.
[0015] Optionally, the material for manufacturing the first oxide layer is a combination of any one or more of silicon oxide and silicon nitride.
[0016] Optionally, the material for manufacturing the first oxide layer is silicon dioxide.
[0017] Optionally, the width of the second polysilicon layer is greater than the width of the first polysilicon layer.
[0018] Optionally, a difference between the surface of the first polysilicon layer and the surface of the epitaxial layer is greater than or equal to 0.9 microns and less than or equal to 3 microns.
[0019] In a second aspect, the application further provides a shield gate trench type semiconductor comprising the trench oxide layer structure according to any one of the first aspect.
[0020] The trench oxide layer structure and the shield gate trench type semiconductor provided by the application have the following beneficial effects:
[0021] The trench oxide layer structure in the application comprises: an epitaxial layer provided with a trench; the trench is filled with a first polysilicon layer, a second polysilicon layer and an oxide layer, wherein the oxide layer comprises a first oxide layer, a second oxide layer and a separation layer; the separation layer is arranged between the first polysilicon layer and the second polysilicon layer, so that a step difference exists between the first oxide layer and the first polysilicon layer; the first oxide layer is arranged around the first polysilicon layer and part of the separation layer; and the surface of the first oxide layer is higher than the surface of the first polysilicon layer. Based on this, the step difference between the first oxide layer and the first polysilicon layer under the trench oxide layer structure is formed by the separation layer in the application, the morphology of the first polysilicon layer is adjusted, and thus the technical problem of the risk of gate leakage or even short-circuit leakage between the gate and the source polysilicon caused by the fact that the thickness of the inter-electrode oxide is much smaller than the thickness of the shielding oxide in the prior art is overcome, the risk of gate leakage is improved, and the reliability of the gate is improved. BRIEF DESCRIPTION OF DRAWINGS
[0022] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings described below are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0023] Figure 1 The present application is a conventional shielding gate trench type power metal oxide semiconductor transistor structure in the prior art;
[0024] Figure 2 The present application is a structure schematic diagram of a trench oxide layer structure provided in an embodiment of the present application;
[0025] Figure 3 The present application is a structure schematic diagram of a trench oxide layer structure provided in an embodiment of the present application;
[0026] Figure 4 The present application is a structure schematic diagram of a trench oxide layer structure provided in an embodiment of the present application;
[0027] Figure 5 The present application is an exemplary preparation schematic diagram of a trench oxide layer structure provided in an embodiment of the present application;
[0028] Figure 6 The present application is an exemplary preparation schematic diagram of a shielding gate trench type semiconductor provided in an embodiment of the present application;
[0029] Figure 7 The present application is an exemplary preparation schematic diagram of a shielding gate trench type semiconductor provided in an embodiment of the present application;
[0030] Figure 8 An exemplary preparation schematic diagram four of the shielding gate trench type semiconductor provided by the embodiment of the present application is provided;
[0031] Figure 9 An exemplary preparation schematic diagram five of the shielding gate trench type semiconductor provided by the embodiment of the present application is provided;
[0032] Figure 10 An exemplary preparation schematic diagram six of the shielding gate trench type semiconductor provided by the embodiment of the present application is provided;
[0033] Figure 11 An exemplary preparation schematic diagram seven of the shielding gate trench type semiconductor provided by the embodiment of the present application is provided;
[0034] Figure 12 A structure schematic diagram of the shielding gate trench type semiconductor provided by the embodiment of the present application is provided.
[0035] Icon: 10-trench oxide layer structure; 20-shielding gate trench type semiconductor; 101-epitaxial layer; 102-trench; 103-first polysilicon layer; 104-second polysilicon layer; 105-first oxide layer; 106-second oxide layer; 107-isolation layer; 107A-first contact surface; 107B-second contact surface; 108-barrier layer; 109-source contact area; 110-body area; 111-source metal; 112-interlayer dielectric layer; 113-source level contact hole; 201-first layer; 202-second layer. DETAILED DESCRIPTION
[0036] In order to make the purpose, technical scheme and advantages of the embodiment of the present application more clear, the technical scheme in the embodiment of the present application will be described clearly and completely below in combination with the drawings in the embodiment of the present application. Obviously, the described embodiment is a part of the embodiments of the present application, rather than all the embodiments of the present application. The components of the embodiment of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0037] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0038] It should be noted that: similar labels and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.
[0039] In the description of the utility model, it needs to be explained that the orientation or position relation indicated by the terms "center", "upper", "lower", "inner", "outer" and the like is based on the orientation or position relation shown in the drawings, or is the orientation or position relation when the utility model product is usually placed, and is only for the convenience of describing the utility model and simplifying the description, and therefore cannot be understood as limiting the utility model. In addition, the terms "first", "second" and the like are only used for differentiation in description, and cannot be understood as indicating or implying relative importance.
[0040] In addition, in the description of the utility model, it needs to be explained that, unless otherwise explicitly specified and limited, the term "arrangement" should be understood broadly, for example, it can be fixedly connected, or can be detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the communication inside two elements. For ordinary skilled persons in the art, the specific meaning of the above-mentioned terms in the utility model can be understood according to the specific circumstances.
[0041] Some embodiments of the utility model will be described in detail below with reference to the drawings. In the case of no conflict, the following examples and features in the examples can be combined with each other.
[0042] Please refer to Figure 1 , Figure 1 A conventional shielding gate trench type power metal oxide semiconductor transistor (MOSFET) structure in the prior art is shown, as described in the background art, during preparation, an inter-electrode oxide IPO, i.e. an isolation layer 107, is formed by oxidation, since the IPO thickness after oxidation of polysilicon is much smaller than the thickness of the shielding oxide layer, i.e. the first oxide layer 105, the inter-electrode oxide IPO cannot fill the hollow of the trench sidewall, resulting in that when the gate polysilicon is deposited subsequently, the gate polysilicon will enter the hollow, forming a gate polysilicon sharp corner at the gate polysilicon, as indicated by the dashed box in the figure. Figure 1
[0043] Based on this, the application provides a trench oxide layer structure and a shielding gate trench type semiconductor, which can overcome the technical problem of the risk of gate leakage or even short circuit leakage of the gate and source polysilicon caused by the fact that the inter-electrode oxide thickness is much smaller than the shielding oxide layer thickness in the prior art.
[0044] Please refer to Figure 2 , Figure 2 A structure diagram of the trench oxide layer structure in the application is shown, the application provides a trench oxide layer structure 10, which comprises:
[0045] An epitaxial layer 101; wherein the epitaxial layer 101 is provided with a trench 102.
[0046] A first polysilicon layer 103, a second polysilicon layer 104 and an oxide layer filled in the trench 102; the oxide layer comprises a first oxide layer 105, a second oxide layer 106 and an isolation layer 107; the first polysilicon layer 103 is located below the second polysilicon layer 104; the second oxide layer 106 is provided around the second polysilicon layer 104; the isolation layer 107 is provided between the first polysilicon layer 103 and the second polysilicon layer 104, so that there is a step difference between the first oxide layer 105 and the first polysilicon layer 103; the first oxide layer 105 is provided around the first polysilicon layer 103 and part of the isolation layer 107.
[0047] Wherein, the surface of the first oxide layer 105 is higher than the surface of the first polysilicon layer 103, so that there is a step difference between the first oxide layer 105 and the first polysilicon layer 103.
[0048] It should be noted that in the embodiment, the first oxide layer 105 comprises a shielding oxide layer, the second oxide layer 106 comprises a gate oxide layer, and the first polysilicon layer 103 comprises a separate gate field plate; the second polysilicon layer 104 comprises a gate polysilicon layer.
[0049] In the embodiment, the width of the second polysilicon layer 104 is greater than the width of the first polysilicon layer 103.
[0050] In one possible implementation, the difference between the surface of the first polysilicon layer 103 and the surface of the epitaxial layer 101 is greater than or equal to 0.9 microns and less than or equal to 3 microns.
[0051] In the application, the trench oxide layer structure is provided with an isolation layer between the first polysilicon layer and the second polysilicon layer, so that there is a step difference between the first oxide layer and the first polysilicon layer, and then the gate polysilicon topography is changed to overcome the technical problem of gate leakage or even the risk of gate and source polysilicon short circuit leakage caused by the fact that the inter-electrode oxide thickness is much smaller than the shielding oxide thickness in the prior art.
[0052] In one possible implementation, please refer to Figure 2 , Figure 3 , Figure 3 Another schematic diagram of the trench oxide layer structure in the application is shown, and the isolation layer 107 in the application comprises a stepped structure.
[0053] The contact surface between the stepped structure and the first polysilicon layer 103 is the first contact surface 107A, and the contact surface between the stepped structure and the second polysilicon layer 104 is the second contact surface 107B. The projection area of the first contact surface 107A on the plane where the epitaxial layer 101 is located is smaller than the projection area of the second contact surface 107B on the plane where the epitaxial layer 101 is located.
[0054] It should be noted that the embodiment is not limited to the specific implementation structure of the isolation layer 107, as long as there is a step difference between the first oxide layer 105 and the first polysilicon layer 103.
[0055] Please refer to Figure 3 on the basis of Figure 4 , Figure 4 Another schematic diagram of the trench oxide layer structure in the present application is shown. In one possible implementation, the stepped structure can be a reverse stepped structure, which includes at least two layers, the first layer 201 and the second layer 202, from bottom to top along the direction away from the surface of the first polysilicon layer 103.
[0056] The width of the second layer 202 is greater than the width of the first layer 201.
[0057] In one possible implementation, in order to further optimize the gate polysilicon topography and improve the gate leakage and gate high-temperature reliability, in the embodiment, the ratio of the thickness of the first layer 201 to the width of the first layer 201 is greater than or equal to 1.
[0058] In the embodiment, the ratio of the height difference of the shielding oxide layer to the separation gate field plate to the width of the separation gate field plate surface is not less than 1:1. Based on the TEOS hole filling characteristics, the holes on the sidewall of the trench can be filled, and the problem that the polysilicon will fill into the holes during the subsequent deposition of the gate polysilicon can be avoided.
[0059] In the embodiment, the thickness of the first layer 201 is greater than or equal to 0.2 microns.
[0060] In addition, the present application can further improve the risk of gate leakage and even gate and source polysilicon short-circuit leakage from the perspective of device preparation materials. For example, in the embodiment, the material for making the first oxide layer 105 is a combination of any one or more of silicon oxide and silicon nitride.
[0061] In one possible implementation, the material for making the first oxide layer 105 is silicon dioxide.
[0062] In summary, the trench oxide layer structure is provided in the present application, a step difference is formed between the first oxide layer and the first polysilicon layer below the trench oxide layer structure through the isolation layer, the morphology of the first polysilicon layer is adjusted, and then the technical problem of the risk of gate leakage or even the short circuit leakage of the gate and the source polysilicon caused by the fact that the thickness of the inter-electrode oxide is much smaller than the thickness of the shielding oxide layer in the prior art is overcome, the risk of gate leakage is improved, and the reliability of the gate is improved.
[0063] Similar to the idea of the previous embodiment, the present application also provides a shielding gate trench type semiconductor, which comprises the trench oxide layer structure according to any one of the above.
[0064] Based on this, the shielding gate trench type semiconductor provided in the present application has smaller gate leakage and stronger gate reliability, and the coupling capacitance between the gate and the separate gate, i.e., the gate input capacitance (Ciss) can be reduced by controlling the thickness of the isolation oxide layer.
[0065] Further, the manufacturing method of the shielding gate trench type semiconductor provided in the present application is described below.
[0066] First, refer to Figure 5 , Figure 5 An example of a preparation schematic provided in the present application is that a deep trench 102 is etched on an epitaxial layer 101, and then a thermal oxidation process is performed, and then a shielding oxide layer, i.e., a first oxide layer 105, is made on the surface of the trench 102, and the preferred material of the first oxide layer 105 is silicon dioxide. It should be noted that, please continue to refer to Figure 5 , at the same time as the first oxide layer 105 on the surface of the trench 102, a shielding oxide layer will also grow on the surface of the epitaxial layer 101.
[0067] Next, refer to Figure 6 , Figure 6 An example of a preparation schematic provided in the present application is that a deep trench 102 is etched on an epitaxial layer 101, and then a thermal oxidation process is performed, and then a shielding oxide layer, i.e., a first oxide layer 105, is made on the surface of the trench 102, and the preferred material of the first oxide layer 105 is silicon dioxide.
[0068] It should be noted that the present application does not limit the height of the first polysilicon layer 103, which can be adaptively adjusted according to the process requirements of the preparer. In one possible implementation, the difference between the surface of the first polysilicon layer 103 and the surface of the epitaxial layer 101 is greater than or equal to 0.9 microns, and less than or equal to 3 microns.
[0069] Please refer to Figure 5 , on the basis of Figure 7 , Figure 7This is a third exemplary fabrication diagram provided for an embodiment of the present invention. A barrier layer 108 is grown on the first polysilicon layer 103. The barrier layer 108 fills the trench 102 and covers the first oxide layer 105 on the surface of the trench 102. Then, please refer to... Figure 8 , Figure 8 The fourth exemplary fabrication diagram provided for the present utility model embodiment shows that, in order to ensure that the thickness of the first oxide layer 105 remains unchanged, the barrier layer 108 can be etched to a specified thickness by adjusting the etching selectivity ratio of the barrier layer 108 and the first oxide layer 105. In one possible implementation, the thickness of the barrier layer 108 is not less than 0.2 μm.
[0070] Next, please Figure 8 Based on, refer to Figure 9 , Figure 9 The fifth exemplary fabrication diagram provided in this utility model embodiment shows that the etching selectivity ratio of the barrier layer 108 and the first oxide layer 105 is adjusted, and the first oxide layer 105 is etched to the command height so that the surface of the first oxide layer 105 is higher than the surface of the first polysilicon layer 103 and lower than the surface of the barrier layer 108, forming a groove in the epitaxial layer 101.
[0071] Please Figure 9 Based on, refer to Figure 10 , Figure 10 The sixth exemplary fabrication diagram provided for this embodiment of the present invention shows that the barrier layer 108 is removed by a wet process to obtain an inverted stepped structure. This stepped structure includes at least two layers, which are a first layer 201 and a second layer 202 from bottom to top along the direction away from the surface of the first polysilicon layer 103. The width of the second layer 202 is greater than the width of the first layer 201.
[0072] In one possible implementation, the wet etching solution in this embodiment may be a hot phosphoric acid solution.
[0073] Subsequently, reference Figure 11 , Figure 11 The seventh exemplary fabrication diagram provided for this utility model embodiment shows that TEOS is deposited in the inverted stepped structure to form an isolation layer 107, that is, by utilizing its pore-filling properties, it fills the grooves on the shielding oxide layer and forms a nearly flat surface. For example, the height or depth of the isolation layer 107 can be adjusted according to the length of the deep trench 102.
[0074] Subsequently, it is possible Figure 11 Based on this, the conventional shielding trench 102 process is carried out to obtain the following: Figure 12 The shielded gate trench semiconductor 20 shown further includes a source contact region 109, a body region 110, a source metal 111, an interlayer dielectric layer 112, and a source contact hole 113.
[0075] In summary, the application can form a step difference between the separation gate and the shielding layer through the blocking layer, and then adjust the shielding layer process and the isolation layer process, optimize the gate polysilicon morphology, and then improve the gate leakage and the gate high temperature reliability.
[0076] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not limited to them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A trench oxide layer structure, characterized in that, The trench oxide layer structure comprises: an epitaxial layer; wherein the epitaxial layer is provided with a trench; a first polysilicon layer, a second polysilicon layer and an oxide layer filled in the trench; the oxide layer comprises a first oxide layer, a second oxide layer and an isolation layer; the first polysilicon layer is below the second polysilicon layer; the second oxide layer is provided around the second polysilicon layer; the isolation layer is provided between the first polysilicon layer and the second polysilicon layer, so that there is a step difference between the first oxide layer and the first polysilicon layer; the first oxide layer is provided around the first polysilicon layer and part of the isolation layer; wherein the surface of the first oxide layer is higher than the surface of the first polysilicon layer.
2. The trench oxide structure of claim 1, wherein The isolation layer comprises a stepped structure; the contact surface between the stepped structure and the first polysilicon layer is a first contact surface; the contact surface between the stepped structure and the second polysilicon layer is a second contact surface; the projection area of the first contact surface on the plane of the epitaxial layer is smaller than the projection area of the second contact surface on the plane of the epitaxial layer.
3. The trench oxide structure of claim 2, wherein The stepped structure comprises at least two layers, and from bottom to top along the direction away from the surface of the first polysilicon layer, the two layers are a first layer and a second layer in sequence. The width of the second layer is greater than the width of the first layer.
4. The trench oxide structure of claim 3, wherein The ratio between the thickness of the first layer and the width of the first layer is greater than or equal to 1.
5. The trench oxide structure of claim 3 or 4, wherein the trench oxide structure is formed in a semiconductor substrate. The thickness of the first layer is greater than or equal to 0.2 microns.
6. The trench oxide structure of claim 1, wherein, The material of the first oxide layer is a combination of any one or more of silicon oxide and silicon nitride.
7. The trench oxide structure of claim 1 or 6, wherein The material of the first oxide layer is silicon dioxide.
8. The trench oxide structure of claim 1, wherein, The width of the second polysilicon layer is greater than the width of the first polysilicon layer.
9. The trench oxide structure of claim 1, wherein, The difference between the surface of the first polysilicon layer and the surface of the epitaxial layer is greater than or equal to 0.9 microns and less than or equal to 3 microns.
10. A shielded gate trench semiconductor, characterized in that, The trench oxide layer structure comprises any one of claims 1 to 9. The trench oxide layer structure comprises any one of claims 1 to 9.